parameterized-design

Here are 6 public repositories matching this topic...

FLASHICON / multi-port-ram-register-file

Register file with one synchronous write port and several independent read ports, modeled in SystemVerilog like a small SRAM. Each read port decodes its own address, so multiple reads and a write complete in the same cycle. Parameterized width, depth and port count, with assertions and Yosys synthesis.

asic fpga verilog systemverilog computer-architecture alu gtkwave vlsi digital-design verilator arithmetic-logic-unit rtl-design yosy parameterized-design

Updated Nov 4, 2026

FLASHICON / parameterized-8-bit-alu

Star

Synthesis-ready parameterized 8-bit ALU in SystemVerilog with 10 arithmetic, logic, shift and comparison operations. Verified with Verilator and GTKWave, synthesized with Yosys.

asic fpga verilog systemverilog hardware-designs computer-architecture alu gtkwave vlsi yosys digital-design verilator arithmetic-logic-unit rtl-design parameterized-design

Updated Nov 1, 2026

mohamed-abdulraziq / Parameterized-Systolic-Matrix-Multiplier

Star

Parameterized output-stationary N×N systolic matrix multiplier in SystemVerilog, featuring signed MAC processing elements, operand/control skew, stall support, ordered result collection, self-checking verification, and synthesis reports.

mac asic matrix-multiplication synthesis systemverilog computer-architecture functional-verification rtl-design hardware-accelerator systolic-array processing-element parameterized-design

Updated Nov 2, 2026
SystemVerilog

shreekanthkapparagaon / parameterized-apb3-slave

Star

Parameterized AMBA APB3 Slave Peripheral in Verilog with configurable register bank, reusable APB Master BFM, and self-checking verification environment.

asic fpga verification rtl verilog gtkwave vlsi iverilog digital-design apb rtl-design bus-protocol apb3 parameterized-design

Updated Jul 5, 2026
Verilog

mohamed-abdulraziq / Parameterized-APB-Interconnect

Star

Parameterized single-master, multi-slave AMBA APB interconnect in SystemVerilog, featuring an IDLE/SETUP/ACCESS bridge, configurable RAM slaves, byte strobes, protection and address error handling, and self-checking verification.

fpga vivado systemverilog memory-mapped interconnect amba apb functional-verification rtl-design bus-protocol parameterized-design self-checking-testbench

Updated Nov 2, 2026
SystemVerilog

venkatalakshmilanda / parameterized_register_file

Star

A parameterized Verilog Register File featuring synchronous write, dual asynchronous read ports, configurable data width and memory depth, along with a comprehensive testbench for functional verification.

asic fpga verilog vlsi testbench digitaldesign rtl-design hardware-design registerfile parameterized-design

Updated Oct 3, 2026
Verilog

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