self-checking-testbench

Here are 4 public repositories matching this topic...

yeseo01 / Vending-Machine

Verilog vending-machine RTL with balance-register state handling and a self-checking testbench covering 232 specification checks.

verification rtl verilog digital-logic iverilog vending-machine digital-systems hardware-design self-checking-testbench

Updated Sep 24, 2026
Verilog

markjustinimmanuel2018-svg / Verification-Fundamentals

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Phase-2 Cycle-3: Verification Fundamentals

randomization assertions constrained-random-verification functional-coverage class-based-verification cross-coverage self-checking-testbench

Updated Aug 30, 2026
SystemVerilog

mohamed-abdulraziq / Parameterized-APB-Interconnect

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Parameterized single-master, multi-slave AMBA APB interconnect in SystemVerilog, featuring an IDLE/SETUP/ACCESS bridge, configurable RAM slaves, byte strobes, protection and address error handling, and self-checking verification.

fpga vivado systemverilog memory-mapped interconnect amba apb functional-verification rtl-design bus-protocol parameterized-design self-checking-testbench

Updated Nov 2, 2026
SystemVerilog

lla7wel / fpga-ripple-carry-adder

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1-bit full adder + 4-bit ripple-carry adder in VHDL — verified on Basys 3 hardware, in Vivado simulation, and exhaustively in CI with self-checking GHDL testbenches

fpga continuous-integration vhdl vivado digital-logic ghdl basys3 self-checking-testbench

Updated Jul 24, 2026
VHDL

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