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processing-element

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AliGhorbani1380 / AI-based-Neural-Network-Processing-Unit

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Welcome to the repository for **Exercise 3 of the AI Systems Course** at the **University of Tehran**. This project focuses on designing and implementing a lightweight, efficient **processing element (PE)** for performing operations of neurons in a **multi-layer perceptron (MLP)** using Verilog.

fpga neural-network verilog mlp hardware-acceleration ai-systems fpga-programming processing-element
  • Updated May 5, 2025
  • Verilog

mohamed-abdulraziq / Parameterized-Systolic-Matrix-Multiplier

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Parameterized output-stationary N×N systolic matrix multiplier in SystemVerilog, featuring signed MAC processing elements, operand/control skew, stall support, ordered result collection, self-checking verification, and synthesis reports.

mac asic matrix-multiplication synthesis systemverilog computer-architecture functional-verification rtl-design hardware-accelerator systolic-array processing-element parameterized-design
  • Updated Nov 2, 2026
  • SystemVerilog

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