Tiny SoC for learning the DFT flow with Tessent Shell 2022.4: Memory BIST, IJTAG and OCC insertion. Planned to be taken through synthesis, scan/ATPG and P&R to GDSII.
design-pattern dft rtl verilog vlsi design-for-testability occ verilog-project vlsi-design vlsi-designing mbist rtl-design tessent ijtag design-for-test vlsi-testing rtl-to-gdsii design-for-testability--dft
-
Updated
Nov 2, 2026 - Tcl