AI-assisted FPGA development across AMD Vivado, Anlogic TangDynasty, and Intel Quartus.
This repository showcases the projects I developed for the DE10-Lite board as part of the "FPGA Capstone: Building FPGA Projects" course on Coursera.
Blockdiagramm is a graphical block design tool for IC design
MATLAB code for the lab sessions in the "ASIC for DSP" course at LiU-ISY
The design and verification of a 2 Channel DMA Controller. With Various tests for read writes of each channel using the Round Robin logic.
蓝桥杯 FPGA 设计与开发（AMD/Xilinx 平台）国一工程模板与零基础教学资源库，涵盖完整驱动库、真题解析、模拟赛代码和入门资料
Collection of Verilog HDL RTL designs including combinational, arithmetic, sequential circuits, counters, shift registers, and FSM implementations.
Verilog implementation of a CNN-style image processing pipeline with convolution, activation, pooling, and RTL-based verification.
Verilog implementations of a 4-bit adder using behavioral, dataflow, and structural modeling styles, along with corresponding testbenches and block diagrams. This project demonstrates the design and simulation of digital adders as part of an academic lab experiment.
FPGA-based Hardware PUF implementation on Shrike FPGA using Verilog, SPN architecture, UART & SHA-256 for secure device authentication.
SHA1 Hardware Accelerator on Intel MAX 10 DECA using Nios II + SystemVerilog
FPGA-based solar-powered EV charging station with FSM-based charge control and MPPT implementation for efficient energy management. Designed in Verilog with ModelSim validation. Achieves real-time control, reduced peak demand, and improved battery health; accepted as a CRC Press/Taylor & Francis book chapter.
hardware-oriented audio processing project implemented in VHDL with a small Python WAV preprocessing/postprocessing pipeline
Verilog/Quartus FPGA labs and final vending machine project for Intro to FPGA Design
Development of waveform generator in spartan 6 FPGA using Numato Mimas v2 development board
Parameterizable FPGA-based Smart Home Automation Controller in Verilog HDL featuring PWM lighting and fan control, sensor-driven automation, security alarms, scene management, FSM-based control logic, waveform verification, and FPGA implementation workflow.
FPGA-based CNN accelerator for real-time breast tumour classification on AMD Kria KV260. Achieves 1472 FPS — 19.5× faster than CPU — at 85.47% accuracy using MobileNetV2, Vitis HLS, and PYNQ.
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