This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)
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Oct 19, 2023 - SystemVerilog
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async-fifo
Here are 24 public repositories matching this topic...
Dual-clock FIFO with a clock domain crossing subsystem, written in SystemVerilog. Gray code pointers pass through two-stage synchronizers, so the write and read sides run on unrelated clocks without metastability trouble. Full and empty flags and assertions are checked in multi-clock Verilator simulation.
asic verilog synchronizer systemverilog hardware-designs gtkwave fifo cdc vlsi yosys digital-design verilator metastability gray-code clock-domain-crossing rtl-design async-fifo
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Nov 3, 2026
Coverage-driven verification of an asynchronous FIFO across independent write and read clocks, using constrained-random stimulus, a reference scoreboard, CDC checks, assertions and cross coverage in SystemVerilog.
asic verification assertions scoreboard systemverilog fifo cdc vlsi uvm constrained-random clock-domain-crossing async-fifo coverage-driven-verification
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Nov 6, 2026
Learn independent UVM checking with APB-UART, async FIFOs, and reproducible fault-injection examples.
verification uart systemverilog fault-injection fifo modelsim uvm iverilog sva apb design-verification functional-coverage async-fifo
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Nov 4, 2026 - SystemVerilog
UVM-based SystemVerilog testbench for CDC & Async FIFO: SVA assertions, functional coverage, agents/sequences/scoreboard, and VCS/Questa run scripts.
makefile verification vcs systemverilog fifo cdc uvm testbench sva metastability functional-coverage async-fifo questa-sim
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Aug 22, 2025 - SystemVerilog
The repository documents my exploration of essential communication protocols in digital systems. I acknowledge the YouTube channel "All About VLSI" for their insightful workshops and sessions that supported my understanding of protocols
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Mar 23, 2026 - C++
Async FIFO verification using UVM testbench
async fifo uvm testbench system-verilog sv system-verification uvm-verification async-fifo testbench-verification system-verilog-codes system-verilog-testbench uvm-testbench
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Sep 29, 2026 - SystemVerilog
UVM testbenches in SystemVerilog: adder, async FIFO (CDC + SVA), UART RX with AXI-Lite RAL, NVMe reliability (AES, CRC, parity) and PCIe Gen4 TLP to NVMe hand-off, run on Verilator
crc uart systemverilog cdc nvme uvm testbench pcie verilator sva design-verification functional-coverage axi-lite async-fifo uvm-ral virtual-sequence
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Oct 18, 2026 - SystemVerilog
Parameterized asynchronous FIFO with Gray-code CDC, self-checking verification, fault injection, and clock-ratio regression.
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Aug 13, 2026 - SystemVerilog
Parameterized asynchronous FIFO UVM 1.2 verification platform with boundary, CDC, and reset regression.
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Jul 20, 2026 - SystemVerilog
A parameterizable Asynchronous FIFO RTL design verified using a custom UVM-style Object-Oriented testbench. Features 100% functional coverage, cycle-accurate timing, and SystemVerilog Assertions (SVA) for CDC protocol compliance.
fpga verification fifo cdc vlsi testbench verilog-hdl digital-design systemverilog-hdl clock-domain-crossing functional-verification asic-design rtl-design uvm-verification async-fifo
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May 16, 2026 - SystemVerilog
Learning-oriented asynchronous FIFO RTL with CDC constraints, wrappers, simulation/formal checks, and PYNQ-Z2 demo
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Jun 27, 2026 - SystemVerilog
Parameterized dual-clock asynchronous FIFO designed in Verilog for safe Clock Domain Crossing (CDC). Implements Gray-code pointer encoding, 2-flip-flop synchronizers, and conservative full/empty flag logic following Cummings SNUG 2002 architecture. Verified with a 600-line self-checking reference testbench and SVA protocol assertions across 7 test.
verilog icarus-verilog cdc vlsi yosys digital-design clock-domain-crossing async-fifo systemverilog-assertions
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Jul 22, 2026 - Verilog
UVM verification of an Asynchronous FIFO with SVA assertions, and functional coverage
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Jun 2, 2026 - SystemVerilog
Multi-Channel DMA Subsystem & Parameterized Dual-Clock Async CDC FIFO with APB & AXI4 Master Burst Interfaces in SystemVerilog.
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Aug 19, 2026 - SystemVerilog
Dual-clock asynchronous FIFO in Verilog (Cummings): Gray-code pointers with 2-flop synchronisers, verified in Verilator across clock ratios with randomised traffic.
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Sep 28, 2026 - SystemVerilog
ITCH parser v3 - Async FIFO with gray code CDC. 100% reliability. Code reduction: 677→395 lines (41% simpler).
fpga vhdl xilinx low-latency protocol-parser production-ready cdc trading-systems gray-code nasdaq-itch artix-7 async-fifo
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Jan 24, 2026 - VHDL
Clock-domain-crossing verification: a dual-clock asynchronous FIFO with Gray pointers and 2-flop synchronizers, checked across two independent clocks with cocotb. Verified on Icarus Verilog.
python hardware verification rtl synchronizer systemverilog cdc verilator metastability clock-domain-crossing cocotb async-fifo riscv-verification
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Oct 2, 2026 - Python
CDC-safe asynchronous FIFO in SystemVerilog with Gray pointers, 2FF synchronizers, SVA, and reproducible simulation/synthesis flows.
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Feb 23, 2026 - Verilog
Asynchronous FIFO - dual-clock gray-pointer FIFO in Verilog with industry-style structure
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May 24, 2026 - Verilog
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