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1. async-fifo async-fifo Public

   Dual-clock asynchronous FIFO in Verilog (Cummings): Gray-code pointers with 2-flop synchronisers, verified in Verilator across clock ratios with randomised traffic.

   SystemVerilog

2. fpga-market-data-pipeline fpga-market-data-pipeline Public

   Low-latency FPGA market data pipeline in Verilog: 64-bit AXI-Stream Ethernet/IPv4/UDP receive path and MoldUDP64/ITCH 5.0 parser, verified with cocotb and synthesised with Yosys/nextpnr.

   Verilog