(Original readme for the template repository here)

Here is a very small implementation of the first Project Euler problem on an ASIC using only 0.1mm x 0.1mm area.

Making it's way to silicon is possible thanks to TinyTapeout Project, I highly recommend it for your first tapeout!

To run the testbench you need to go to the src directory and run make, you need Icarus Verilog to execute the simulation.

To build the 100um x 100um macro you need OpenLane installed.