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  • 06:20 (UTC +01:00)

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  1. risc_v risc_v Public

    RV32I RISC-V instruction set CPU implementation

    SystemVerilog

  2. RISC_V_32I RISC_V_32I Public

    RISC V microarchitecture SystemVerilog implementation

    SystemVerilog

  3. UART UART Public

    UART Controller with transmitter and receiver functionality

    SystemVerilog

  4. BERT_FPGA BERT_FPGA Public

    Bit Error Rate Tester Project

    Verilog

  5. STM32-Retro-Game STM32-Retro-Game Public

    C