UVM-based functional verification of an APB-based UART Master Core RTL. Includes multi-agent environment, assertions, coverage collection, and multiple test scenarios (full/half duplex, parity, framing, timeout errors) achieving 100% functional coverage and protocol compliance.
fpga eda uart systemverilog vlsi uvm testbench digital-design serial-communication apb functional-verification hardware-verification rtl-design rtl-verification uvm-environment
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Updated
Nov 1, 2025 - SystemVerilog