AXI4-Lite slave in SystemVerilog that exposes control, configuration, status and data registers to a bus master. It handles the five independent channels with proper VALID and READY handshakes, decodes addresses, and returns OKAY or error responses. A master model and protocol assertions verify it in Verilator.
asic verilog systemverilog gtkwave soc vlsi yosys digital-design verilator axi amba axi4 axi4-lite amba-axi rtl-design bus-protocol register-map slave-interface
-
Updated
Nov 4, 2026