risc-v-processor

Here are 10 public repositories matching this topic...

akira2963753 / Pipelined-RV32-SoC

32-bit Pipelined RISC-V CPU Based on RV32I & RV32M including Forwarding, Hazard, Flush, Brach Predictor and two L1 Cache to transmiss data with BRAM using the AXI bus.

cpu fpga riscv risc-v rv32i riscv32 rv32im riscv-cpu rv32m risc-v32 risc-v-processor

Updated Sep 15, 2026
SystemVerilog

GSTL-ITU / HORNET-RV32IMF

Star

A 5-stage pipelined RV32IMF RISC-V SoC optimized for FPGA (Nexys Video/4-DDR). Features a custom IEEE-754 FPU, interrupt-driven UART, and various peripherals.

fpga verilog educational vivado computer-architecture itu soc verilog-hdl risc-v fpu nexys-video axi4-lite rv32imf edge-ai risc-v-architecture risc-v-processor fpu32 nexys-4-ddr

Updated Nov 2, 2026
C

muhammadtalhasami / RV32I_Single_Cycle

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This repository contains an implementation of a RV32I fetch pipeline microprocessor. The RV32I is a 32-bit RISC-V instruction set architecture, with the 'I' extension indicating the base integer instructions.

Updated Aug 10, 2024
Verilog

Pranav-2045 / riscv-5stage-pipelined-matmul

Star

Synthesizable 5-stage pipelined RV32I processor in Verilog featuring full hazard handling (forwarding, load-use stalls, branch flushes) and an integrated 64-cycle 4×4 matrix multiplication coprocessor.

python matrix-multiplication verilog computer-architecture icarus-verilog hardware-acceleration instruction-set-architecture rv32i processor-design forwarding-unit custom-assembler pipelined-processor risk-v risc-v-processor 32-bit-processor gtk-wave verilog-2001 hazard-handling

Updated Oct 7, 2026
HTML

afrozsahar04 / FPGA-based-RISC-V-Processor-Customizable-for-AI-Applications

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FPGA-implemented RISC-V processor, evolved from single-cycle to 5-stage pipelined architecture for higher performance and timing efficiency. BRAM-based instruction memory optimizes FPGA usage. Fully FPGA-ready, general-purpose yet tailorable for any AI application, demonstrated with an ML heart rate anomaly detector for wearable AI.

machine-learning python3 embedded-systems assembly-language computer-architecture linear-regression-models digital-design rv32i semiconductor-devices fpga-programming vlsi-design rtl-design hardware-design cmos-circuits hardware-software-codesign risc-v-processor application-specific-integrated-circuits digital-design-and-computer-architecture

Updated Feb 22, 2026
Verilog

gfoot / gf-rv16

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Experimental 16-bit RISC-V like ISA for a homebrew CPU

riscv risc-v riscv-sim riscv-asm riscv-simulator riscv-emulator risc-v-assembly riscv-assembly homebrew-cpu risc-v-emulator riscv-assembler riscv-cpu risc-v-architecture risc-v-simulator risc-v-processor

Updated Jul 8, 2026
Python

francisvalguedes / cyclone-fpga-riscv-sdram-pwm

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RISC-V (Nios V) SoC para placas genéricas Cyclone IV (EP4CE6, EP4CE10, EP4CE15) com controlador SDRAM, bootloader via SPI e módulo PWM (com Testbench) em VHDL

Updated Aug 19, 2026
SystemVerilog

Pathfinder1996 / computer-architecture-homework

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1131 NTU CSIE Computer Architecture Homework

verilog risc-v risc-v-assembly risc-v-processor

Updated Nov 16, 2025
Verilog

ellectroid / RISC-V-MCU-Flash-Loader-FE310-Red-V

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A RISC-V MCU Flash loader: FE310 + QSPI Flash IS25LP032D Red-V Board

flash assembly loader jlink riscv risc-v openocd rv32i riscv32 rv32imc qspi fe310 qspi-flash risc-v-assembly rv32ima rv32i-processor risc-v-processor flash-loader

Updated Jul 13, 2026
C

prabhatpps / RV32I_Single-Cycle_32-bit_RISC-V_Processor

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A complete RV32I single-cycle processor implemented in Verilog. This is a straightforward, educational implementation where all five pipeline stages (fetch, decode, execute, memory, writeback) happen in one clock cycle.

microprocessor risc-v vlsi-design rtl-design single-cycle-processor risc-v-processor single-cycle-core-riscv-processor

Updated Mar 10, 2026
Verilog

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