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MJoergen / HyperRAM

Star

Portable HyperRAM controller

fpga vhdl intel xilinx vivado altera lattice modelsim questasim avalon quartus artix questa hyperram

Updated Dec 8, 2024
VHDL

axi-security / eXpect

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Formal AXI verification properties from the eXpect framework for secure SoC validation

verification eda systemverilog soc formal-verification axi amba hardware-security questa axi4 axi4-lite hardware-design

Updated Oct 28, 2024
SystemVerilog

rfdonnelly / docker-questa

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A Docker image for Mentor/Siemens Questa

docker docker-image siemens mentor questa

Updated Sep 26, 2023
Shell

MJoergen / Avalon

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Utilities for Avalon Memory Map

fpga memory intel xilinx vivado altera modelsim questasim avalon quartus questa

Updated Jun 16, 2026
VHDL

gopro-uvm-rtl-verification / AXI4-Interconnect-Fabric-Verification-with-UVM

Star

Synthesizable AXI4 crossbar with a full UVM verification environment — RTL, SVA, coverage, stress, and CI.

ci verification rtl vcs systemverilog uvm qos arbitration backpressure sva crossbar questa axi4 jerkins uvm-verification hardware-validation

Updated Aug 21, 2025
SystemVerilog

LockBall / floatfixlib_VHDL1993

Star

ieee_proposed with names changed to floatfixlib to be compatible with Quartus Prime Lite and support fixed, float, etc.

vhdl modelsim float fixed quartus de10-lite questa floatfixlib ieee-proposed

Updated Oct 25, 2023
VHDL

gopro-uvm-rtl-verification / RISC-V-CPU-Core-UVM-Based-ISA-Compliance-Verification

Star

RV32IM RISC-V CPU core with a full UVM verification environment and ISA-compliance via Spike (DPI-C): constrained-random, SVA, coverage, Python debug tools, and CI.

python jenkins cpu processor verification dpi spike riscv isa vcs systemverilog uvm constrained-random sva rv32im questa functional-coverage

Updated Aug 20, 2025
SystemVerilog

saivittalb / simd-processor-verification

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✅ Formal verification of a 16-bit SIMD processor

linux makefile tcl verilog systemverilog questa systemverilog-assertions questa-propcheck

Updated Feb 1, 2023
Verilog

Abdelrahman1810 / RTL-Verification-of-AMBA3_4-APB-Protocol

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This repository contains the digital design and verification of the AMBA3 (Advanced Microcontroller Bus Architecture) and AMBA4 APB (Advanced Peripheral Bus) protocols.

tcl verilog systemverilog questasim questa verfication degital-design

Updated Aug 26, 2024
SystemVerilog

abdo-ehab-euv / sram-controller-uvm-verification

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SystemVerilog and UVM verification of an 8x8 SRAM memory controller with coverage, scoreboard, regression scripts, and bug-demo dashboard.

python tcl verification rtl scoreboard sram regression-testing systemverilog modelsim uvm testbench constrained-random memory-controller questa hardware-verification functional-coverage uvm-verification directed-testing design-verification-project

Updated May 14, 2026
SystemVerilog

Tharunreddym / riscv-pipeline-verification

Star

UVM-based verification environment for a 5-stage RV32I RISC-V pipeline using constrained-random testing, DPI-C golden reference modeling, assertions, scoreboarding, functional coverage, and 20-seed QuestaSim regression debugging.

c-plus-plus verification verilog scoreboard regression-testing systemverilog uvm constrained-random risc-v asic-verification questa dpi-c functional-coverage rtl-verification pipeline-verification

Updated May 19, 2026
SystemVerilog

AUDIY / Questa_Verification_Tutorials

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Examples for 「Questa-Altera FPGA Starter Editionで始めるRTL検証」

verification verilog systemverilog questasim verilog-hdl systemverilog-hdl sva questa

Updated Apr 18, 2026
Verilog

sashakatne / nvfp4-dotprod-formal-dv

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Formal (VC Formal FPV) and UVM verification of an 8-lane mixed-precision INT8/BF16/NVFP4 dot-product core, with a shared SystemVerilog golden reference across assertions and scoreboards.

eda rtl systemverilog uvm formal-verification int8 sva dot-product questa hardware-verification mixed-precision design-verification bfloat16 nvfp4 vc-formal assume-guarantee

Updated Jul 4, 2026
SystemVerilog

ScottyB55 / I2C_Chip_Verification

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UVM verification environment for an I2C controller (constrained-random + assertions + functional coverage) — Questa/ModelSim

asic i2c verification systemverilog modelsim uvm sva questa functional-coverage

Updated Jan 9, 2026
VHDL

Assaf-Afriat / uvm-crc-8-16

Star

Configurable CRC-8/16 RTL with full UVM verification (SystemVerilog, QuestaSim). Serial and parallel modes.

fpga verification rtl crc systemverilog uvm questa

Updated Mar 5, 2026
SystemVerilog

flfl04 / SPI_Verilog

Star

This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.

rtl verilog vivado questa

Updated Jun 13, 2024

Tharunreddym / sram-uvm-verification

Star

SRAM subsystem verification using SystemVerilog UVM, SVA assertions, scoreboard, functional coverage, and 20-seed QuestaSim regression evidence from EDA Playground.

assertions scoreboard sram regression-testing systemverilog uvm constrained-random digital-design questa functional-coverage eda-playground verification-environment

Updated May 19, 2026
SystemVerilog

Tharunreddym / axi4-verification

Star

AXI4 Memory Controller UVM Verification Environment with real Siemens Questa seed-1 simulation logs, scoreboard checks, functional coverage summaries, and documented burst-read debug fix.

python scoreboard regression-testing systemverilog uvm constrained-random semiconductor digital-design sva questa axi4 functional-coverage rtl-verification eda-playground

Updated May 19, 2026
SystemVerilog

sashakatne / Team3_AsyncFIFO_S24_ECE593

Star

Design and UVM verification of a 64-entry 8-bit asynchronous FIFO for clock-domain crossing (80 MHz write / 50 MHz read) — Gray-coded pointers, two-flop synchronizers, wrap-aware full/empty flags, a reset-aware scoreboard, functional coverage, and Questa farm evidence. ECE 593 team project.

rtl systemverilog cdc uvm gray-code clock-domain-crossing questa hardware-verification design-verification asynchronous-fifo functional-coverage

Updated May 26, 2026
SystemVerilog

petr-plihal / cpu-for-brainfuck

Star

Procesor ve VHDL pro jazyk Brainfuck

embedded makefile vhdl brainfuck ghdl questa hardware-simulation cpu-design processor-simulation

Updated Jun 22, 2025
VHDL

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Here are 30 public repositories matching this topic...

MJoergen / HyperRAM

axi-security / eXpect

rfdonnelly / docker-questa

MJoergen / Avalon

gopro-uvm-rtl-verification / AXI4-Interconnect-Fabric-Verification-with-UVM

LockBall / floatfixlib_VHDL1993

gopro-uvm-rtl-verification / RISC-V-CPU-Core-UVM-Based-ISA-Compliance-Verification

saivittalb / simd-processor-verification

Abdelrahman1810 / RTL-Verification-of-AMBA3_4-APB-Protocol

abdo-ehab-euv / sram-controller-uvm-verification

Tharunreddym / riscv-pipeline-verification

AUDIY / Questa_Verification_Tutorials

sashakatne / nvfp4-dotprod-formal-dv

ScottyB55 / I2C_Chip_Verification

Assaf-Afriat / uvm-crc-8-16

flfl04 / SPI_Verilog

Tharunreddym / sram-uvm-verification

Tharunreddym / axi4-verification

sashakatne / Team3_AsyncFIFO_S24_ECE593

petr-plihal / cpu-for-brainfuck

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