Projeto e síntese lógica de uma Unidade Lógica e Aritmética (ULA) parametrizável em SystemVerilog utilizando Synopsys Design Compiler (Tecnologia SAED32).
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Jul 22, 2026 - Verilog
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design-compiler
Here are 9 public repositories matching this topic...
12th-order complex RLS self-interference cancellation Soft IP with FPGA prototyping, ASIC-portable RTL, ModelSim convergence and DC optimization evidence.
asic fpga verilog systemverilog digital-signal-processing modelsim rls full-duplex self-interference-cancellation design-compiler
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Jul 30, 2026 - Verilog
The RISCV project was converted from RTL code to GDS II format using 14nm PDKs. This was implemented with the ICC2 and Design Compiler NXT EDA tools from Synopsys, following a Flat Design Style
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Jun 3, 2025 - Verilog
An RTL-to-GDSII ASIC Flow Project Design, simulate, synthesize, and layout a full 1×8 demux for 8-bit data — all the way from Verilog to GDSII.
asic rtl verilog synthesis hdl vlsi digital-design demux icc2 floorplanning hardware-design clock-tree-synthesis rtl-to-gdsii design-compiler
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Jun 4, 2025
Projeto introdutório de síntese lógica de uma porta AND em SystemVerilog utilizando o Synopsys Design Compiler com a biblioteca SAED32.
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Jul 22, 2026 - Tcl
ETC10123 laboratory portfolio: SPI Master RTL, synthesis, Formality, ICC2 physical design, weekly labs, and release-backed reports.
verilog spi synopsys formality hcmus electronic-design-automation physical-design icc2 asic-design rtl-verification design-compiler etc10123
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Aug 23, 2026 - Shell
🎯 AI PPT Design Compiler — 从用户需求到可编辑 PowerPoint 的本地化演示文稿设计引擎。模块化页面渲染器、结构化 Schema、Design Planner、PPTX 输出。
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Aug 14, 2026 - Python
Functional Verification, ASIC Synthesis and Formal Verification of an AMBA Memory Interface Bridge integrated with the LEON3 Processor and GRETH Ethernet MAC.
asic software-testing formal-verification leda amba-apb design-compiler amba-ahb standalone-testing bridge-module
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Jun 28, 2026 - C
ETC10122 coursework: dual-port RAM RTL, self-checking verification, ASIC-flow evidence, exercises, and a worked 2020 exam.
verilog vlsi formality hcmus electronic-design-automation physical-design icc2 asic-design rtl-design typst rtl-verification design-compiler integrated-circuit-design dual-port-ram etc10122
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Aug 29, 2026 - Verilog
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