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o2: the identity register on the shared 1-wire bus, plus front LEDs and activity lights - #358
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The O2 carried its own 1-wire state machine, CRC and MAC-to-ROM builder next to the w1 module the Octane uses, and MACE's flash/NIC register was split between a stub cell and that model. Replace both with one device for the whole register, ported from the QEMU model: flash enable, the identity line to a w1::Bus holding the board's DS2502, and the two front LED bits. The line is two bits, so the device times each low pulse on the guest clock and hands the finished reset or slot to the bus. It keeps the QEMU model's structure but not its absolute datasheet windows: the PROM's delay loops are counted in emulated instructions, so a fast emulator (jitv2, a fast host) runs them short, and a pulse outside a window was ignored, which left the Ethernet address reading as all ff. A low of at least 300 us is a reset, at least 30 us a zero, anything shorter a one, and a part's zero holds the line until the next slot. READ ROM, SKIP ROM and READ MEMORY replies are byte-for-byte what the old model sent, and a test pins them. The register trace and the protocol log go; the monitor keeps an onewire status line. Snapshots keep the register, as the QEMU model does. Differences: READ STATUS and READ DATA/CRC now answer as the shared DS2502 does.
The identity register already holds the red and green LED bits. Have the device set or clear the status bar's persistent red and green LED bits on every write, reset and load, and give the O2 display that heartbeat instead of the zero it passed. An LED lights when its bit is clear: the O2 register description in docs/datasheets/o2-prom-probe-registers.md says the register resets with green disabled and that writing zero enables both outputs. That is the datasheet's reading, not a hardware measurement. Observed in a boot to login: the PROM writes 0x00 (both lit), pulses flash enable, then writes 0x3c and straight away 0x1c (red dark, green lit). IRIX only toggles flash enable afterwards, to write the environment, so a booted machine shows green. The status bar itself could not be checked: the screenshot command captures a REX3 framebuffer the O2 does not have.
The O2 display now reads the shared activity word for the front LEDs, but the SCSI and Ethernet parts never set their bits, so those lights stayed dark. Give the word to both AIC-7880 controllers and the MEC, as the Octane does for its controllers and Ethernet. The controllers set the light for the target a command runs against, for ids 0 to 5, whichever bus it is on. The Ethernet sets transmit when frames go out and receive when one is delivered to the guest.
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The O2 version of what #351 did for the Octane.
w1::Bus, ported from my QEMU model, so the O2 and Octane use the same DS2502 and the O2's own 1-wire state machine and CRC code go.One thing worth knowing: the PROM times its 1-wire pulses with delay loops, and under jitv2 or on a fast host those loops run faster than real hardware, so every pulse comes out shorter than the 1-wire spec says. Checking each pulse against the spec's timing windows rejected them, and the Ethernet address read back as all
ff. The device now drops the windows' upper limits and classifies by length alone: at least 300 µs is a reset, at least 30 µs a zero, anything shorter a one. READ ROM, SKIP ROM and READ MEMORY replies are byte-for-byte what the old model sent, and a test pins them.Tested on the O2 under the interpreter and jitv2:
nvram eaddris right, and boot time is unchanged.