[h4rm0n1c]

Integrates #41, #43, #44, #56, #57 and #58 while preserving their original commits and authorship. Adds corrective patches so larger frame dimensions, flipped rows and ESP32 support work together, and keeps ESP8266 core 3 display refresh out of interrupt context.

Changes:

• Clear the Countdown textbox between numbers; widen framebuffer dimensions, byte strides and indexing.
• Correct narrow/partial-row indexing, scrolling boundaries and logical readback/copies of flipped rows.
• Refresh ESP32 displays in a worker task with current core 2/core 3 PWM APIs, idempotent lifecycle, stock SPIDMD destruction cleanup, explicit core 2 PWM channel ownership, invalid-output-pin rejection and SPI transactions held through latching.
• Carry the hardware-tested cooperative ESP8266 core 3 backend; retain AVR/Due refresh behaviour and ESP8266 default pins.
• Add sanitizer-backed framebuffer regressions and Uno/Countdown/ESP8266/ESP32 build checks.

Validation:

• Complete candidate builds for Uno, the original AVR Countdown example, ESP8266 core 3, and ESP32 Arduino 2.0.17/3.3.12.
• Address/UndefinedBehavior Sanitizer checks pass at 15 framebuffer sizes, including 255/256-pixel boundaries, partial rows, 2048-pixel width, copies, scrolling and flip readback. The uncorrected widened-dimension candidate reproduced a zero-stride heap overflow at 2048 pixels.
• Complete candidate on the original ESP32 passes all 15 dimension checks, startup/lifecycle checks and 12 HTTP stop/start cycles with a competing SPI task, followed by 838 successful HTTP requests/zero failures over 30s. Serial capture through 100s shows no panic/WDT or stop violations; camera shows RUN correctly. Earlier corrective-candidate core 2/core 3 runs also passed 20 destruction cycles, two-instance lifecycle and 1802 HTTP requests with zero failures. Core 2 independent PWM duties were checked.
• Earlier ESP8266 hardware runs covered indexing, scroll/flip corrections and Wi-Fi coexistence. Camera checks covered ESP32 brightness, blank-on-stop and restored output.

Limits: no eight-panel chain or new AVR physical validation; not every issue #40 variant was reproduced. ESP32 second-instance lifecycle used unwired GPIOs, and logical multi-row tests do not establish physical multi-row output. Competing SPI traffic is not a second peripheral protocol test. Other ESP32 variants, RTC/LDR and the clock application remain unvalidated. ESP32 SPIDMD copying is disabled to avoid duplicated hardware ownership; use DMDFrame snapshots. Core 2 external PWM users must reserve the selected channel and paired timer.

See README.md and tests/README.md for API restrictions, memory limits and repeatable checks.

For those who waited 6 years for a maintainer to work on this, sorry for the delay and thank you for your patience.