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Maximally simplified RISC-V CPU with fetch/decode/execute pipeline

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Name		Name	Last commit message	Last commit date
test_programs		test_programs
.gitignore		.gitignore
LICENSE		LICENSE
README.md		README.md
alu.v		alu.v
biu.v		biu.v
branch_predictor.v		branch_predictor.v
cpu.vh		cpu.vh
decode.v		decode.v
execute.v		execute.v
fastrom.v		fastrom.v
fetch.v		fetch.v
hazard_detector.v		hazard_detector.v
test.bat		test.bat
test.v		test.v

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riscv

Simplified RISC-V CPU with fetch/decode/execute pipeline

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Maximally simplified RISC-V CPU with fetch/decode/execute pipeline

3 stars

1 watching

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