Highlights
- Pro
Pinned Loading
-
Prolepsis-SoC
Prolepsis-SoC PublicProlepsis: An ISA-agnostic, RTL-based predictive Thermal Management Unit (TMU) for multicore processors, featuring Kalman-filter temperature forecasting.
SystemVerilog 1
-
hardware-debug-failure-learning
hardware-debug-failure-learning PublicResearch prototype for safe reuse of RTL root-cause analysis across repeated hardware failures.
Python
-
MobileNet-Accelerator-RTL
MobileNet-Accelerator-RTL Public🏆 Top 100 submission for the DVCon India 2026 Design Contest. A highly optimized, Verilog-based MobileNet Accelerator featuring a custom Systolic Array and on-the-fly Global Average Pooling.
Verilog
-
kairos-edge
kairos-edge PublicHardware-software co-designed framework for thermally aware and memory-efficient edge inference.
Python
-
AES128-LowPower-Architecture
AES128-LowPower-Architecture Public templateForked from tr0san/AES128bit
Low-power AES-128 hardware architecture in Verilog, achieving a 50% reduction in dynamic power through parallel duplication and architecture-driven voltage scaling.
Verilog
-
algorithmic-fairness-analysis
algorithmic-fairness-analysis PublicQuantifying and mitigating educational bias in gig economy routing algorithms using causal models and constrained optimization.
Python
If the problem persists, check the GitHub status page or contact support.




