[dependabot]

Updates the requirements on fearless_simd to permit the latest version.

Release notes

Sourced from fearless_simd's releases.

fearless_simd-v1.1.0

Crates.io | Docs

This release has an MSRV of 1.89.

Added

• Added concat_swizzle_dyn and concat_swizzle_dyn_precise for all non-mask vector types, selecting bytes from the concatenation of two vectors. Out-of-range indices produce implementation-defined values in the former and zero in the latter. (#354 by @​Shnatsel)
• Added compress, compress_merge, expand, and expand_merge for all integer and floating-point vector types. Compression packs mask-selected elements into consecutive low lanes, while expansion places consecutive low elements into mask-selected lanes. Both preserve element order; unused lanes are zeroed or taken from a merge vector. (#395 by @​Novum, @​Shnatsel, #412 by @​RunDevelopment)
• Added MaskWiden and MaskNarrow traits to widen and narrow mask lanes while preserving their boolean values. SimdWiden and SimdNarrow now also guarantee the corresponding conversions for a vector's associated mask, making them available in generic code. (#396, #399 by @​Shnatsel)
• Added SimdMask::from_vector, SimdMask::to_vector, and the associated Ints type for conversions between masks and signed integer vectors. True lanes map to -1 and false lanes to 0; other input values have unspecified behavior. (#400 by @​valadaptive, @​Shnatsel)
• Added lane-wise simd_ne for all vector and mask types. (#408 by @​Shnatsel)
• Added floating-point classification methods is_nan, is_infinite, is_finite, is_subnormal, is_normal, is_sign_positive, and is_sign_negative, returning a mask for each property. (#405 by @​RunDevelopment, @​Shnatsel)
• Added round for floating-point vectors, rounding to the nearest integer with ties away from zero. (#409 by @​RunDevelopment)
• Added to_degrees and to_radians for floating-point vectors. (#406 by @​RunDevelopment)

Changed

• mul_add_precise and mul_sub_precise now use shared SIMD emulation on SSE2 and WebAssembly as well as SSE4.2, improving performance on platforms without native fused multiply-add support. (#394 by @​valadaptive, @​Shnatsel)
• 512-bit dynamic swizzles now use vectorized decomposition on SSE4.2 and WebAssembly. The SSE4.2 swizzle_dyn_precise implementation has also been optimized, and its scalar fallback now avoids branches for unpredictable indices. (#354, #392 by @​Shnatsel)
• Precise f32-to-u32 conversion has been optimized on SSE4.2, and more 32-bit integer/float conversions use SIMD on SSE2. (#404 by @​Shnatsel)
• More 64-bit integer operations now use explicit SIMD implementations on x86 without AVX-512, including comparisons, min/max, multiplication, and right shifts. Multiplication and shifts by runtime values have also been optimized. (#407 by @​Shnatsel)
• Floating-point classification now uses simd_ne where beneficial to improve x86 code generation. (#408 by @​Shnatsel)
• Level::try_detect is now marked inline. (#411 by @​Dr-Emann)

Fixed

• Corrected the mul_add_precise and mul_sub_precise documentation to explain that WebAssembly does not unconditionally provide fused multiply-add support and these operations may be slower there. (#402 by @​valadaptive)

Full Changelog: fearless_simd-v1.0.0...fearless_simd-v1.1.0

Changelog

Sourced from fearless_simd's changelog.

[1.1.0][] (2026-10-06)

This release has an [MSRV][] of 1.89.

Added

• Added concat_swizzle_dyn and concat_swizzle_dyn_precise for all non-mask vector types, selecting bytes from the concatenation of two vectors. Out-of-range indices produce implementation-defined values in the former and zero in the latter. (#354[] by [@​Shnatsel][])
• Added compress, compress_merge, expand, and expand_merge for all integer and floating-point vector types. Compression packs mask-selected elements into consecutive low lanes, while expansion places consecutive low elements into mask-selected lanes. Both preserve element order; unused lanes are zeroed or taken from a merge vector. (#395[] by [@​Novum][], [@​Shnatsel][], #412[] by [@​RunDevelopment][])
• Added MaskWiden and MaskNarrow traits to widen and narrow mask lanes while preserving their boolean values. SimdWiden and SimdNarrow now also guarantee the corresponding conversions for a vector's associated mask, making them available in generic code. (#396[], #399[] by [@​Shnatsel][])
• Added SimdMask::from_vector, SimdMask::to_vector, and the associated Ints type for conversions between masks and signed integer vectors. True lanes map to -1 and false lanes to 0; other input values have unspecified behavior. (#400[] by [@​valadaptive][], [@​Shnatsel][])
• Added lane-wise simd_ne for all vector and mask types. (#408[] by [@​Shnatsel][])
• Added floating-point classification methods is_nan, is_infinite, is_finite, is_subnormal, is_normal, is_sign_positive, and is_sign_negative, returning a mask for each property. (#405[] by [@​RunDevelopment][], [@​Shnatsel][])
• Added round for floating-point vectors, rounding to the nearest integer with ties away from zero. (#409[] by [@​RunDevelopment][])
• Added to_degrees and to_radians for floating-point vectors. (#406[] by [@​RunDevelopment][])

Changed

• mul_add_precise and mul_sub_precise now use shared SIMD emulation on SSE2 and WebAssembly as well as SSE4.2, improving performance on platforms without native fused multiply-add support. (#394[] by [@​valadaptive][], [@​Shnatsel][])
• 512-bit dynamic swizzles now use vectorized decomposition on SSE4.2 and WebAssembly. The SSE4.2 swizzle_dyn_precise implementation has also been optimized, and its scalar fallback now avoids branches for unpredictable indices. (#354[], #392[] by [@​Shnatsel][])
• Precise f32-to-u32 conversion has been optimized on SSE4.2, and more 32-bit integer/float conversions use SIMD on SSE2. (#404[] by [@​Shnatsel][])
• More 64-bit integer operations now use explicit SIMD implementations on x86 without AVX-512, including comparisons, min/max, multiplication, and right shifts. Multiplication and shifts by runtime values have also been optimized. (#407[] by [@​Shnatsel][])
• Floating-point classification now uses simd_ne where beneficial to improve x86 code generation. (#408[] by [@​Shnatsel][])
• Level::try_detect is now marked inline. (#411[] by [@​Dr-Emann][])

Fixed

• Corrected the mul_add_precise and mul_sub_precise documentation to explain that WebAssembly does not unconditionally provide fused multiply-add support and these operations may be slower there. (#402[] by [@​valadaptive][])

[1.0.0][] (2026-09-21)

This release has an [MSRV][] of 1.89.

Added

• Added the optional #[simd] attribute in fearless_simd_macros 0.1.0 to annotate SIMD-generic functions. The first argument can be a SIMD token, vector, mask, reference, or user-defined wrapper implementing ExtractToken. The core library does not depend on the macro crate. (#347[], #383[] by [@​Shnatsel][])
• Added Native<S> to SimdFloatElement and SimdIntElement to select native-width vectors in scalar-generic code (#378[] by [@​Shnatsel][]).
• Added the public ExtractToken trait for SIMD tokens, vectors, masks, references, and user-defined wrappers.
• Added reverse for all SIMD vector and mask types. (#356[] by [@​Shnatsel][])
• Added rotate_elements_left and rotate_elements_right to mask types. Rotations wrap the offset, matching the existing non-mask vector operations. (#360[] by [@​Shnatsel][])
• Added lane-wise saturating_add and saturating_sub for all integer vector types and backends. (#352[] by [@​Shnatsel][])
• Added lane-wise count_ones and count_zeros operations for all integer vector types and backends. The result has the same vector type as the input, including for signed integers. (#345[] by [@​Shnatsel][])
• Added reduce_min, reduce_max, reduce_min_precise, and reduce_max_precise for all non-mask vector types. The precise floating-point variants ignore quiet NaNs, returning NaN only when all lanes are quiet NaNs; signaling NaNs have implementation-defined behavior. (#358[] by [@​Shnatsel][])
• Added reduce_sum and reduce_product for all non-mask vector types. Integer arithmetic wraps. Floating-point reductions use a fixed order that produces identical results across backends for a given vector type and lane count, except for NaN bit patterns. Summation limits each lane's contribution to at most log2(N) roundings for N lanes. (#357[], #361[] by [@​Shnatsel][])
• Added mul_add_precise and mul_sub_precise for floating-point vectors. They guarantee the infinite-precision product-plus-add rounded once, including on SIMD levels without hardware fused multiply-add instructions. They are not susceptible to the bug in Rust standard library, std::simd and musl libc that causes incorrect rounding for subnormal results. SSE4.2 gets SIMD emulation of these operations for better performance. (#323[], #324[] by [@​Shnatsel][])
• Documented the storage representation of the SIMD vector types. The documented representation will not change without a semver major version change. (#330[] by [@​danderson][])
• Added TryFrom bounds to SimdIntElement, allowing attempted conversion from all primitive integer types. (#335[] by [@​danderson][], [@​Shnatsel][])
• Added a security policy. Starting with v1.0, the latest Fearless SIMD version for each MSRV will receive security backports for at least three years after that Rust version was released. (#367[] by [@​Shnatsel][], [@​DJMcNab][])

Changed

... (truncated)

Commits

• b8a50a2 Release v1.1.0 (#413)
• dc7c0f0 Add mask<->vector conversion methods (#400)
• 02a29b3 Add pseudo code to compress*/expand* docs (#412)
• 10f7efa add inline to Level::try_detect (#411)
• 9dd8537 Add byte compress and expand operations (#395)
• 8f78c23 Add to_degrees and to_radians (#406)
• 0c9e682 Add simd_ne and use it internally where beneficial (#408)
• 0964602 Explicitly vectorize more operations on 64-bit integers on x86 without AVX-51...
• b619aa5 Add round (#409)
• 433ea83 Add float classification methods (#405)
• Additional commits viewable in compare view

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[dependabot]

Looks like fearless_simd is up-to-date now, so this is no longer needed.