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Emulator fidelity: reset, interrupts, Intel HEX, Mega and ATtiny85 configs - #30
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- Intel HEX: handle extended segment/linear records and checksums; add TryLoadHex. - Cpu.Reset clears the I/O space up to RamStart and resets every peripheral. - Interrupt entry takes 4 cycles (5 on 22-bit-PC parts); the instruction after SEI/RETI always runs before a pending interrupt. Per-CPU interrupt hooks. - AvrRunner carries its cycle target across calls (Run, RunUntil, RunCycles). - USART keeps RXC unless RXEN goes 1 to 0; write-one-to-clear flags in TIFR, ADCSRA, SPSR, TWCR, WDTCSR and EECR. - ATmega2560 configs in the core with the right OCx pins, channel C, ICP, INT0-7 and PCINT0-2; fast PWM channel C sets its pin at BOTTOM. - ATtiny85: EEARH at 0x3F, AvrAttinyTimer1 ported from avr8js. - ADC Avcc/Aref settable; EEPROM write time scales with the CPU frequency.
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Fixes from the audit of the CPU, the peripherals and the iCircuit (CircuitMirror) integration. Full list in the CHANGELOG
[Unreleased]section.Things that break real firmware
LoadHexignored record types 02/04, so a Mega sketch larger than 64 KB overwrote its own vectors. There is now a shared parser with checksum verification, plus a strictTryLoadHex.Cpu.Reset(): it is now a real reset. The I/O space up toRamStartgoes back to its reset values and every peripheral resets. Before, iCircuit's firmware-reload path could hangSerial.write.analogWriteon pins 4 and 9-13).Mega2560*Config, and the TestKit uses them.eeprom_write_bytethrew with interrupts on.timer-attiny.ts.Fidelity
Avcc/Arefare settable.API (additive)
TryLoadHex/HexInfo.Cpu.RamStart,AvrBuilder.WithRamStartandCpu.PreserveOnReset.OnInterruptDispatch/OnBreakpoint/OnSleep. The static hooks are now[Obsolete].AvrRunner.Run/RunUntil/RunCycles.AvrTimerConfig.CreateNew.AvrAttinyTimer1.ATtiny85Simulation.Timer1changes type to it.Behaviour changes a test may notice
sei.Reset().Verification
Avr8Sharp.Tests: 657/657 (was 583)TestKit.Samples: 73/73 (was 45)