diff --git a/.gitignore b/.gitignore
index 3a0c30d..c929cde 100644
--- a/.gitignore
+++ b/.gitignore
@@ -6,6 +6,8 @@ dist/
 wheels/
 *.egg-info
 .pytest_cache/
+.ruff_cache/
+data/
 
 # Virtual environments
 .venv
@@ -15,4 +17,6 @@ wheels/
 
 # sphinx
 docs/_build/
-docs/api/
\ No newline at end of file
+docs/api/
+*.mo
+.doctrees/
\ No newline at end of file
diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md
index d3dab86..8919127 100644
--- a/CONTRIBUTING.md
+++ b/CONTRIBUTING.md
@@ -4,36 +4,36 @@ Thank you for your interest in contributing to Tiny8! This guide will help you g
 
 Whether you're fixing a bug, adding a feature, improving documentation, or creating new assembly examples, your contributions are welcome and appreciated.
 
-## 🌟 Ways to Contribute
+## Ways to Contribute
 
-### 🐛 Bug Reports
+### Bug Reports
 - Search [existing issues](https://github.com/sql-hkr/tiny8/issues) first
 - Provide a clear description and minimal reproduction steps
 - Include your Python version and operating system
 - Add relevant code snippets or assembly programs
 
-### 💡 Feature Requests
+### Feature Requests
 - Open an issue describing the feature and its use case
 - Discuss design decisions before implementing large changes
 - Consider backward compatibility and educational value
 
-### 📝 Documentation
+### Documentation
 - Fix typos and improve clarity
 - Add more code examples
 - Enhance API documentation
 - Create tutorials or guides
 
-### 🎓 Assembly Examples
+### Assembly Examples
 - Create educational assembly programs
 - Document algorithms and implementation details
 - Add visualizations demonstrating key concepts
 
-### 🧪 Testing
+### Testing
 - Improve test coverage
 - Add edge case tests
 - Test on different platforms
 
-## 🚀 Getting Started
+## Getting Started
 
 ### Prerequisites
 
@@ -87,7 +87,7 @@ Whether you're fixing a bug, adding a feature, improving documentation, or creat
    tiny8 examples/fibonacci.asm
    ```
 
-## 🧪 Testing
+## Testing
 
 ### Running Tests
 
@@ -135,7 +135,7 @@ def test_feature_name():
     assert cpu.read_reg(16) == expected_value
 ```
 
-## 🎨 Code Style
+## Code Style
 
 ### Linting and Formatting
 
@@ -183,7 +183,7 @@ def execute_instruction(self, opcode: int, operands: list[int]) -> None:
     # Implementation
 ```
 
-## 📚 Documentation
+## Documentation
 
 ### Building Documentation
 
@@ -211,7 +211,7 @@ start _build/html/index.html  # Windows
 - Update `docs/index.rst` for significant features
 - Include code examples in docstrings when helpful
 
-## 🎯 Assembly Examples
+## Assembly Examples
 
 ### Creating Examples
 
@@ -251,7 +251,7 @@ done:
 - **Test coverage**: Add corresponding unit tests
 - **Documentation**: Reference in README or docs if significant
 
-## 🔄 Pull Request Process
+## Pull Request Process
 
 ### Before Submitting
 
@@ -300,14 +300,14 @@ Before submitting your PR, ensure:
 - [ ] Branch is up-to-date with main
 - [ ] No unrelated changes included
 
-## 🔍 Code Review Process
+## Code Review Process
 
 - Maintainers will review PRs within a few days
 - Address feedback constructively
 - Push additional commits to the same branch
 - Request re-review after addressing comments
 
-## 🌐 Community Guidelines
+## Community Guidelines
 
 ### Code of Conduct
 
@@ -323,7 +323,7 @@ Before submitting your PR, ensure:
 - **Discussions**: Use GitHub Discussions for questions and ideas
 - **Email**: For security issues only (see below)
 
-## 🔒 Security Issues
+## Security Issues
 
 If you discover a security vulnerability:
 
@@ -332,21 +332,21 @@ If you discover a security vulnerability:
 3. Provide detailed information about the vulnerability
 4. Allow time for a fix before public disclosure
 
-## 📄 License
+## License
 
 By contributing to Tiny8, you agree that your contributions will be licensed under the [MIT License](LICENSE).
 
 Your contributions will be attributed in the project's commit history and release notes.
 
-## ❓ Questions?
+## Questions?
 
 - Check the [documentation](https://sql-hkr.github.io/tiny8/)
 - Search [existing issues](https://github.com/sql-hkr/tiny8/issues)
 - Open a new issue for discussion
 - Join [GitHub Discussions](https://github.com/sql-hkr/tiny8/discussions)
 
-## 🙏 Thank You!
+## Thank You!
 
 Thank you for taking the time to contribute to Tiny8! Your efforts help make this project a better learning tool for everyone exploring computer architecture.
 
-Every contribution, no matter how small, makes a difference. We appreciate your support! ⭐
+Every contribution, no matter how small, makes a difference. We appreciate your support!
diff --git a/README.md b/README.md
index b4bd250..e0547a6 100644
--- a/README.md
+++ b/README.md
@@ -6,47 +6,62 @@
 [![CI](https://github.com/sql-hkr/tiny8/actions/workflows/ci.yml/badge.svg)](https://github.com/sql-hkr/tiny8/actions/workflows/ci.yml)
 [![codecov](https://codecov.io/github/sql-hkr/tiny8/graph/badge.svg?token=OBM58R8MCL)](https://codecov.io/github/sql-hkr/tiny8)
 
-> **An educational 8-bit CPU simulator with interactive visualization**
+> **From bare-metal computer architecture to Generative AI — an educational 8-bit AVR RISC CPU simulator with real-time interactive visualization**
 
-Tiny8 is a lightweight and educational toolkit for exploring the fundamentals of computer architecture through hands-on assembly programming and real-time visualization. Designed for learning and experimentation, it features an AVR-inspired 8-bit CPU with 32 registers, a rich instruction set, and powerful debugging tools — all with zero heavy dependencies.
+Tiny8 is a lightweight educational toolkit that bridges bare-metal computer architecture and modern Generative AI. Designed for hands-on learning and experimentation, it guides you through the full stack of computing — from 32 general-purpose registers, ALU operations, stack frames, and C compilation up to executing an iterative reverse-diffusion model synthesizing 28x28 MNIST digits directly on an AVR 8-bit RISC processor. With an interactive Vim-inspired terminal debugger, time-travel reverse execution, and a 32x32 TrueColor memory heatmap, Tiny8 lets you see, step through, and understand computation at every level.
 
 
 <div align="center">
-  <img src="https://github.com/user-attachments/assets/ffbcb2c4-2c3a-469f-b7b7-e6e86eb374da" alt="Animated bubble sort visualization" width="600">
-  <p><em>Real-time visualization of a bubble sort algorithm executing on Tiny8</em></p>
+  <img src="https://github.com/user-attachments/assets/bd3e88da-9bcb-4a41-bb9e-57d9d4e39bc6" alt="Native 28x28 Generative Diffusion synthesis executing at x5,000 speed in Tiny8 TUI" width="850">
+  <p><em>Real-time generative reverse-diffusion synthesis (MNIST digit 8) executing at x5,000 speed in Tiny8 TUI (HEX mode for weight/LFSR init &rarr; PIXEL mode for reverse denoising trajectory)</em></p>
 </div>
 
-## ✨ Features
+## Features
 
-### 🎯 **Interactive Terminal Debugger**
-<img width="600" src="https://github.com/user-attachments/assets/0bbd4382-806e-4b5a-af0b-54d83417fcfb" alt="CLI visualizer screenshot">
+### **Modern Textual TUI Debugger & Dashboard**
+- **Reactive Terminal Dashboard**: Real-time panels with gradient heatmap bars, SREG condition timeline, call stack, and memory dump
+- **Bottom statusline**: High-contrast mode badges (`NORMAL`, `RUNNING`, `INSERT`, `COMMAND`), file progress, and key hints (`h: help`)
+- **Interactive controls**: Step forward/back (`n`/`p`), continue (`c`), toggle breakpoint (`b`), play/pause (`Space`), speed control (`+`/`-`), TUI application help guide (`h` / `?`), and instruction inspector modal (`i`)
+- **Seamless Vim Editor**: Press `e` anytime to jump into the built-in editor, modify code, and hit `:run` to debug
 
-- **Vim-style navigation**: Step through execution with intuitive keyboard controls
-- **Change highlighting**: See exactly what changed at each step (registers, flags, memory)
-- **Advanced search**: Find instructions, track register/memory changes, locate PC addresses
-- **Marks and bookmarks**: Set and jump to important execution points
-- **Vertical scrolling**: Handle programs with large memory footprints
+### **Built-in Vim-Style Modal Editor**
+- **Standalone file creation & editing**: Run `tiny8` or `tiny8 my_prog.c` to create and edit files directly inside the terminal
+- **Complete Vim modes**:
+  - `NORMAL`: `h`/`j`/`k`/`l` movement, `w`/`b` word jump, `0`/`$` line limits, `gg`/`G` bounds, `x` delete char, `dd` delete line, `yy` yank, `p` paste, `u` undo, `Ctrl+r` redo
+  - `INSERT`: Full typing with syntax highlighting, line numbers, and `<Esc>` to return to normal mode
+  - `COMMAND` (`:`): `:w` (save), `:w <file>`, `:q` (exit), `:wq` / `:x` (save and run), `:run` (compile/assemble and launch debugger), `:e <file>` (switch file)
 
-### 🎬 **Graphical Animation**
-- Generate high-quality GIF/MP4 videos of program execution
-- Visualize register evolution, memory access patterns, and flag changes
-- Perfect for presentations, documentation, and learning materials
+### **32x32 Heatmap Memory Dump & Diffusion Synthesis**
+- **32x32 Heatmap Memory Grid (1024 Bytes)**: TrueColor gradient heatmap background mapped directly to memory (`0x0200`..`0x05FF` VRAM default), rendering 28x28 MNIST handwritten digits directly inside the memory dump with 1:1 pixel aspect ratio.
+- **Embedded Generative AI**: Iterative reverse-diffusion synthesis generating MNIST digits on Tiny8 AVR CPU (`tiny8 examples/diffusion_mnist8.asm`).
+- **Viridis & Grayscale Palettes**: Supports both colorful Viridis heatmap and realistic MNIST Grayscale pixel display modes (toggle with `g` for gray/viridis and `x` for hex/pixel).
+- **Sample Programs**: Native 28x28 diffusion generation (`tiny8 examples/diffusion_mnist8.asm`) showcasing real-time image synthesis on the 32x32 VRAM heatmap monitor.
 
-### 🏗️ **Complete 8-bit Architecture**
+### **Built-in C Compiler & Extensions**
+- **Compile and run C programs directly**: Write C code (`.c`) and execute on Tiny8 (`tiny8 program.c`)
+- **Enhanced C features**: Character literals (`'A'`, `'#'`), string literals, fixed-size arrays (`int arr[4];`), `for` loops, `break;`, logical `&&` and `||`, function calls, `peek()`/`poke()`, and VRAM helpers (`vram_set`, `vram_get`, `vram_puts`, `vram_clear`)
+- **Compile-to-assembly inspection**: Generate and inspect clean Tiny8 assembly with `-c` flag
+
+### **Optimized AVR Instruction Set**
+- **Extended SRAM Addressing**: `LDS Rd, k` (Load Direct from SRAM) and `STS k, Rr` (Store Direct to SRAM) for direct 16-bit address access
+- **16-bit Pointer Pairs**: Full support for pointer pairs `Z (R31:R30)`, `X (R27:R26)`, and `Y (R29:R28)` with `LD` and `ST` across the entire 64KB address space
+
+
+### **Complete 8-bit Architecture**
 - **32 general-purpose registers** (R0-R31)
 - **8-bit ALU** with arithmetic, logical, and bit manipulation operations
 - **Status register (SREG)** with 8 condition flags
-- **2KB address space** for unified memory and I/O
+- **64KB address space** for unified memory and I/O
 - **Stack operations** with dedicated stack pointer
-- **AVR-inspired instruction set** with 60+ instructions
+- **AVR instruction set** with 67 instructions compliant with Microchip DS40002198A
 
-### 📚 **Educational Focus**
+### **Educational Focus**
 - Clean, readable Python implementation
 - Comprehensive examples (Fibonacci, bubble sort, factorial, and more)
 - Step-by-step execution traces for debugging
 - Full API documentation and instruction set reference
 
-## 🚀 Quick Start
+## Quick Start
 
 ### Installation
 
@@ -83,24 +98,29 @@ done:
 
 Run it:
 ```bash
-tiny8 fibonacci.asm # Interactive debugger
-tiny8 fibonacci.asm -m ani -o fibonacci.gif # Generate animation
+tiny8 fibonacci.asm            # Interactive Textual debugger
+tiny8 examples/factorial.c     # Run C program directly in debugger
+tiny8 examples/factorial.c -c  # Print compiled Tiny8 assembly
 ```
 
 ### Python API
 
 ```python
-from tiny8 import CPU, assemble_file
+from tiny8 import CPU, assemble_file, compile_c
 
+# Run assembly program
 asm = assemble_file("fibonacci.asm")
 cpu = CPU()
 cpu.load_program(asm)
 cpu.run(max_steps=1000)
+print(f"Result: R17 = {cpu.read_reg(17)}")
 
-print(f"Result: R17 = {cpu.read_reg(17)}")  # Final Fibonacci number
+# Or compile and run C code directly!
+asm_from_c = compile_c("int main() { return 10 + 32; }")
 ```
 
-## 💡 Why Tiny8?
+
+## Why Tiny8?
 
 **For Students** — Write assembly, see immediate results with visual feedback. Understand how each instruction affects CPU state without abstractions.
 
@@ -108,7 +128,7 @@ print(f"Result: R17 = {cpu.read_reg(17)}")  # Final Fibonacci number
 
 **For Hobbyists** — Rapid algorithm prototyping at the hardware level with minimal overhead and an extensible, readable codebase.
 
-## 📖 Documentation
+## Documentation
 
 - [**Full Documentation**](https://sql-hkr.github.io/tiny8/) — Complete API reference and guides
 - [**Instruction Set Reference**](#instruction-set-reference) — All 60+ instructions
@@ -116,45 +136,55 @@ print(f"Result: R17 = {cpu.read_reg(17)}")  # Final Fibonacci number
 - [**Examples**](#examples) — Sample programs with explanations
 - [**Contributing**](CONTRIBUTING.md) — Guidelines for contributors
 
-## 🎮 Interactive CLI Controls
-
-The terminal-based debugger provides powerful navigation and inspection capabilities.
-
-### Navigation & Playback
-
-- `l` / `h` or `→` / `←` — Step forward/backward
-- `w` / `b` — Jump ±10 steps
-- `0` / `$` — Jump to first/last step
-- `Space` — Play/pause auto-execution
-- `[` / `]` — Decrease/increase playback speed
-
-### Display & Inspection
-
-- `r` — Toggle register display (all/changed only)
-- `M` — Toggle memory display (all/non-zero only)
-- `=` — Show detailed step information
-- `j` / `k` — Scroll memory view up/down
-
-### Search & Navigation Commands (press `:`)
-
-- `:123` — Jump to step 123
-- `:+50` / `:-20` — Relative jumps
-- `:/ldi` — Search forward for instruction "ldi"
-- `:?add` — Search backward for "add"
-- `:@0x100` — Jump to PC address 0x100
-- `:r10` — Find next change to register R10
-- `:r10=42` — Find where R10 equals 42
-- `:m100` — Find next change to memory[100]
-- `:fZ` — Find next change to flag Z
-
-### Marks & Help
-
-- `ma` — Set mark 'a' at current step
-- `'a` — Jump to mark 'a'
-- `/` — Show help screen
-- `q` or `ESC` — Quit
-
-## 🎓 Examples
+## Interactive CLI Controls
+
+The terminal debugger provides modern modal navigation and inspection capabilities.
+
+### Navigation & Execution Shortcuts
+
+- `n` / `p` — Step forward / backward (+1 / -1)
+- `c` — Continue run forward until next breakpoint, watchpoint, or program completion
+- `C` (Shift+C) — Reverse continue run backward until previous breakpoint or watchpoint
+- `b` — Toggle breakpoint at current PC
+- `Space` — Play / pause automatic step execution
+- `+` / `-` — Increase / decrease playback speed
+- `j` / `k` (or `J` / `K`) — Scroll memory dump down / up (by 32-byte line or fast 128-byte page)
+- `e` — Open full-screen Vim Editor for source code
+- `r` — Reset execution to step 0
+- `h` / `?` — Open TUI application usage & keyboard guide modal
+- `i` — Inspect specification & status details for the currently selected instruction
+- `q` — Quit debugger
+
+### Tabbed Views (Inspector & Telemetry)
+
+- **Registers & Memory** — Gradient heatmap bars for R0..R31 alongside 32x32 memory dump with TrueColor heatmap background (0x0200..0x05FF VRAM)
+- **C Variables** — Live symbol table tracking C variable names, types, memory addresses, hex/dec values, and update status
+- **Call Stack** — Dynamic function call backtrace reconstructed from execution calls and returns
+
+### Command Bar (press `:`)
+
+- `:<step>` or `:goto <step>` — Jump directly to step number
+- `:b <pc>` or `:break <pc>` — Toggle breakpoint at PC (`0x000E` or `14`)
+- `:b <pc> if <expr>` — Set conditional breakpoint (e.g. `:b 10 if R16 == 42`, `:b 0x12 if mem[0x60] > 0`)
+- `:bc` or `:clear` — Clear all breakpoints and conditional breakpoints
+- `:watch <expr>` or `:w <expr>` — Add watchpoint on register, memory address, or condition (e.g. `:watch R0`, `:watch mem[0x60]`)
+- `:unwatch [expr]` — Remove watchpoint or clear all watchpoints
+- `:mark <name>` — Create bookmark for current execution state
+- `:'<name>` or `:goto <name>` — Jump to bookmarked step
+- `:c` or `:run` — Continue execution to next breakpoint
+- `:rc` or `:rev` — Reverse continue execution backward
+- `:set R<n> <val>` — Live modify register value in current state (e.g. `:set R16 42`)
+- `:poke <addr> <val>` — Live modify memory value at address (e.g. `:poke 0x60 255`)
+- `:exec <instruction>` — Mini REPL: assemble and execute an instruction on the fly (e.g. `:exec LDI R17, 88`)
+- `:mem <addr>` or `:m <addr>` — Jump memory view to address (`0x0060`)
+- `:find <text>` — Search forward for instruction
+- `:e [file]` — Open Vim editor for file
+- `:r` or `:reset` — Reset to step 0
+- `:h` or `:help` — Show instruction reference modal
+- `:q` or `:quit` — Exit tiny8
+- `<Esc>` — Cancel command bar / close modal dialog
+
+## Examples
 
 The `examples/` directory contains programs demonstrating key concepts:
 
@@ -162,18 +192,17 @@ The `examples/` directory contains programs demonstrating key concepts:
 |---------|-------------|
 | `fibonacci.asm` | Fibonacci sequence using registers |
 | `bubblesort.asm` | Sorting algorithm with memory visualization |
-| `factorial.asm` | Recursive factorial calculation |
+| `diffusion_mnist8.asm` | Native 28x28 MNIST digit generation using an iterative reverse diffusion process |
 | `find_max.asm` | Finding maximum value in array |
 | `is_prime.asm` | Prime number checking algorithm |
 | `gcd.asm` | Greatest common divisor (Euclidean algorithm) |
 
 ### Bubble Sort
 
-Sort 32 bytes in memory:
+Sort 32 pseudo-random bytes in ascending order (RAM 0x60..0x7F):
 
 ```bash
-tiny8 examples/bubblesort.asm -ms 0x60 -me 0x80 # Watch live
-tiny8 examples/bubblesort.asm -m ani -o sort.gif -ms 0x60 -me 0x80   # Create GIF
+tiny8 examples/bubblesort.asm
 ```
 
 ### Using Python
@@ -188,166 +217,169 @@ cpu.run()
 print("Sorted:", [cpu.read_ram(i) for i in range(0x60, 0x80)])
 ```
 
-## 🔧 CLI Options
+## CLI Options
 
 ### Command Syntax
 
 ```bash
-tiny8 FILE [OPTIONS]
+tiny8 [FILE] [OPTIONS]
 ```
 
 ### General Options
 
 | Option | Description |
 |--------|-------------|
-| `-m, --mode {cli,ani}` | Visualization mode: `cli` for interactive debugger (default), `ani` for animation |
 | `-v, --version` | Show version and exit |
-| `--max-steps N` | Maximum execution steps (default: `15000`) |
+| `-e, --edit` | Launch directly into Vim editor mode |
+| `--max-steps N` | Maximum execution steps (default: until infinite loop or halt) |
+| `-c, --compile-only` | Compile C program and print generated Tiny8 assembly without running |
 
-### Memory Display Options
+### Interactive Controls (Textual TUI)
 
-| Option | Description |
-|--------|-------------|
-| `-ms, --mem-start ADDR` | Starting memory address (decimal or `0xHEX`, default: `0x00`) |
-| `-me, --mem-end ADDR` | Ending memory address (decimal or `0xHEX`, default: `0xFF`) |
+| Key | Action |
+|-----|--------|
+| `Space` | Play / Pause auto execution |
+| `Shift+Space` | Reverse playback auto execution |
+| `n` | Step forward (+1 instruction) |
+| `p` | Step backward (-1 instruction, time-travel) |
+| `c` | Continue execution forward to next breakpoint |
+| `C` (`Shift+c`) | Reverse continue backward to previous breakpoint |
+| `b` | Toggle breakpoint on current instruction |
+| `:` | Open command line prompt (e.g. `:goto <step>`, `:b <pc>`, `:q`) |
+| `j` / `k` (or `J` / `K`) | Scroll memory viewport down / up by 32 bytes (or 128-byte fast page) |
+| `g` | Toggle Grayscale / Viridis color palette |
+| `x` | Toggle Hexadecimal digits (02X) / Graphic Pixel blocks |
+| `m` | Cycle view modes (Viridis+Hex -> Viridis+Pixel -> Grayscale+Pixel -> Grayscale+Hex) |
+| `e` | Launch full-screen Vim-style modal editor |
+| `h` / `?` | Open TUI Application Usage & Keyboard Guide |
+| `i` | Open Instruction Reference modal (all 67 instructions) |
+| `+` / `-` | Increase / Decrease playback speed |
+| `r` | Reset execution back to step 0 |
+| `q` | Quit debugger |
 
-### CLI Mode Options
 
-| Option | Description |
-|--------|-------------|
-| `-d, --delay SEC` | Initial playback delay in seconds (default: `0.15`) |
-
-### Animation Mode Options
-
-| Option | Description |
-|--------|-------------|
-| `-o, --output FILE` | Output filename (`.gif`, `.mp4`, `.png`) |
-| `-f, --fps FPS` | Frames per second (default: `60`) |
-| `-i, --interval MS` | Update interval in milliseconds (default: `1`) |
-| `-pe, --plot-every N` | Update plot every N steps (default: `100`, higher = faster) |
 
-> **Windows**: CLI debugger requires WSL or `windows-curses`. Animation works natively.
 
-## 📋 Instruction Set Reference
+## Instruction Set Reference
 
-Tiny8 implements an AVR-inspired instruction set with 62 instructions organized into logical categories. All mnemonics are case-insensitive. Registers are specified as R0-R31, immediates support decimal, hex (`$FF` or `0xFF`), and binary (`0b11111111`) notation.
+Tiny8's instruction set strictly adheres to the official **[Microchip AVR® Instruction Set Manual (DS40002198A)](https://ww1.microchip.com/downloads/en/DeviceDoc/AVR-Instruction-Set-Manual-DS40002198A.pdf)**. All mnemonics are case-insensitive. Registers are specified as `R0`–`R31`, and immediates support decimal, hex (`0xFF`), and binary (`0b11111111`) notation.
 
 ### Data Transfer
 
-| Instruction | Description | Example |
-|-------------|-------------|---------|
-| `LDI Rd, K` | Load 8-bit immediate into register | `ldi r16, 42` |
-| `MOV Rd, Rr` | Copy register to register | `mov r17, r16` |
-| `LD Rd, Rr` | Load from RAM at address in Rr | `ld r18, r16` |
-| `ST Rr, Rs` | Store Rs to RAM at address in Rr | `st r16, r18` |
-| `IN Rd, port` | Read from I/O port into register | `in r16, 0x3F` |
-| `OUT port, Rr` | Write register to I/O port | `out 0x3F, r16` |
-| `PUSH Rr` | Push register onto stack | `push r16` |
-| `POP Rd` | Pop from stack into register | `pop r16` |
+| Instruction | Description (DS40002198A) | Operation | Example |
+|-------------|---------------------------|-----------|---------|
+| `LDI Rd, K` | Load Immediate | Rd ← K (16 ≤ d ≤ 31) | `ldi r16, 42` |
+| `MOV Rd, Rr` | Copy Register | Rd ← Rr | `mov r17, r16` |
+| `LD Rd, Rr` | Load Indirect from Data Space | Rd ← (Rr) | `ld r18, r26` |
+| `ST Rr, Rs` | Store Indirect to Data Space | (Rr) ← Rs | `st r26, r18` |
+| `LDS Rd, k` | Load Direct from Data Space | Rd ← (k) | `lds r16, 0x0200` |
+| `STS k, Rr` | Store Direct to Data Space | (k) ← Rr | `sts 0x0200, r16` |
+| `IN Rd, P` | Load an I/O Location to Register | Rd ← P | `in r16, 0x3F` |
+| `OUT P, Rr` | Store Register to an I/O Location | P ← Rr | `out 0x3F, r16` |
+| `PUSH Rr` | Push Register on Stack | STACK ← Rr, SP ← SP - 1 | `push r16` |
+| `POP Rd` | Pop Register from Stack | SP ← SP + 1, Rd ← STACK | `pop r16` |
 
 ### Arithmetic Operations
 
-| Instruction | Description | Example |
-|-------------|-------------|---------|
-| `ADD Rd, Rr` | Add registers | `add r16, r17` |
-| `ADC Rd, Rr` | Add with carry | `adc r16, r17` |
-| `SUB Rd, Rr` | Subtract registers | `sub r16, r17` |
-| `SUBI Rd, K` | Subtract immediate | `subi r16, 10` |
-| `SBC Rd, Rr` | Subtract with carry | `sbc r16, r17` |
-| `SBCI Rd, K` | Subtract immediate with carry | `sbci r16, 5` |
-| `INC Rd` | Increment register | `inc r16` |
-| `DEC Rd` | Decrement register | `dec r16` |
-| `MUL Rd, Rr` | Multiply (result in Rd:Rd+1) | `mul r16, r17` |
-| `DIV Rd, Rr` | Divide (quotient→Rd, remainder→Rd+1) | `div r16, r17` |
-| `NEG Rd` | Two's complement negation | `neg r16` |
-| `ADIW Rd, K` | Add immediate to word (16-bit) | `adiw r24, 1` |
-| `SBIW Rd, K` | Subtract immediate from word | `sbiw r24, 1` |
+| Instruction | Description (DS40002198A) | Operation | Flags | Example |
+|-------------|---------------------------|-----------|-------|---------|
+| `ADD Rd, Rr` | Add without Carry | Rd ← Rd + Rr | H, S, V, N, Z, C | `add r16, r17` |
+| `ADC Rd, Rr` | Add with Carry | Rd ← Rd + Rr + C | H, S, V, N, Z, C | `adc r16, r17` |
+| `ADIW Rd, K` | Add Immediate to Word | Rd+1:Rd ← Rd+1:Rd + K | S, V, N, Z, C | `adiw r24, 1` |
+| `SUB Rd, Rr` | Subtract without Carry | Rd ← Rd - Rr | H, S, V, N, Z, C | `sub r16, r17` |
+| `SUBI Rd, K` | Subtract Immediate | Rd ← Rd - K | H, S, V, N, Z, C | `subi r16, 10` |
+| `SBC Rd, Rr` | Subtract with Carry | Rd ← Rd - Rr - C | H, S, V, N, Z, C | `sbc r16, r17` |
+| `SBCI Rd, K` | Subtract Immediate with Carry | Rd ← Rd - K - C | H, S, V, N, Z, C | `sbci r16, 5` |
+| `SBIW Rd, K` | Subtract Immediate from Word | Rd+1:Rd ← Rd+1:Rd - K | S, V, N, Z, C | `sbiw r24, 1` |
+| `INC Rd` | Increment | Rd ← Rd + 1 | S, V, N, Z | `inc r16` |
+| `DEC Rd` | Decrement | Rd ← Rd - 1 | S, V, N, Z | `dec r16` |
+| `MUL Rd, Rr` | Multiply Unsigned | R1:R0 ← Rd × Rr | Z, C | `mul r16, r17` |
+| `MULS Rd, Rr` | Multiply Signed | R1:R0 ← Rd × Rr (signed) | Z, C | `muls r16, r17` |
+| `MULSU Rd, Rr` | Multiply Signed with Unsigned | R1:R0 ← Rd × Rr (Rd signed, Rr unsigned) | Z, C | `mulsu r16, r17` |
+| `NEG Rd` | Two's Complement Negation | Rd ← 0x00 - Rd | H, S, V, N, Z, C | `neg r16` |
 
 ### Logical & Bit Operations
 
-| Instruction | Description | Example |
-|-------------|-------------|---------|
-| `AND Rd, Rr` | Logical AND | `and r16, r17` |
-| `ANDI Rd, K` | AND with immediate | `andi r16, 0x0F` |
-| `OR Rd, Rr` | Logical OR | `or r16, r17` |
-| `ORI Rd, K` | OR with immediate | `ori r16, 0x80` |
-| `EOR Rd, Rr` | Exclusive OR | `eor r16, r17` |
-| `EORI Rd, K` | XOR with immediate | `eori r16, 0xFF` |
-| `COM Rd` | One's complement | `com r16` |
-| `CLR Rd` | Clear register (XOR with self) | `clr r16` |
-| `SER Rd` | Set register to 0xFF | `ser r16` |
-| `TST Rd` | Test for zero or negative | `tst r16` |
-| `SWAP Rd` | Swap nibbles (high/low 4 bits) | `swap r16` |
-| `SBI port, bit` | Set bit in I/O register | `sbi 0x18, 3` |
-| `CBI port, bit` | Clear bit in I/O register | `cbi 0x18, 3` |
+| Instruction | Description (DS40002198A) | Operation | Flags | Example |
+|-------------|---------------------------|-----------|-------|---------|
+| `AND Rd, Rr` | Logical AND | Rd ← Rd · Rr | S, V=0, N, Z | `and r16, r17` |
+| `ANDI Rd, K` | Logical AND with Immediate | Rd ← Rd · K | S, V=0, N, Z | `andi r16, 0x0F` |
+| `OR Rd, Rr` | Logical OR | Rd ← Rd ∨ Rr | S, V=0, N, Z | `or r16, r17` |
+| `ORI Rd, K` | Logical OR with Immediate | Rd ← Rd ∨ K | S, V=0, N, Z | `ori r16, 0x80` |
+| `EOR Rd, Rr` | Exclusive OR | Rd ← Rd ⊕ Rr | S, V=0, N, Z | `eor r16, r17` |
+| `COM Rd` | One's Complement | Rd ← 0xFF - Rd | S, V=0, N, Z, C=1 | `com r16` |
+| `CLR Rd` | Clear Register (Alias: EOR Rd, Rd) | Rd ← Rd ⊕ Rd | S=0, V=0, N=0, Z=1 | `clr r16` |
+| `SER Rd` | Set Register (Alias: LDI Rd, 0xFF) | Rd ← 0xFF | None | `ser r16` |
+| `TST Rd` | Test for Zero or Minus (Alias: AND Rd, Rd) | Rd ← Rd · Rd | S, V=0, N, Z | `tst r16` |
+| `SWAP Rd` | Swap Nibbles | Rd(7..4) ↔ Rd(3..0) | None | `swap r16` |
+| `SBI P, b` | Set Bit in I/O Register | I/O(P, b) ← 1 | None | `sbi 0x18, 3` |
+| `CBI P, b` | Clear Bit in I/O Register | I/O(P, b) ← 0 | None | `cbi 0x18, 3` |
 
 ### Shifts & Rotates
 
-| Instruction | Description | Example |
-|-------------|-------------|---------|
-| `LSL Rd` | Logical shift left | `lsl r16` |
-| `LSR Rd` | Logical shift right | `lsr r16` |
-| `ROL Rd` | Rotate left through carry | `rol r16` |
-| `ROR Rd` | Rotate right through carry | `ror r16` |
-
-### Control Flow
-
-| Instruction | Description | Example |
-|-------------|-------------|---------|
-| `JMP label` | Unconditional jump | `jmp loop` |
-| `RJMP offset` | Relative jump | `rjmp -5` |
-| `CALL label` | Call subroutine | `call function` |
-| `RCALL offset` | Relative call | `rcall -10` |
-| `RET` | Return from subroutine | `ret` |
-| `RETI` | Return from interrupt | `reti` |
-| `BRNE label` | Branch if not equal (Z=0) | `brne loop` |
-| `BREQ label` | Branch if equal (Z=1) | `breq done` |
-| `BRCS label` | Branch if carry set (C=1) | `brcs overflow` |
-| `BRCC label` | Branch if carry clear (C=0) | `brcc no_carry` |
-| `BRGE label` | Branch if greater/equal | `brge positive` |
-| `BRLT label` | Branch if less than | `brlt negative` |
-| `BRMI label` | Branch if minus (N=1) | `brmi negative` |
-| `BRPL label` | Branch if plus (N=0) | `brpl positive` |
-
-### Compare Instructions
-
-| Instruction | Description | Example |
-|-------------|-------------|---------|
-| `CP Rd, Rr` | Compare registers (Rd - Rr) | `cp r16, r17` |
-| `CPI Rd, K` | Compare with immediate | `cpi r16, 42` |
-| `CPSE Rd, Rr` | Compare, skip if equal | `cpse r16, r17` |
-
-### Skip Instructions
-
-| Instruction | Description | Example |
-|-------------|-------------|---------|
-| `SBRS Rd, bit` | Skip if bit in register is set | `sbrs r16, 7` |
-| `SBRC Rd, bit` | Skip if bit in register is clear | `sbrc r16, 7` |
-| `SBIS port, bit` | Skip if bit in I/O register is set | `sbis 0x16, 3` |
-| `SBIC port, bit` | Skip if bit in I/O register is clear | `sbic 0x16, 3` |
+| Instruction | Description (DS40002198A) | Operation | Flags | Example |
+|-------------|---------------------------|-----------|-------|---------|
+| `LSL Rd` | Logical Shift Left (Alias: ADD Rd, Rd) | Rd ← Rd ≪ 1 | H, S, V, N, Z, C | `lsl r16` |
+| `LSR Rd` | Logical Shift Right | 0 → Rd7 … Rd0 → C | S, V, N, Z, C | `lsr r16` |
+| `ASR Rd` | Arithmetic Shift Right | Rd7 → Rd7 … Rd0 → C | S, V, N, Z, C | `asr r16` |
+| `ROL Rd` | Rotate Left through Carry (Alias: ADC Rd, Rd) | C ← Rd7 … Rd0 ← C | H, S, V, N, Z, C | `rol r16` |
+| `ROR Rd` | Rotate Right through Carry | C → Rd7 … Rd0 → C | S, V, N, Z, C | `ror r16` |
+
+### Control Flow & Branches
+
+| Instruction | Description (DS40002198A) | Condition / Target | Flags | Example |
+|-------------|---------------------------|--------------------|-------|---------|
+| `JMP k` | Jump | PC ← k | None | `jmp loop` |
+| `RJMP k` | Relative Jump | PC ← PC + k + 1 | None | `rjmp -5` |
+| `CALL k` | Long Call to Subroutine | STACK ← PC + 1, PC ← k | None | `call function` |
+| `RCALL k` | Relative Call to Subroutine | STACK ← PC + 1, PC ← PC + k + 1 | None | `rcall -10` |
+| `RET` | Return from Subroutine | PC ← STACK | None | `ret` |
+| `RETI` | Return from Interrupt | PC ← STACK, I ← 1 | I | `reti` |
+| `BREQ k` | Branch if Equal | Z = 1 | None | `breq done` |
+| `BRNE k` | Branch if Not Equal | Z = 0 | None | `brne loop` |
+| `BRCS k` | Branch if Carry Set | C = 1 | None | `brcs overflow` |
+| `BRCC k` | Branch if Carry Clear | C = 0 | None | `brcc no_carry` |
+| `BRLO k` | Branch if Lower (Unsigned) | C = 1 (Alias for BRCS) | None | `brlo lower` |
+| `BRSH k` | Branch if Same or Higher (Unsigned) | C = 0 (Alias for BRCC) | None | `brsh same_or_higher` |
+| `BRGE k` | Branch if Greater or Equal (Signed) | S = 0 (N ⊕ V = 0) | None | `brge positive` |
+| `BRLT k` | Branch if Less Than (Signed) | S = 1 (N ⊕ V = 1) | None | `brlt negative` |
+| `BRMI k` | Branch if Minus | N = 1 | None | `brmi negative` |
+| `BRPL k` | Branch if Plus | N = 0 | None | `brpl positive` |
+
+### Compare & Skip Instructions
+
+| Instruction | Description (DS40002198A) | Operation | Flags | Example |
+|-------------|---------------------------|-----------|-------|---------|
+| `CP Rd, Rr` | Compare | Rd - Rr | H, S, V, N, Z, C | `cp r16, r17` |
+| `CPI Rd, K` | Compare with Immediate | Rd - K | H, S, V, N, Z, C | `cpi r16, 42` |
+| `CPSE Rd, Rr` | Compare Skip if Equal | Skip next if Rd = Rr | None | `cpse r16, r17` |
+| `SBRS Rd, b` | Skip if Bit in Register is Set | Skip next if Rd(b) = 1 | None | `sbrs r16, 7` |
+| `SBRC Rd, b` | Skip if Bit in Register is Cleared | Skip next if Rd(b) = 0 | None | `sbrc r16, 7` |
+| `SBIS P, b` | Skip if Bit in I/O Register is Set | Skip next if I/O(P, b) = 1 | None | `sbis 0x16, 3` |
+| `SBIC P, b` | Skip if Bit in I/O Register is Cleared | Skip next if I/O(P, b) = 0 | None | `sbic 0x16, 3` |
 
 ### MCU Control
 
-| Instruction | Description | Example |
-|-------------|-------------|---------|
-| `NOP` | No operation | `nop` |
-| `SEI` | Set global interrupt enable | `sei` |
-| `CLI` | Clear global interrupt enable | `cli` |
+| Instruction | Description (DS40002198A) | Operation | Flags | Example |
+|-------------|---------------------------|-----------|-------|---------|
+| `NOP` | No Operation | None | None | `nop` |
+| `SEI` | Set Global Interrupt Flag | I ← 1 | I | `sei` |
+| `CLI` | Clear Global Interrupt Flag | I ← 0 | I | `cli` |
 
 ### Status Register (SREG) Flags
 
-The 8-bit status register contains condition flags updated by instructions:
+The 8-bit Status Register (SREG) contains condition flags updated by ALU instructions according to exact formulas defined in **DS40002198A**:
 
-| Bit | Flag | Description |
-|-----|------|-------------|
-| 7 | **I** | Global interrupt enable |
-| 6 | **T** | Bit copy storage |
-| 5 | **H** | Half carry (BCD arithmetic) |
-| 4 | **S** | Sign bit (N ⊕ V) |
-| 3 | **V** | Two's complement overflow |
-| 2 | **N** | Negative |
-| 1 | **Z** | Zero |
-| 0 | **C** | Carry/borrow |
+| Bit | Flag | Name | DS40002198A Formula & Meaning |
+|-----|------|------|-------------------------------|
+| 7 | **I** | Global Interrupt Enable | Set by `SEI`, cleared by `CLI` |
+| 6 | **T** | Bit Copy Storage | Bit copy buffer for `BST` / `BLD` |
+| 5 | **H** | Half Carry Flag | Carry/borrow between bit 3 and bit 4 (BCD arithmetic) |
+| 4 | **S** | Sign Bit | True algebraic sign test: S = N ⊕ V |
+| 3 | **V** | Two's Complement Overflow | Set when signed arithmetic overflows range [-128, +127] |
+| 2 | **N** | Negative Flag | Set if MSB is 1 (N = R7) |
+| 1 | **Z** | Zero Flag | Set if result is zero (R == 0) |
+| 0 | **C** | Carry / Borrow Flag | Unsigned carry from MSB (R7) or borrow |
 
 Flags are used for conditional branching and tracking arithmetic results.
 
@@ -356,10 +388,10 @@ Flags are used for conditional branching and tracking arithmetic results.
 - **Comments**: Use `;` for line comments
 - **Labels**: Must end with `:` (e.g., `loop:`)
 - **Registers**: Case-insensitive R0-R31 (r16, R16 equivalent)
-- **Immediates**: Decimal (42), hex ($2A, 0x2A), binary (0b00101010)
+- **Immediates**: Decimal (42), hex (0x2A), binary (0b00101010)
 - **Whitespace**: Flexible indentation, spaces/tabs interchangeable
 
-## 🏗️ Architecture Overview
+## Architecture Overview
 
 ### CPU Components
 
@@ -372,11 +404,14 @@ Flags are used for conditional branching and tracking arithmetic results.
 ### Memory Map
 
 ```text
-0x0000 - 0x001F    Memory-mapped I/O (optional)
-0x0020 - 0xFFFF    Available RAM (stack grows downward from top)
+0x0000 - 0x001F    General-Purpose Registers (R0 - R31) / System Reserved
+0x0020 - 0x005F    I/O Registers (64 ports: 0x00 - 0x3F via IN/OUT)
+0x0060 - 0x01FF    User SRAM (general variables & arrays start at 0x0060)
+0x0200 - 0x05FF    32x32 Heatmap VRAM (1,024 bytes, writable visual memory)
+0x0600 - 0xFFFF    Extended User SRAM (general data, heap & downward-growing stack)
 ```
 
-## 🧪 Testing
+## Testing
 
 ```bash
 pytest                                    # Run all tests
@@ -384,17 +419,17 @@ pytest --cov=src/tiny8 --cov-report=html  # With coverage
 pytest tests/test_arithmetic.py           # Specific test file
 ```
 
-## 🤝 Contributing
+## Contributing
 
 Contributions welcome! See [CONTRIBUTING.md](CONTRIBUTING.md) for guidelines.
 
 **Areas for contribution**: New instructions, example programs, documentation, visualizations, performance optimizations.
 
-## 📄 License
+## License
 
 MIT License — see [LICENSE](LICENSE) for details.
 
-## 📞 Support
+## Support
 
 - **Issues**: [GitHub Issues](https://github.com/sql-hkr/tiny8/issues)
 - **Discussions**: [GitHub Discussions](https://github.com/sql-hkr/tiny8/discussions)
@@ -402,6 +437,6 @@ MIT License — see [LICENSE](LICENSE) for details.
 
 ---
 
-**Made with ❤️ for learners, educators, and curious minds**
+**Made for learners, educators, and curious minds**
 
-*Star ⭐ the repo if you find it useful!*
+*Star the repo if you find it useful!*
diff --git a/docs/Makefile b/docs/Makefile
index d4bb2cb..72ec676 100644
--- a/docs/Makefile
+++ b/docs/Makefile
@@ -4,7 +4,7 @@
 # You can set these variables from the command line, and also
 # from the environment for the first two.
 SPHINXOPTS    ?=
-SPHINXBUILD   ?= sphinx-build
+SPHINXBUILD   ?= $(shell command -v sphinx-build 2>/dev/null || echo "uv run sphinx-build")
 SOURCEDIR     = .
 BUILDDIR      = _build
 
@@ -12,7 +12,28 @@ BUILDDIR      = _build
 help:
 	@$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
 
-.PHONY: help Makefile
+.PHONY: help Makefile gettext update-po html html-ja html-en html-all apidoc
+
+html: html-all
+
+apidoc:
+	@uv run sphinx-apidoc -f -o api ../src/tiny8 2>/dev/null || true
+
+gettext: apidoc
+	@$(SPHINXBUILD) -b gettext "$(SOURCEDIR)" locales/pot $(SPHINXOPTS)
+
+update-po: gettext
+	sphinx-intl update -p locales/pot -l ja -d locales
+
+html-ja: apidoc
+	@$(SPHINXBUILD) -b html -D language=ja "$(SOURCEDIR)" "$(BUILDDIR)/html/ja" $(SPHINXOPTS)
+
+html-en: apidoc
+	@$(SPHINXBUILD) -b html -D language=en "$(SOURCEDIR)" "$(BUILDDIR)/html/en" $(SPHINXOPTS)
+
+html-all: html-en html-ja
+	@mkdir -p "$(BUILDDIR)/html"
+	@cp -f "$(SOURCEDIR)/_templates/root_index.html" "$(BUILDDIR)/html/index.html" 2>/dev/null || true
 
 # Catch-all target: route all unknown targets to Sphinx using the new
 # "make mode" option.  $(O) is meant as a shortcut for $(SPHINXOPTS).
diff --git a/docs/_static/.gitkeep b/docs/_static/.gitkeep
new file mode 100644
index 0000000..e69de29
diff --git a/docs/_templates/components/nav-languages.html b/docs/_templates/components/nav-languages.html
new file mode 100644
index 0000000..4527960
--- /dev/null
+++ b/docs/_templates/components/nav-languages.html
@@ -0,0 +1,11 @@
+<div class="sy-head-languages" style="display: inline-flex; align-items: center; margin-right: 0.5rem; font-size: 0.82rem; font-weight: 600; border: 1px solid var(--sy-c-border); border-radius: 6px; padding: 2px 6px; background: var(--sy-c-surface); height: 28px; z-index: 10; position: relative;">
+  {% if current_language == 'ja' %}
+    <a href="{{ en_page_url }}" onclick="try{localStorage.setItem('tiny8_docs_lang','en');}catch(e){}" style="color: var(--sy-c-text); text-decoration: none; opacity: 0.65; padding: 0 4px; display: inline-block; cursor: pointer;" onmouseover="this.style.opacity='1'" onmouseout="this.style.opacity='0.65'" title="Switch to English">EN</a>
+    <span style="opacity: 0.3; margin: 0 2px;">|</span>
+    <span style="color: var(--accent-9); padding: 0 4px;" title="日本語（現在の表示言語）">JA</span>
+  {% else %}
+    <span style="color: var(--accent-9); padding: 0 4px;" title="English (current language)">EN</span>
+    <span style="opacity: 0.3; margin: 0 2px;">|</span>
+    <a href="{{ ja_page_url }}" onclick="try{localStorage.setItem('tiny8_docs_lang','ja');}catch(e){}" style="color: var(--sy-c-text); text-decoration: none; opacity: 0.65; padding: 0 4px; display: inline-block; cursor: pointer;" onmouseover="this.style.opacity='1'" onmouseout="this.style.opacity='0.65'" title="日本語に切り替え">JA</a>
+  {% endif %}
+</div>
diff --git a/docs/_templates/partials/site-head.html b/docs/_templates/partials/site-head.html
new file mode 100644
index 0000000..b374ec8
--- /dev/null
+++ b/docs/_templates/partials/site-head.html
@@ -0,0 +1,43 @@
+{%- macro render_logo(src, classname) -%}
+  {%- if src and src.startswith(('https://', 'http://')) -%}
+    <img class="{{ classname }}" src="{{ src }}" alt="{{ project }}" height="28" loading="lazy" />
+  {%- elif src -%}
+    <img class="{{ classname }}" src="{{ pathto(src, 1) }}" alt="{{ project }}" height="28" loading="lazy" />
+  {%- elif logo_url -%}
+    <img class="{{ classname }}" src="{{ logo_url }}" alt="{{ project }}" height="28" loading="lazy" />
+  {%- endif -%}
+{%- endmacro -%}
+
+<div class="sy-head">
+  <div class="sy-head-blur"></div>
+  <div class="sy-head-inner sy-container mx-auto">
+    <a class="sy-head-brand" href="{% if theme_logo_target %}{{ theme_logo_target }}{% else %}{{ pathto(root_doc) }}{% endif %}">
+      {{ render_logo(theme_light_logo, 'light-logo') }}
+      {{ render_logo(theme_dark_logo, 'dark-logo') }}
+      <strong>{{ project }}</strong>
+    </a>
+    <div class="sy-head-nav" id="head-nav">
+      <nav class="sy-head-links"{% if theme_nav_links_align %} data-align={{ theme_nav_links_align }}{% endif %}>
+        {%- if theme_nav_links -%}
+          {% include "components/nav-links.html" %}
+        {%- endif -%}
+      </nav>
+      <div class="sy-head-extra flex items-center print:hidden">
+        {%- include "components/searchbox.html" -%}
+        {%- include "components/nav-versions.html" -%}
+        {%- include "partials/nav-socials.html" -%}
+      </div>
+    </div>
+    <div class="sy-head-actions flex items-center shrink-0 print:hidden">
+      {%- include "components/nav-languages.html" -%}
+      {%- include "components/theme-switch.html" -%}
+      <button class="md:hidden flex items-center js-menu" aria-label="Menu" type="button" aria-controls="head-nav" aria-expanded="false">
+        <div class="hamburger">
+          <span class="hamburger_1"></span>
+          <span class="hamburger_2"></span>
+          <span class="hamburger_3"></span>
+        </div>
+      </button>
+    </div>
+  </div>
+</div>
diff --git a/docs/_templates/root_index.html b/docs/_templates/root_index.html
new file mode 100644
index 0000000..bb1b367
--- /dev/null
+++ b/docs/_templates/root_index.html
@@ -0,0 +1,25 @@
+<!DOCTYPE html>
+<html lang="en">
+<head>
+  <meta charset="utf-8">
+  <title>Tiny8 Documentation</title>
+  <script>
+    (function() {
+      var saved = '';
+      try {
+        saved = localStorage.getItem('tiny8_docs_lang');
+      } catch (e) {}
+      var lang = saved || (navigator.language || navigator.userLanguage || 'en').toLowerCase();
+      var target = lang.startsWith('ja') ? 'ja/index.html' : 'en/index.html';
+      window.location.replace(target);
+    })();
+  </script>
+  <meta http-equiv="refresh" content="0; url=en/index.html">
+</head>
+<body style="font-family: system-ui, -apple-system, sans-serif; display: flex; align-items: center; justify-content: center; height: 100vh; margin: 0; background: #0a0a0a; color: #eee;">
+  <div style="text-align: center;">
+    <h1 style="font-size: 1.5rem; margin-bottom: 1rem;">Tiny8 Documentation</h1>
+    <p>Redirecting to <a href="en/index.html" style="color: #60a5fa;">English</a> / <a href="ja/index.html" style="color: #60a5fa;">日本語</a>...</p>
+  </div>
+</body>
+</html>
diff --git a/docs/architecture.rst b/docs/architecture.rst
index 4f7f9bb..e7973ec 100644
--- a/docs/architecture.rst
+++ b/docs/architecture.rst
@@ -6,162 +6,153 @@ This guide provides a detailed overview of the Tiny8 CPU architecture, including
 CPU Overview
 ------------
 
-Tiny8 implements a simplified 8-bit CPU architecture inspired by the AVR family (ATmega series). The design prioritizes educational clarity over cycle-accurate emulation, making it ideal for learning computer architecture fundamentals.
+Tiny8 implements an 8-bit RISC CPU architecture modeled directly after the Atmel / Microchip AVR instruction set architecture. Instruction semantics, flag behaviors, and operations strictly adhere to the official specification:
+
+* **Official Specification**: `Microchip AVR® Instruction Set Manual (DS40002198A) <https://ww1.microchip.com/downloads/en/DeviceDoc/AVR-Instruction-Set-Manual-DS40002198A.pdf>`_
+
+The design balances hardware realism with educational clarity, providing full visibility and interactive step debugging.
 
 Key Specifications
 ~~~~~~~~~~~~~~~~~~
 
 * **Word size**: 8 bits
 * **Registers**: 32 general-purpose 8-bit registers (R0-R31)
-* **Memory**: 2KB RAM (configurable)
-* **Stack**: Grows downward from high memory
-* **Instruction set**: ~60 instructions (AVR-inspired)
-* **Status register**: 8 flags (SREG)
+* **Memory**: 64KB RAM (configurable)
+* **Stack**: Grows downward from high memory (SP decrements on push)
+* **Instruction set**: 67 instructions compliant with AVR DS40002198A
+* **Status register**: 8 flags (SREG: I, T, H, S, V, N, Z, C)
 
 Register Architecture
 ---------------------
 
-General-Purpose Registers
-~~~~~~~~~~~~~~~~~~~~~~~~~
-
-Tiny8 has 32 general-purpose 8-bit registers, labeled **R0** through **R31**.
+In strict alignment with the **Microchip AVR® Instruction Set Manual (DS40002198A, Section 4)**, the CPU register file consists of 32 8-bit general-purpose working registers, labeled **R0** through **R31**. All 32 registers have direct, single-cycle access to the Arithmetic Logic Unit (ALU).
 
 .. code-block:: text
 
-   ┌─────────────────────────────────────┐
-   │  R0  │  R1  │  R2  │   ...  │  R31  │
-   ├──────┴──────┴──────┴────────┴───────┤
-   │     32 x 8-bit registers            │
-   └─────────────────────────────────────┘
-
-All registers are fully general-purpose - there are no dedicated accumulator, index, or pointer registers. However, some instructions may work only with specific register ranges:
-
-* **LDI (Load Immediate)**: Only works with R16-R31
-* **Most arithmetic/logic**: Works with any register R0-R31
-
-.. note::
-   While all registers are general-purpose, you may want to establish conventions in your programs (e.g., using R0-R15 for temporary values and R16-R31 for important data).
+   ┌────────────────────────────────────────────────────────────────────────┐
+   │                            AVR Register File                           │
+   ├──────────────────────────────────┬─────────────────────────────────────┤
+   │       R0 – R15 (General)         │     R16 – R31 (Upper Working)       │
+   ├──────────────────────────────────┼─────────────────────────────────────┤
+   │  R0   R1   ...   R14   R15       │  R16  R17  ...   R24   R25          │
+   └──────────────────────────────────┴─────────────────────────────────────┘
+                                      │  R26 (XL)   R27 (XH)  → X-register  │
+                                      │  R28 (YL)   R29 (YH)  → Y-register  │
+                                      │  R30 (ZL)   R31 (ZH)  → Z-register  │
+                                      └─────────────────────────────────────┘
+
+Register Organization & Special Functions
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+* **General Working Registers (R0–R15)**:
+  Operate with all two-register arithmetic, logical, and bit operations (e.g., ``ADD``, ``SUB``, ``AND``, ``OR``, ``EOR``, ``MOV``, ``CP``).
+* **Upper Registers (R16–R31)**:
+  Support direct immediate instructions (``LDI``, ``SUBI``, ``SBCI``, ``ANDI``, ``ORI``, ``CPI``) where an 8-bit constant :math:`K` is supplied in the instruction.
+* **16-bit Word Operand Pairs (R25:R24, X, Y, Z)**:
+  The word operations ``ADIW`` (Add Immediate to Word) and ``SBIW`` (Subtract Immediate from Word) operate exclusively on the upper register pairs:
+  * ``R25:R24``
+  * ``R27:R26`` (X-register)
+  * ``R29:R28`` (Y-register)
+  * ``R31:R30`` (Z-register)
+* **16-bit Pointer Registers (X, Y, Z)**:
+  Six registers (R26–R31) serve as three 16-bit indirect address pointers for Data Space memory addressing:
+  * **X-register**: ``XL = R26`` (low byte), ``XH = R27`` (high byte)
+  * **Y-register**: ``YL = R28`` (low byte), ``YH = R29`` (high byte)
+  * **Z-register**: ``ZL = R30`` (low byte), ``ZH = R31`` (high byte)
 
 Special Registers
 ~~~~~~~~~~~~~~~~~
 
-In addition to general-purpose registers, the CPU has several special registers:
-
 Program Counter (PC)
 ^^^^^^^^^^^^^^^^^^^^
 
-* Points to the current instruction in the program
-* Automatically increments after each instruction
-* Modified by branch, jump, and call instructions
-* **Width**: Depends on program size (virtual, not a physical register)
+* 16-bit program address pointer referencing instructions in program memory.
+* Automatically increments during sequential execution.
+* Modified by jump (``JMP``, ``RJMP``), subroutine call/return (``CALL``, ``RCALL``, ``RET``, ``RETI``), skip instructions (``CPSE``, ``SBRS``, ``SBRC``, ``SBIS``, ``SBIC``), and conditional branches (``BRxx``).
 
 Stack Pointer (SP)
 ^^^^^^^^^^^^^^^^^^
 
-* Points to the top of the stack in memory
-* Initialized to the end of RAM (default: 0x07FF with 2KB RAM)
-* Decrements on PUSH, increments on POP
-* Used implicitly by CALL and RET instructions
+* 16-bit stack pointer pointing to the current top of the stack in Data SRAM.
+* Initialized to the end of RAM (default: ``0xFFFF`` with 64KB RAM).
+* Decrements during ``PUSH``, ``CALL``, and ``RCALL`` (post-decrement).
+* Increments during ``POP``, ``RET``, and ``RETI`` (pre-increment).
 
 Status Register (SREG)
 ^^^^^^^^^^^^^^^^^^^^^^
 
-* 8-bit register containing condition flags
-* Updated by arithmetic, logic, and comparison instructions
-* Used by conditional branch instructions
+* 8-bit condition flag register containing flags: ``I``, ``T``, ``H``, ``S``, ``V``, ``N``, ``Z``, ``C``.
+* Updated by arithmetic, logical, and shift operations according to exact Boolean algebra defined in DS40002198A.
 
 .. code-block:: text
 
    SREG: [ I | T | H | S | V | N | Z | C ]
          Bit 7                         Bit 0
 
-See the `Status Flags`_ section for detailed flag descriptions.
-
-Memory Model
-------------
-
-Address Space
-~~~~~~~~~~~~~
+Memory Model & Addressing Modes
+-------------------------------
 
-Tiny8 uses a flexible, byte-addressable memory model with configurable RAM size.
-
-**Default Configuration:**
-
-* RAM size: 2048 bytes (2KB)
-* Address range: 0x0000 to 0x07FF
-* Stack pointer initializes to 0x07FF (ram_size - 1)
+Data Memory Space
+~~~~~~~~~~~~~~~~~
 
-**Memory Layout:**
+Tiny8 provides a flat, byte-addressable memory space modeled after AVR SRAM with configurable capacity (default: 65536 bytes / 64KB, addressable range ``0x0000`` to ``0xFFFF``).
 
 .. code-block:: text
 
-   0x07FF  ┌──────────────┐ ← SP (initial position)
-           │              │
-           │  Stack Area  │ Stack grows downward (PUSH decrements SP)
-           │              │
-           │ ↓ ↓ ↓ ↓ ↓ ↓  │
-           │              │
-           │              │
-           │   Free RAM   │ Available for program use
-           │              │
-           │              │
-           │ ↑ ↑ ↑ ↑ ↑ ↑  │
-           │              │
-           │  Data Area   │ Variables and data grow upward
-           │              │
-   0x0000  └──────────────┘ Program starts here (PC=0)
-
-**Key Points:**
-
-* Memory is byte-addressable (each address holds one 8-bit value)
-* Full 2KB address space available by default
-* No fixed boundaries between stack and data areas
-* Stack and data can grow toward each other (watch for collisions!)
-* All memory initializes to 0 on CPU creation
-* RAM size is configurable via ``Memory(ram_size=...)``
-
-**Memory Access:**
-
-The CPU uses register-indirect addressing for memory operations:
+   0xFFFF  ┌──────────────────────────────────┐ ← SP (Initial Position)
+           │            Stack Area            │ Stack grows downward (PUSH, CALL)
+           │            ↓  ↓  ↓  ↓            │
+   0x0600  ├──────────────────────────────────┤
+           │      Upper RAM & Model Weights   │ Dynamic data, arrays, diffusion weights
+   0x0200  ├──────────────────────────────────┤
+           │  Display VRAM Matrix (32x32)     │ Memory-mapped display (1024 bytes)
+           │  ASCII Text & Heatmap Output     │ Fits 28x28 MNIST digits (margin: 2)
+   0x0060  ├──────────────────────────────────┤
+           │            User SRAM             │ General data & arrays start at 0x0060
+   0x0020  ├──────────────────────────────────┤
+           │          I/O Registers           │ 64 I/O ports (0x00..0x3F via IN/OUT)
+   0x0000  ├──────────────────────────────────┤
+           │    General Working Registers     │ 32 registers (R0..R31) / Reserved
+           └──────────────────────────────────┘
+
+AVR Addressing Modes
+~~~~~~~~~~~~~~~~~~~~
+
+Tiny8 strictly adheres to the standard AVR addressing modes specified in DS40002198A:
+
+1. **Direct Single Register**: Operates on a single working register :math:`Rd` (e.g. ``INC Rd``, ``DEC Rd``, ``NEG Rd``, ``COM Rd``, ``CLR Rd``, ``SER Rd``, ``SWAP Rd``, ``LSL Rd``, ``LSR Rd``).
+2. **Direct Two-Register**: Operates on two working registers :math:`Rd` and :math:`Rr` (e.g. ``ADD Rd, Rr``, ``ADC Rd, Rr``, ``SUB Rd, Rr``, ``SBC Rd, Rr``, ``AND Rd, Rr``, ``OR Rd, Rr``, ``EOR Rd, Rr``, ``CP Rd, Rr``, ``MOV Rd, Rr``).
+3. **Immediate Addressing**: An 8-bit constant :math:`K` operates on an upper register :math:`R16 \le Rd \le R31` (e.g. ``LDI Rd, K``, ``SUBI Rd, K``, ``SBCI Rd, K``, ``ANDI Rd, K``, ``ORI Rd, K``, ``CPI Rd, K``).
+4. **Word Immediate Addressing**: A 6-bit constant :math:`0 \le K \le 63` operates on register pairs :math:`R25:R24`, :math:`X`, :math:`Y`, or :math:`Z` (e.g. ``ADIW Rd, K``, ``SBIW Rd, K``).
+5. **Direct Data Addressing**: 16-bit absolute memory address :math:`k` loads or stores directly to Data Space (e.g. ``LDS Rd, k``, ``STS k, Rr``).
+6. **Data Indirect Addressing with Pointer Registers (X, Y, Z)**: Accesses Data Space through 16-bit register pointers :math:`X` (R27:R26), :math:`Y` (R29:R28), or :math:`Z` (R31:R30) (e.g. ``LD Rd, X``, ``ST X, Rr``).
+7. **I/O Direct Addressing**: Reads or writes to 6-bit I/O addresses :math:`0 \le P \le 63` (e.g. ``IN Rd, P``, ``OUT P, Rr``, ``SBI P, b``, ``CBI P, b``, ``SBIS P, b``, ``SBIC P, b``).
+8. **Relative Program Addressing**: Jumps or branches relative to the current Program Counter within range :math:`PC + k + 1` (e.g. ``RJMP k``, ``RCALL k``, ``BREQ k``, ``BRNE k``, ``BRCS k``, ``BRCC k``, ``BRLO k``, ``BRSH k``, ``BRGE k``, ``BRLT k``, ``BRMI k``, ``BRPL k``).
+9. **Direct Program Addressing**: Unconditional jump or long subroutine call directly to 16-bit program address :math:`k` (e.g. ``JMP k``, ``CALL k``).
+10. **Indirect Program Addressing**: Return from subroutine or interrupt through return address popped from the stack (e.g. ``RET``, ``RETI``).
+
+Memory Access Examples
+~~~~~~~~~~~~~~~~~~~~~~
 
 .. code-block:: asm
 
-   ; Load from memory
-   ldi r26, 0x00        ; Set address low byte
-   ldi r27, 0x02        ; Set address high byte (address = 0x0200)
-   ld r16, r26          ; Load byte from address in R26 into R16
+   ; 1. Direct Data Addressing
+   lds r16, 0x0200      ; Load byte directly from address 0x0200
+   sts 0x0200, r16      ; Store byte directly to address 0x0200
    
-   ; Store to memory  
-   ldi r26, 0x50        ; Address = 0x50
-   ldi r16, 42          ; Value to store
-   st r26, r16          ; Store R16 to memory[R26]
-
-Memory Operations
-~~~~~~~~~~~~~~~~~
-
-**Stack Operations**
-
-The stack is used for temporary storage and subroutine calls:
-
-.. code-block:: asm
+   ; 2. Data Indirect Addressing via X Pointer Register (R27:R26)
+   ldi r26, 0x50        ; XL = 0x50
+   ldi r27, 0x02        ; XH = 0x02 (X = 0x0250)
+   ld r16, r26          ; Load from memory[X] into R16
+   st r26, r17          ; Store R17 to memory[X]
 
+   ; 3. Stack Operations
    push r16             ; Push R16 onto stack (SP decrements)
    pop r17              ; Pop from stack into R17 (SP increments)
-   
-   call my_function     ; Pushes return address, then jumps
-   ret                  ; Pops return address, then returns
 
-**I/O Operations**
-
-Access I/O ports and special registers:
-
-.. code-block:: asm
-
-   in r16, 0x3F         ; Read from I/O port 0x3F into R16
-   out 0x3F, r16        ; Write R16 to I/O port 0x3F
-
-Memory Initialization
-~~~~~~~~~~~~~~~~~~~~~
+   ; 4. I/O Port Operations
+   in r16, 0x10         ; Read from keyboard buffer port (0x0010)
+   out 0x3F, r16        ; Write to I/O port 0x3F
 
 * All memory is initialized to 0 on CPU creation
 * The assembler loads program instructions starting at address 0
@@ -170,176 +161,201 @@ Memory Initialization
 Status Flags
 ------------
 
-The Status Register (SREG) contains 8 condition flags that reflect the result of operations and control program flow.
+The Status Register (SREG) contains 8 condition flags that reflect the result of operations and control program flow. In accordance with the **Microchip AVR® Instruction Set Manual (DS40002198A)**, each flag is defined and updated according to exact Boolean algebraic formulas.
 
-Flag Descriptions
-~~~~~~~~~~~~~~~~~
+Flag Descriptions & Boolean Formulas
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 .. list-table::
    :header-rows: 1
-   :widths: 10 15 75
+   :widths: 6 12 22 60
 
    * - Bit
+     - Flag
      - Name
-     - Description
+     - DS40002198A Definition & Formula
    * - 7
-     - **I** (Interrupt)
-     - Global interrupt enable flag. When set, interrupts are enabled.
+     - **I**
+     - Global Interrupt
+     - Set by ``SEI``, cleared by ``CLI`` or hardware interrupt entry.
    * - 6
-     - **T** (Transfer)
-     - Bit copy storage. Used by BLD and BST instructions for bit manipulation.
+     - **T**
+     - Bit Copy Storage
+     - Transferred between SREG and register bit locations by ``BST`` / ``BLD``.
    * - 5
-     - **H** (Half Carry)
-     - Half-carry flag. Set when there's a carry from bit 3 to bit 4 in arithmetic operations. Used for BCD arithmetic.
+     - **H**
+     - Half Carry
+     - Indicates carry/borrow across nibble boundary (bit 3 to bit 4). ADD: :math:`Rd3 \cdot Rr3 + Rr3 \cdot \overline{R3} + \overline{R3} \cdot Rd3`. SUB: :math:`\overline{Rd3} \cdot Rr3 + Rr3 \cdot R3 + R3 \cdot \overline{Rd3}`.
    * - 4
-     - **S** (Sign)
-     - Sign flag, computed as N ⊕ V (N XOR V). Indicates true sign of result considering two's complement overflow.
+     - **S**
+     - Sign Bit
+     - True algebraic sign test considering two's complement overflow: :math:`S = N \oplus V`.
    * - 3
-     - **V** (Overflow)
-     - Two's complement overflow flag. Set when signed arithmetic produces a result outside the range -128 to +127.
+     - **V**
+     - Overflow
+     - Two's complement signed overflow flag. ADD: :math:`Rd7 \cdot Rr7 \cdot \overline{R7} + \overline{Rd7} \cdot \overline{Rr7} \cdot R7`. SUB: :math:`Rd7 \cdot \overline{Rr7} \cdot \overline{R7} + \overline{Rd7} \cdot Rr7 \cdot R7`.
    * - 2
-     - **N** (Negative)
-     - Negative flag. Set when the result of an operation has bit 7 set (i.e., the result is negative in two's complement).
+     - **N**
+     - Negative
+     - Set if the most significant bit (MSB, bit 7) of the result is 1: :math:`N = R7`.
    * - 1
-     - **Z** (Zero)
-     - Zero flag. Set when the result of an operation is zero.
+     - **Z**
+     - Zero
+     - Set if the result equals zero: :math:`Z = \overline{R7} \cdot \overline{R6} \cdot \overline{R5} \cdot \overline{R4} \cdot \overline{R3} \cdot \overline{R2} \cdot \overline{R1} \cdot \overline{R0}`.
    * - 0
-     - **C** (Carry)
-     - Carry flag. Set when there's a carry out of bit 7 (unsigned overflow) or a borrow in subtraction.
+     - **C**
+     - Carry / Borrow
+     - Unsigned carry out of bit 7 or borrow. ADD: :math:`Rd7 \cdot Rr7 + Rr7 \cdot \overline{R7} + \overline{R7} \cdot Rd7`. SUB: :math:`\overline{Rd7} \cdot Rr7 + Rr7 \cdot R7 + R7 \cdot \overline{Rd7}`.
 
-Flag Updates
-~~~~~~~~~~~~
+Flag Updates by Instruction Category
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-Different instructions update flags in different ways:
+According to AVR Instruction Set Manual DS40002198A:
 
-**Arithmetic Instructions** (ADD, SUB, ADC, SBC)
-  Update all flags: C, Z, N, V, S, H
+**Arithmetic (ADD, ADC, SUB, SUBI, SBC, SBCI)**
+  Updates all condition flags: ``H``, ``S``, ``V``, ``N``, ``Z``, ``C``.
 
-**Logical Instructions** (AND, OR, EOR)
-  Update Z, N, S; Clear V; Leave C unchanged
+**Comparisons (CP, CPI)**
+  Identical flag updates to subtraction (``SUB`` / ``SUBI``), but the register value is discarded.
 
-**Comparison** (CP, CPI)
-  Update all flags like subtraction, but don't store result
+**Bitwise Logical (AND, ANDI, OR, ORI, EOR, TST)**
+  Updates ``S``, ``V=0`` (cleared), ``N``, ``Z``. Carry ``C`` and Half-Carry ``H`` are **unaffected** (``-``). ``TST Rd`` is an alias for ``AND Rd, Rd``.
 
-**Test** (TST)
-  Update Z, N, S, V; Clear V
+**Register Clearing & Setting (CLR, SER)**
+  * ``CLR Rd`` is an alias for ``EOR Rd, Rd``: sets ``Z=1``, ``S=0``, ``V=0``, ``N=0``; leaves ``C`` and ``H`` unaffected.
+  * ``SER Rd`` is an alias for ``LDI Rd, 0xFF``: **no flags affected**.
 
-**Increment/Decrement** (INC, DEC)
-  Update Z, N, V, S; Leave C unchanged
+**Single-Operand Arithmetic (INC, DEC, NEG, COM)**
+  * ``INC`` / ``DEC``: Update ``S``, ``V``, ``N``, ``Z``. Carry ``C`` is **unaffected** (allows loop counters without clobbering carry).
+  * ``NEG``: Two's complement negation (:math:`R = 0 - Rd`). Updates ``H``, ``S``, ``V``, ``N``, ``Z``, ``C``. (:math:`C = (R \neq 0)`, :math:`V = (Rd = 0x80)`).
+  * ``COM``: One's complement inversion (:math:`R = 0xFF - Rd`). Updates ``S``, ``V=0``, ``N``, ``Z``, and forces ``C=1``.
 
-Using Flags for Branches
-~~~~~~~~~~~~~~~~~~~~~~~~~
+**Shifts & Rotates (LSL, LSR, ROL, ROR, SWAP)**
+  * ``LSL Rd``: Alias for ``ADD Rd, Rd``.
+  * ``ROL Rd``: Alias for ``ADC Rd, Rd``.
+  * ``LSR Rd``: Logical shift right. Sets :math:`C = Rd0`, :math:`N = 0`, :math:`Z = (R = 0)`, :math:`V = N \oplus C = C`, :math:`S = N \oplus V = C`.
+  * ``ROR Rd``: Rotate right through carry. Sets :math:`C = Rd0`, :math:`N = R7`, :math:`Z = (R = 0)`, :math:`V = N \oplus C`, :math:`S = N \oplus V`.
+  * ``SWAP Rd``: Swaps nibbles. **No flags affected**.
 
-Conditional branch instructions test specific flag conditions:
+**Word Operations (ADIW, SBIW)**
+  16-bit word addition / subtraction on pointer register pairs (R25:R24, R27:R26, R29:R28, R31:R30). Updates ``S``, ``V``, ``N``, ``Z``, ``C``.
 
-.. code-block:: asm
+**Data Transfer & Branches (LDI, MOV, LD, ST, LDS, STS, PUSH, POP, IN, OUT, JMP, RJMP, CALL, RCALL, RET, BRxx)**
+  Do not affect status flags, except ``RETI`` which sets the Global Interrupt Flag ``I = 1``.
 
-   ; Branch if equal (Z flag set)
-   breq label
-   
-   ; Branch if not equal (Z flag clear)
-   brne label
-   
-   ; Branch if carry set (C flag set)
-   brcs label
-   
-   ; Branch if less than (signed: S flag set)
-   brlt label
-   
-   ; Branch if lower (unsigned: C flag set)
-   brlo label
+Using Flags for Branches
+~~~~~~~~~~~~~~~~~~~~~~~~~
 
-Instruction Execution
----------------------
+Conditional branch instructions inspect specific SREG condition flags (all branches take target label or relative offset without altering flags):
 
-Fetch-Decode-Execute Cycle
-~~~~~~~~~~~~~~~~~~~~~~~~~~~
+.. list-table::
+   :header-rows: 1
+   :widths: 15 20 65
+
+   * - Mnemonic
+     - Condition
+     - Description (per DS40002198A)
+   * - ``BREQ label``
+     - Z = 1
+     - Branch if Equal
+   * - ``BRNE label``
+     - Z = 0
+     - Branch if Not Equal
+   * - ``BRCS label``
+     - C = 1
+     - Branch if Carry Set
+   * - ``BRCC label``
+     - C = 0
+     - Branch if Carry Clear
+   * - ``BRLO label``
+     - C = 1
+     - Branch if Lower (Unsigned, alias for ``BRCS``)
+   * - ``BRSH label``
+     - C = 0
+     - Branch if Same or Higher (Unsigned, alias for ``BRCC``)
+   * - ``BRGE label``
+     - S = 0 (N ⊕ V = 0)
+     - Branch if Greater or Equal (Signed)
+   * - ``BRLT label``
+     - S = 1 (N ⊕ V = 1)
+     - Branch if Less Than (Signed)
+   * - ``BRMI label``
+     - N = 1
+     - Branch if Minus
+   * - ``BRPL label``
+     - N = 0
+     - Branch if Plus
+
+Instruction Execution & ALU
+----------------------------
+
+ALU Operation & Register Access
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+In strict compliance with the **AVR® Instruction Set Manual (DS40002198A, Section 4)**, the high-performance AVR Arithmetic Logic Unit (ALU) operates in direct connection with all 32 general-purpose registers:
+
+* **Single-Cycle Operation**: Arithmetic and logical register-to-register operations execute within a single instruction transition. In this cycle:
+  1. Two operand registers are read from the Register File.
+  2. The operation (Arithmetic, Logical, or Bit manipulation) is evaluated.
+  3. The result is written back to the destination register :math:`Rd`.
+  4. The Status Register (SREG) condition flags are updated according to exact Boolean algebraic formulas.
+* **ALU Functional Blocks**:
+  * **Arithmetic**: Addition (``ADD``, ``ADC``, ``ADIW``), Subtraction (``SUB``, ``SUBI``, ``SBC``, ``SBCI``, ``SBIW``), Comparison (``CP``, ``CPI``), Negation (``NEG``), Increment (``INC``), Decrement (``DEC``), and Multiplication (``MUL``, ``MULS``, ``MULSU``).
+  * **Logical**: Bitwise AND (``AND``, ``ANDI``, ``TST``), OR (``OR``, ``ORI``), Exclusive-OR (``EOR``, ``CLR``), and One's Complement (``COM``).
+  * **Bit & Shift Functions**: Bit set/clear (``SBI``, ``CBI``), Shifts (``LSL``, ``LSR``, ``ASR``), Rotates through carry (``ROL``, ``ROR``), and Nibble swap (``SWAP``).
 
-Tiny8 uses a simplified instruction execution model:
+Fetch-Decode-Execute Cycle
+~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-1. **Fetch**: Read instruction at address PC
-2. **Decode**: Parse instruction mnemonic and operands
-3. **Execute**: Perform the operation
-4. **Update**: Increment PC, update flags, record traces
+Tiny8 executes programs through the classical CPU cycle:
 
 .. code-block:: text
 
-   ┌──────────┐
-   │  FETCH   │ ← Read instruction at PC
-   └────┬─────┘
-        │
-   ┌────▼─────┐
-   │  DECODE  │ ← Parse mnemonic and operands
-   └────┬─────┘
-        │
-   ┌────▼─────┐
-   │ EXECUTE  │ ← Perform operation
-   └────┬─────┘
-        │
-   ┌────▼─────┐
-   │  UPDATE  │ ← Update PC, flags, traces
-   └──────────┘
-
-Instruction Format
-~~~~~~~~~~~~~~~~~~
+   ┌─────────────────────────────────────────────────────────────┐
+   │                          CPU Cycle                          │
+   ├───────────┬───────────┬───────────────────┬─────────────────┤
+   │   FETCH   │  DECODE   │      EXECUTE      │   WRITE & STEP  │
+   │ Read from │ Opcode &  │ ALU / Branch /    │ Update Reg/RAM, │
+   │ PC address│ Operands  │ Memory Operation  │ SREG & Advance  │
+   └───────────┴───────────┴───────────────────┴─────────────────┘
 
-Instructions are stored as tuples in memory:
+Instruction Format & Encoding
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-.. code-block:: python
-
-   (mnemonic, (operand1, operand2, ...))
-   
-   # Examples:
-   ("ldi", (("reg", 16), 42))      # ldi r16, 42
-   ("add", (("reg", 16), ("reg", 17)))  # add r16, r17
-   ("jmp", ("loop",))              # jmp loop
-
-Operand Types
-~~~~~~~~~~~~~
-
-Operands can be:
+In physical AVR microcontrollers:
+* Most instructions are **16-bit (1-word)** opcodes.
+* Direct memory instructions (``LDS``, ``STS``) and long jumps/calls (``JMP``, ``CALL``) are **32-bit (2-word)** opcodes.
 
-* **Register**: ``("reg", N)`` where N is 0-31
-* **Immediate**: Integer value
-* **Label**: String referring to a program location
-* **Address**: Memory address (integer)
+In Tiny8, the assembler validates operands according to AVR DS40002198A constraints (e.g., verifying that ``LDI``, ``SUBI``, ``CPI`` only target upper registers R16–R31, and that ``ADIW`` / ``SBIW`` target valid pointer register pairs), then stores them as pre-decoded execution tuples:
 
-Step Tracing
-~~~~~~~~~~~~
-
-The CPU automatically records traces during execution:
-
-**Register Trace**
-  Records all register changes as ``(step, register, new_value)``
-
-**Memory Trace**
-  Records all memory writes as ``(step, address, new_value)``
+.. code-block:: python
 
-**Step Trace**
-  Records full CPU state snapshots for visualization
+   (mnemonic, (operand1, operand2, ...))
 
-These traces enable the interactive debugger and animation features.
+   # Examples:
+   ("ldi", (16, 42))        # LDI R16, 42
+   ("add", (16, 17))        # ADD R16, R17
+   ("lds", (16, 0x0200))    # LDS R16, 0x0200
+   ("jmp", ("loop",))       # JMP loop
 
-Performance Characteristics
----------------------------
+Step Tracing & State Inspection
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-Execution Model
-~~~~~~~~~~~~~~~
+During each execution step, Tiny8 records changes to facilitate visual debugging:
 
-* **Single-cycle execution**: Each instruction completes in one "step"
-* **No pipeline**: Instructions execute sequentially
-* **No timing accuracy**: Simplified model for education
+* **Register Trace**: Tracks register writes as ``(step, register_index, new_value)``.
+* **Memory Trace**: Tracks SRAM writes as ``(step, address, new_value)``.
+* **Step Telemetry**: Records PC, SREG flags, cycle counts, and call stack backtraces.
 
-.. note::
-   Real AVR microcontrollers have variable instruction timing (1-4 cycles) and pipelined execution. Tiny8 abstracts these details for simplicity.
+Hardware Realism & AVR Compliance
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-Limitations
-~~~~~~~~~~~
+Tiny8 is strictly grounded in the **Microchip AVR® Instruction Set Manual (DS40002198A)**:
 
-* No I/O peripherals (timers, UART, etc.)
-* No interrupt handling (I flag exists but not functional)
-* Simplified flag semantics
-* No program memory vs. data memory separation (Von Neumann architecture)
+* **Instruction Set Fidelity**: All 61 supported instructions strictly follow official Microchip AVR definitions, operands, and SREG Boolean formulas without non-standard instruction extensions.
+* **Hardware MUL Compliance**: In accordance with AVR DS40002198A, ``MUL Rd, Rr`` writes the 16-bit unsigned product strictly into the dedicated register pair ``R1:R0`` (R0 = low byte, R1 = high byte).
+* **Software Division**: Conforming to physical AVR silicon, integer division is performed via standard software routines (e.g., subtraction loops or shift-and-subtract) rather than non-standard hardware instructions.
+* **Execution & Memory Model**: Instructions execute in discrete single-step transitions across a unified flat address space with memory-mapped I/O (ports 0x00..0x3F including CRT matrix and keyboard buffer) for full visibility and educational inspectability.
 
 Design Philosophy
 -----------------
@@ -352,7 +368,7 @@ Tiny8's architecture is designed with these principles:
 4. **Extensibility**: Easy to add new instructions
 5. **Practicality**: Can run real algorithms and demonstrate CS concepts
 
-The architecture strikes a balance between realism (AVR-inspired) and pedagogy (simplified execution model), making it suitable for:
+The architecture strikes a balance between realism (standard AVR architecture) and pedagogy (simplified execution model), making it suitable for:
 
 * Computer architecture courses
 * Assembly language learning
diff --git a/docs/assembly_language.rst b/docs/assembly_language.rst
index 105bc55..83ceadf 100644
--- a/docs/assembly_language.rst
+++ b/docs/assembly_language.rst
@@ -486,3 +486,338 @@ Common Patterns
 ---------------
 
 See the :doc:`getting_started` guide for common assembly patterns like loops, conditionals, and memory operations.
+
+Instruction Set Reference
+-------------------------
+
+The Tiny8 instruction set strictly follows the **Microchip AVR® Instruction Set Manual (DS40002198A)**. All mnemonics and register identifiers are case-insensitive. Immediates can be specified in decimal, hexadecimal (``$FF`` or ``0xFF``), or binary (``0b11111111``).
+
+Arithmetic and Logic Instructions
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. list-table::
+   :header-rows: 1
+   :widths: 18 26 36 20
+
+   * - Mnemonic & Operands
+     - Description (DS40002198A)
+     - Operation
+     - Flags
+   * - ``ADD Rd, Rr``
+     - Add without Carry
+     - Rd ← Rd + Rr
+     - H, S, V, N, Z, C
+   * - ``ADC Rd, Rr``
+     - Add with Carry
+     - Rd ← Rd + Rr + C
+     - H, S, V, N, Z, C
+   * - ``ADIW Rd, K``
+     - Add Immediate to Word
+     - Rd+1:Rd ← Rd+1:Rd + K
+     - S, V, N, Z, C
+   * - ``SUB Rd, Rr``
+     - Subtract without Carry
+     - Rd ← Rd - Rr
+     - H, S, V, N, Z, C
+   * - ``SUBI Rd, K``
+     - Subtract Immediate
+     - Rd ← Rd - K
+     - H, S, V, N, Z, C
+   * - ``SBC Rd, Rr``
+     - Subtract with Carry
+     - Rd ← Rd - Rr - C
+     - H, S, V, N, Z, C
+   * - ``SBCI Rd, K``
+     - Subtract Immediate with Carry
+     - Rd ← Rd - K - C
+     - H, S, V, N, Z, C
+   * - ``SBIW Rd, K``
+     - Subtract Immediate from Word
+     - Rd+1:Rd ← Rd+1:Rd - K
+     - S, V, N, Z, C
+   * - ``AND Rd, Rr``
+     - Logical AND
+     - Rd ← Rd · Rr
+     - S, V=0, N, Z
+   * - ``ANDI Rd, K``
+     - Logical AND with Immediate
+     - Rd ← Rd · K
+     - S, V=0, N, Z
+   * - ``OR Rd, Rr``
+     - Logical OR
+     - Rd ← Rd ∨ Rr
+     - S, V=0, N, Z
+   * - ``ORI Rd, K``
+     - Logical OR with Immediate
+     - Rd ← Rd ∨ K
+     - S, V=0, N, Z
+   * - ``EOR Rd, Rr``
+     - Exclusive OR
+     - Rd ← Rd ⊕ Rr
+     - S, V=0, N, Z
+   * - ``COM Rd``
+     - One's Complement
+     - Rd ← 0xFF - Rd
+     - S, V=0, N, Z, C=1
+   * - ``NEG Rd``
+     - Two's Complement Negation
+     - Rd ← 0x00 - Rd
+     - H, S, V, N, Z, C
+   * - ``INC Rd``
+     - Increment
+     - Rd ← Rd + 1
+     - S, V, N, Z
+   * - ``DEC Rd``
+     - Decrement
+     - Rd ← Rd - 1
+     - S, V, N, Z
+   * - ``TST Rd``
+     - Test for Zero or Minus
+     - Rd ← Rd · Rd (alias for AND)
+     - S, V=0, N, Z
+   * - ``CLR Rd``
+     - Clear Register
+     - Rd ← Rd ⊕ Rd (alias for EOR)
+     - S=0, V=0, N=0, Z=1
+   * - ``SER Rd``
+     - Set Register
+     - Rd ← 0xFF (alias for LDI)
+     - None
+   * - ``MUL Rd, Rr``
+     - Multiply Unsigned
+     - R1:R0 ← Rd × Rr
+     - Z, C
+   * - ``MULS Rd, Rr``
+     - Multiply Signed
+     - R1:R0 ← Rd × Rr (signed)
+     - Z, C
+   * - ``MULSU Rd, Rr``
+     - Multiply Signed with Unsigned
+     - R1:R0 ← Rd × Rr (Rd signed, Rr unsigned)
+     - Z, C
+
+Branch Instructions
+~~~~~~~~~~~~~~~~~~~
+
+.. list-table::
+   :header-rows: 1
+   :widths: 18 26 36 20
+
+   * - Mnemonic & Operands
+     - Description (DS40002198A)
+     - Operation
+     - Flags
+   * - ``JMP target``
+     - Jump
+     - PC ← target
+     - None
+   * - ``RJMP offset``
+     - Relative Jump
+     - PC ← PC + offset + 1
+     - None
+   * - ``CALL target``
+     - Long Call to Subroutine
+     - STACK ← PC + 1, PC ← target
+     - None
+   * - ``RCALL offset``
+     - Relative Call to Subroutine
+     - STACK ← PC + 1, PC ← PC + offset + 1
+     - None
+   * - ``RET``
+     - Return from Subroutine
+     - PC ← STACK
+     - None
+   * - ``RETI``
+     - Return from Interrupt
+     - PC ← STACK, I ← 1
+     - I
+   * - ``CPSE Rd, Rr``
+     - Compare Skip if Equal
+     - If Rd = Rr then skip next instruction
+     - None
+   * - ``CP Rd, Rr``
+     - Compare
+     - Rd - Rr
+     - H, S, V, N, Z, C
+   * - ``CPI Rd, K``
+     - Compare with Immediate
+     - Rd - K
+     - H, S, V, N, Z, C
+   * - ``BREQ label``
+     - Branch if Equal
+     - If Z = 1 then PC ← label
+     - None
+   * - ``BRNE label``
+     - Branch if Not Equal
+     - If Z = 0 then PC ← label
+     - None
+   * - ``BRCS label``
+     - Branch if Carry Set
+     - If C = 1 then PC ← label
+     - None
+   * - ``BRCC label``
+     - Branch if Carry Clear
+     - If C = 0 then PC ← label
+     - None
+   * - ``BRLO label``
+     - Branch if Lower (Unsigned)
+     - If C = 1 then PC ← label (alias for BRCS)
+     - None
+   * - ``BRSH label``
+     - Branch if Same or Higher
+     - If C = 0 then PC ← label (alias for BRCC)
+     - None
+   * - ``BRGE label``
+     - Branch if Greater or Equal (Signed)
+     - If S = 0 (N ⊕ V = 0) then PC ← label
+     - None
+   * - ``BRLT label``
+     - Branch if Less Than (Signed)
+     - If S = 1 (N ⊕ V = 1) then PC ← label
+     - None
+   * - ``BRMI label``
+     - Branch if Minus
+     - If N = 1 then PC ← label
+     - None
+   * - ``BRPL label``
+     - Branch if Plus
+     - If N = 0 then PC ← label
+     - None
+
+Data Transfer Instructions
+~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. list-table::
+   :header-rows: 1
+   :widths: 18 26 36 20
+
+   * - Mnemonic & Operands
+     - Description (DS40002198A)
+     - Operation
+     - Flags
+   * - ``MOV Rd, Rr``
+     - Copy Register
+     - Rd ← Rr
+     - None
+   * - ``LDI Rd, K``
+     - Load Immediate
+     - Rd ← K (16 ≤ d ≤ 31)
+     - None
+   * - ``LD Rd, addr_reg``
+     - Load Indirect from Data Space
+     - Rd ← (addr_reg)
+     - None
+   * - ``ST addr_reg, Rr``
+     - Store Indirect to Data Space
+     - (addr_reg) ← Rr
+     - None
+   * - ``LDS Rd, addr``
+     - Load Direct from Data Space
+     - Rd ← (addr)
+     - None
+   * - ``STS addr, Rr``
+     - Store Direct to Data Space
+     - (addr) ← Rr
+     - None
+   * - ``IN Rd, port``
+     - Load an I/O Location to Register
+     - Rd ← P
+     - None
+   * - ``OUT port, Rr``
+     - Store Register to an I/O Location
+     - P ← Rr
+     - None
+   * - ``PUSH Rr``
+     - Push Register on Stack
+     - STACK ← Rr, SP ← SP - 1
+     - None
+   * - ``POP Rd``
+     - Pop Register from Stack
+     - SP ← SP + 1, Rd ← STACK
+     - None
+
+Bit and Bit-Test Instructions
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. list-table::
+   :header-rows: 1
+   :widths: 18 26 36 20
+
+   * - Mnemonic & Operands
+     - Description (DS40002198A)
+     - Operation
+     - Flags
+   * - ``SBI port, bit``
+     - Set Bit in I/O Register
+     - I/O(P, bit) ← 1
+     - None
+   * - ``CBI port, bit``
+     - Clear Bit in I/O Register
+     - I/O(P, bit) ← 0
+     - None
+   * - ``LSL Rd``
+     - Logical Shift Left
+     - Rd ← Rd ≪ 1 (alias for ADD Rd, Rd)
+     - H, S, V, N, Z, C
+   * - ``LSR Rd``
+     - Logical Shift Right
+     - 0 → Rd7 … Rd0 → C
+     - S, V, N, Z, C
+   * - ``ASR Rd``
+     - Arithmetic Shift Right
+     - Rd7 → Rd7 … Rd0 → C
+     - S, V, N, Z, C
+   * - ``ROL Rd``
+     - Rotate Left through Carry
+     - C ← Rd7 … Rd0 ← C (alias for ADC Rd, Rd)
+     - H, S, V, N, Z, C
+   * - ``ROR Rd``
+     - Rotate Right through Carry
+     - C → Rd7 … Rd0 → C
+     - S, V, N, Z, C
+   * - ``SWAP Rd``
+     - Swap Nibbles
+     - Rd(7..4) ↔ Rd(3..0)
+     - None
+   * - ``SBRS Rd, bit``
+     - Skip if Bit in Register is Set
+     - If Rd(bit) = 1 then skip next instruction
+     - None
+   * - ``SBRC Rd, bit``
+     - Skip if Bit in Register is Cleared
+     - If Rd(bit) = 0 then skip next instruction
+     - None
+   * - ``SBIS port, bit``
+     - Skip if Bit in I/O Register is Set
+     - If I/O(P, bit) = 1 then skip next instruction
+     - None
+   * - ``SBIC port, bit``
+     - Skip if Bit in I/O Register is Cleared
+     - If I/O(P, bit) = 0 then skip next instruction
+     - None
+
+MCU Control Instructions
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. list-table::
+   :header-rows: 1
+   :widths: 18 26 36 20
+
+   * - Mnemonic & Operands
+     - Description (DS40002198A)
+     - Operation
+     - Flags
+   * - ``NOP``
+     - No Operation
+     - No operation performed
+     - None
+   * - ``SEI``
+     - Set Global Interrupt Flag
+     - I ← 1
+     - I
+   * - ``CLI``
+     - Clear Global Interrupt Flag
+     - I ← 0
+     - I
+
+
diff --git a/docs/conf.py b/docs/conf.py
index a53e5fc..541f52f 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -35,6 +35,8 @@
 exclude_patterns = ["_build", "Thumbs.db", ".DS_Store"]
 
 language = "en"
+locale_dirs = ["locales/"]
+gettext_compact = False
 
 # -- Autodoc configuration ---------------------------------------------------
 autodoc_default_options = {
@@ -74,7 +76,7 @@
 # https://www.sphinx-doc.org/en/master/usage/configuration.html#options-for-html-output
 
 html_theme = "shibuya"
-html_static_path = []  # No static files yet
+html_static_path = ["_static"]
 
 # Theme options
 html_theme_options = {
@@ -112,3 +114,24 @@
         "Miscellaneous",
     ),
 ]
+
+
+def setup(app):
+    """Sphinx application setup hook."""
+
+    def add_language_switcher_context(app, pagename, templatename, context, doctree):
+        depth = pagename.count("/")
+        prefix = "../" * depth
+        outdir_name = os.path.basename(os.path.abspath(app.outdir))
+        current_lang = app.config.language or "en"
+        context["current_language"] = current_lang
+
+        if outdir_name in ("en", "ja"):
+            up_to_langs = prefix + "../"
+            context["en_page_url"] = f"{up_to_langs}en/{pagename}.html"
+            context["ja_page_url"] = f"{up_to_langs}ja/{pagename}.html"
+        else:
+            context["en_page_url"] = f"{prefix}en/{pagename}.html"
+            context["ja_page_url"] = f"{prefix}ja/{pagename}.html"
+
+    app.connect("html-page-context", add_language_switcher_context)
diff --git a/docs/examples/bubblesort.rst b/docs/examples/bubblesort.rst
index 4224747..b838468 100644
--- a/docs/examples/bubblesort.rst
+++ b/docs/examples/bubblesort.rst
@@ -47,7 +47,8 @@ This generates a sequence of pseudo-random 8-bit values.
    ldi r25, 75       ; PRNG multiplier
 
    init_loop:
-       mul r18, r25  ; multiply seed by 75
+       mul r18, r25  ; multiply seed by 75 (product in R1:R0)
+       mov r18, r0   ; transfer low byte of product
        inc r18       ; add 1
        st r16, r18   ; store at RAM[base + index]
        ; ...
@@ -107,6 +108,7 @@ Inner Loop
        ; compare and swap if A > B (for ascending order)
        cp r21, r24
        brcs no_swap    ; skip if A < B
+       breq no_swap    ; skip if A == B
        st r20, r24     ; swap: RAM[addr_A] = B
        st r22, r21     ; swap: RAM[addr_B] = A
        
@@ -119,7 +121,6 @@ For each j:
 1. Load adjacent elements (j and j+1)
 2. Compare them
 3. Swap if first > second (for ascending order)
-3. Swap if first > second
 4. Advance to next pair
 
 Register Usage
diff --git a/docs/examples/gcd.rst b/docs/examples/gcd.rst
index 718fc67..621a605 100644
--- a/docs/examples/gcd.rst
+++ b/docs/examples/gcd.rst
@@ -7,4 +7,4 @@ Computes the GCD of two numbers using Euclidean algorithm.
    :language: asm
    :linenos:
 
-Demonstrates division, modulo operation, and iterative algorithm.
+Demonstrates subtraction-based Euclidean algorithm and conditional comparison.
diff --git a/docs/examples/index.rst b/docs/examples/index.rst
index dfd2fc3..98fa900 100644
--- a/docs/examples/index.rst
+++ b/docs/examples/index.rst
@@ -28,12 +28,6 @@ You can run any example with the interactive debugger:
 
    tiny8 examples/fibonacci.asm
 
-Or generate an animation:
-
-.. code-block:: bash
-
-   tiny8 examples/bubblesort.asm -m ani -o bubblesort.gif
-
 Or use the Python API:
 
 .. code-block:: python
@@ -83,6 +77,13 @@ Advanced Examples
    is_prime
    reverse
 
+C Language Programs & Interactive Demos
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Tiny8 includes an embedded C subset compiler capable of compiling and running C programs directly on the simulated CPU:
+
+* **factorial.c**: Recursive factorial calculation demonstration.
+
 Quick Reference
 ---------------
 
@@ -92,52 +93,58 @@ Quick Reference
 
    * - Program
      - Concept
-     - Key Instructions
+     - Key Instructions / Language
    * - Hello World
-     - Basic structure
-     - LDI, JMP
+     - Basic memory writing
+     - LDI, ST, INC, JMP
    * - Fibonacci
-     - Loops, arithmetic
+     - Iterative sequence
      - ADD, MOV, DEC, BRNE
-   * - Factorial
-     - Multiplication
+   * - Factorial (ASM)
+     - Iterative multiplication
      - MUL, DEC, CPI, BRGE
+   * - Factorial (C)
+     - Recursive function calls
+     - C Compiler (CALL, RET, PUSH, POP)
    * - Sum 1 to N
-     - Accumulation
-     - ADD, INC, CP, BRLO
+     - Loop accumulation
+     - ADD, INC, CP, BRLT, BREQ
    * - Array Sum
-     - Memory access
-     - LDS, ADD, INC
+     - Pointer iteration
+     - LD, ST, ADD, INC, BRNE
    * - Find Max
-     - Comparison
-     - CP, BRLO, MOV
+     - Array scanning & comparison
+     - LD, ST, CP, BRGE, MOV
    * - Linear Search
-     - Sequential search
-     - LDS, CP, BREQ
+     - Target search & sentinel
+     - LD, ST, CP, BREQ, INC
    * - Memory Copy
-     - Data transfer
-     - LDS, STS, INC
+     - Block memory transfer
+     - LD, ST, INC, DEC, BRNE
    * - Bubble Sort
-     - Sorting algorithm
-     - LD, ST, CP, BRCC
+     - PRNG & in-place sort
+     - MUL, LD, ST, CP, BRCS
    * - GCD
      - Euclidean algorithm
-     - DIV, MUL, SUB, MOV
+     - DIV, MOV, CPI, BREQ
    * - Power
-     - Repeated multiplication
-     - MUL, DEC, BRNE
+     - Exponentiation
+     - MUL, INC, CP, BRLT
    * - Multiply by Shift
-     - Bit manipulation
-     - LSL, LSR, ADD
+     - Binary shift multiplication
+     - LSL, LSR, ANDI, ADD
    * - Count Bits
-     - Bit operations
-     - LSR, ANDI
+     - Bit testing & division
+     - AND, DIV, CPI, BRNE
    * - Is Prime
-     - Number theory
-     - DIV, MUL, CP
+     - Trial division
+     - DIV, MUL, CP, BRGE, BRLT
    * - Reverse Array
-     - Array manipulation
-     - LDS, STS, SWAP
+     - Two-pointer array reverse
+     - LD, ST, CP, BRGE, INC, DEC
+   * - MNIST Diffusion (ASM)
+     - Iterative reverse-diffusion synthesis
+     - ASM (diffusion_mnist8.asm)
 
 Learning Path
 -------------
diff --git a/docs/getting_started.rst b/docs/getting_started.rst
index d124b1b..c763ded 100644
--- a/docs/getting_started.rst
+++ b/docs/getting_started.rst
@@ -94,44 +94,38 @@ Debugger Controls
 
 Use these keyboard shortcuts to control execution:
 
-**Navigation:**
+**Execution:**
 
-* ``l`` or ``→`` - Step forward one instruction
-* ``h`` or ``←`` - Step backward one instruction  
-* ``w`` - Jump forward 10 steps
-* ``b`` - Jump backward 10 steps
-* ``0`` - Go to first step
-* ``$`` - Go to last step
+* ``Space`` - Play / pause automatic continuous execution
+* ``Shift+Space`` - Reverse playback execution
+* ``n`` - Step forward 1 instruction (+1 step)
+* ``p`` - Step backward 1 instruction (-1 step, time-travel)
+* ``c`` - Continue forward to next breakpoint
+* ``C`` (``Shift+c``) - Reverse continue backward to previous breakpoint
+* ``b`` - Toggle breakpoint at current PC
+* ``+`` / ``-`` - Increase / decrease playback speed
+* ``r`` - Reset execution back to Step 0
 
-**Playback:**
+**Display & Navigation:**
 
-* ``Space`` - Toggle play/pause
-* ``[`` - Slower playback
-* ``]`` - Faster playback
+* ``j`` / ``k`` - Scroll memory view down / up by 32 bytes (1 row)
+* ``J`` / ``K`` - Fast scroll memory view down / up by 128 bytes (4 rows)
+* ``g`` - Toggle Grayscale / Viridis color palette
+* ``x`` - Toggle Hexadecimal (02X) / Graphic Pixel blocks
+* ``m`` - Cycle view modes
+* ``i`` - Inspect details of currently executing instruction
+* ``h`` or ``?`` - Open full help and keyboard guide modal
+* ``e`` - Open built-in Vim modal editor
 
-**Display:**
+**Command Bar Prompt:**
 
-* ``r`` - Toggle showing all registers
-* ``M`` - Toggle showing all memory
-* ``=`` - Show detailed step information
-* ``j`` - Scroll memory view down
-* ``k`` - Scroll memory view up
-
-**Marks:**
-
-* ``m`` + letter - Set a mark at current position
-* ``'`` + letter - Jump to a saved mark
-
-**Search/Commands:**
-
-* ``/`` - Show help screen
-* ``:`` - Enter command mode (for advanced navigation and search)
+* ``:`` - Enter command prompt (e.g. ``:goto <step>``, ``:b <pc>``, ``:q``)
 
 **Exit:**
 
-* ``q`` or ``Esc`` - Quit
+* ``q`` - Quit debugger
 
-Try stepping through your program with ``l`` and watch how the registers change!
+Try stepping through your program with ``n`` and watch how the registers change!
 
 Running from Python
 -------------------
diff --git a/docs/index.rst b/docs/index.rst
index 3bc76f1..06a54a8 100644
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -3,53 +3,41 @@
 Tiny8 Documentation
 ===================
 
-**An educational 8-bit CPU simulator with interactive visualization**
+**From bare-metal computer architecture to Generative AI — an educational 8-bit AVR RISC CPU simulator with real-time interactive visualization**
 
-Tiny8 is a lightweight and educational toolkit for exploring the fundamentals of computer architecture through hands-on assembly programming and real-time visualization. Designed for learning and experimentation, it features an AVR-inspired 8-bit CPU with 32 registers, a rich instruction set, and powerful debugging tools — all with zero heavy dependencies.
+Tiny8 is a lightweight educational toolkit that bridges bare-metal computer architecture and modern Generative AI. Designed for hands-on learning and experimentation, it guides you through the full stack of computing — from 32 general-purpose registers, ALU operations, stack frames, and C compilation up to executing an iterative reverse-diffusion model synthesizing 28x28 MNIST digits directly on an AVR 8-bit RISC processor. With an interactive Vim-inspired terminal debugger, time-travel reverse execution, and a 32x32 TrueColor memory heatmap, Tiny8 lets you see, step through, and understand computation at every level.
 
-.. image:: https://github.com/user-attachments/assets/6d4f07ba-21b3-483f-a5d4-7603334c40f4
-   :alt: Animated bubble sort visualization
+.. figure:: https://github.com/user-attachments/assets/bd3e88da-9bcb-4a41-bb9e-57d9d4e39bc6
+   :alt: Real-time generative reverse-diffusion synthesis (MNIST 8) at x5,000 speed in Tiny8 TUI (Viridis Palette, HEX init -> PIXEL denoising)
    :align: center
-   :width: 600px
+   :width: 100%
 
-.. centered:: *Real-time visualization of a bubble sort algorithm executing on Tiny8*
+   *Real-time generative reverse-diffusion synthesis (MNIST digit 8) executing at x5,000 speed in Tiny8 TUI (HEX mode for weight/LFSR init &rarr; PIXEL mode for reverse denoising trajectory)*
 
 Features
 --------
 
-🎯 Interactive Terminal Debugger
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-.. image:: https://github.com/user-attachments/assets/5317ebcd-53d5-4966-84be-be94b7830899
-   :alt: CLI visualizer screenshot
-   :align: center
-   :width: 600px
+Interactive Terminal Debugger
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 * **Vim-style navigation**: Step through execution with intuitive keyboard controls
 * **Change highlighting**: See exactly what changed at each step (registers, flags, memory)
-* **Advanced search**: Find instructions, track register/memory changes, locate PC addresses
-* **Marks and bookmarks**: Set and jump to important execution points
-* **Vertical scrolling**: Handle programs with large memory footprints
-
-🎬 Graphical Animation
-~~~~~~~~~~~~~~~~~~~~~~~
+* **Time-travel debugging**: Step forward and backward with sparse checkpoint restoration
+* **32x32 TrueColor Heatmap**: VRAM memory matrix with Viridis/Grayscale visualization
+* **Built-in Vim Editor**: Launch full-screen modal editor anytime with ``e``
 
-* Generate high-quality GIF/MP4 videos of program execution
-* Visualize register evolution, memory access patterns, and flag changes
-* Perfect for presentations, documentation, and learning materials
-
-🏗️ Complete 8-bit Architecture
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Complete 8-bit Architecture
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 * **32 general-purpose registers** (R0-R31)
 * **8-bit ALU** with arithmetic, logical, and bit manipulation operations
 * **Status register (SREG)** with 8 condition flags
-* **2KB address space** for unified memory and I/O
+* **64KB address space** for unified memory and I/O
 * **Stack operations** with dedicated stack pointer
-* **AVR-inspired instruction set** with 60+ instructions
+* **AVR instruction set** with 67 instructions compliant with Microchip DS40002198A
 
-📚 Educational Focus
-~~~~~~~~~~~~~~~~~~~~
+Educational Focus
+~~~~~~~~~~~~~~~~~
 
 * Clean, readable Python implementation
 * Comprehensive examples (Fibonacci, bubble sort, factorial, and more)
@@ -99,12 +87,6 @@ Run it with the interactive debugger:
 
    tiny8 fibonacci.asm
 
-Or generate an animation:
-
-.. code-block:: bash
-
-   tiny8 fibonacci.asm -m ani -o fibonacci.gif
-
 Using the Python API
 ~~~~~~~~~~~~~~~~~~~~
 
diff --git a/docs/locales/ja/LC_MESSAGES/api/modules.po b/docs/locales/ja/LC_MESSAGES/api/modules.po
new file mode 100644
index 0000000..9f69380
--- /dev/null
+++ b/docs/locales/ja/LC_MESSAGES/api/modules.po
@@ -0,0 +1,25 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, 2026.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-25 00:49+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language: ja\n"
+"Language-Team: ja <LL@li.org>\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=utf-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Generated-By: Babel 2.17.0\n"
+
+#: ../../api/modules.rst:2
+msgid "tiny8"
+msgstr ""
+
diff --git a/docs/locales/ja/LC_MESSAGES/api/tiny8.po b/docs/locales/ja/LC_MESSAGES/api/tiny8.po
new file mode 100644
index 0000000..70ad57f
--- /dev/null
+++ b/docs/locales/ja/LC_MESSAGES/api/tiny8.po
@@ -0,0 +1,2564 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, 2026.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-25 01:27+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language: ja\n"
+"Language-Team: ja <LL@li.org>\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=utf-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Generated-By: Babel 2.17.0\n"
+
+#: ../../api/tiny8.rst:2
+msgid "tiny8 package"
+msgstr ""
+
+#: ../../api/tiny8.rst:5
+msgid "Submodules"
+msgstr ""
+
+#: ../../api/tiny8.rst:8
+msgid "tiny8.assembler module"
+msgstr ""
+
+#: of tiny8.assembler:1
+msgid "Assembler for tiny8 converting assembly text into program listings."
+msgstr ""
+
+#: of tiny8.assembler.AsmResult:1 tiny8.compiler.ASTNode:1
+#: tiny8.compiler.CodeGenerator:1 tiny8.compiler.Lexer:1
+#: tiny8.compiler.Parser:1 tiny8.compiler.Token:1 tiny8.cpu.CPU:1
+#: tiny8.memory.Memory:1 tiny8.tui.CheckpointManager:1
+#: tiny8.utils.ProgressBar:1
+msgid "Bases: :py:class:`object`"
+msgstr ""
+
+#: of tiny8.assembler.AsmResult:1
+msgid "Result of assembling assembly source code."
+msgstr ""
+
+#: ../../api/tiny8.rst of tiny8.compiler.CodeGenerator.gen_expr
+#: tiny8.compiler.optimize_assembly tiny8.cpu.CPU.restore_snapshot
+#: tiny8.memory.Memory.restore_ram tiny8.tui.CheckpointManager.detect_loop
+#: tiny8.tui.CheckpointManager.invalidate_after
+#: tiny8.tui.CheckpointManager.precompute tiny8.tui.CheckpointManager.record
+#: tiny8.tui.CheckpointManager.record_if_interval
+#: tiny8.tui.CheckpointManager.restore_exact_step
+#: tiny8.tui.MemoryWidget.get_heatmap_bg
+#: tiny8.tui.Tiny8App.action_exec_instruction
+#: tiny8.tui.Tiny8App.on_input_submitted tiny8.tui.Tiny8App.watch_mem_start
+#: tiny8.tui.eval_condition tiny8.tui.extract_call_frames
+#: tiny8.tui.get_widget_available_lines
+msgid "Parameters"
+msgstr ""
+
+#: of tiny8.assembler.AsmResult:5 tiny8.cpu.CPU:47 tiny8.cpu.CPU:65
+msgid "List of instruction tuples in (mnemonic, operands) format."
+msgstr ""
+
+#: of tiny8.assembler.AsmResult tiny8.cpu.CPU
+msgid "type"
+msgstr ""
+
+#: of tiny8.assembler.AsmResult:7 tiny8.cpu.CPU:67
+msgid "list[tuple[str, tuple]]"
+msgstr ""
+
+#: of tiny8.assembler.AsmResult:11
+msgid "Mapping of label names to program counter addresses."
+msgstr ""
+
+#: of tiny8.assembler.AsmResult:13 tiny8.cpu.CPU:73
+msgid "dict[str, int]"
+msgstr ""
+
+#: of tiny8.assembler.AsmResult:17 tiny8.cpu.CPU:55 tiny8.cpu.CPU:77
+msgid "Mapping of program counter to source line numbers."
+msgstr ""
+
+#: of tiny8.assembler.AsmResult:19 tiny8.cpu.CPU:79
+msgid "dict[int, int]"
+msgstr ""
+
+#: of tiny8.assembler.AsmResult:23
+msgid "Original source lines for display and debugging."
+msgstr ""
+
+#: of tiny8.assembler.AsmResult:25 tiny8.cpu.CPU:85
+msgid "list[str]"
+msgstr ""
+
+#: ../../api/tiny8.rst of tiny8.compiler.CodeGenerator.gen_expr
+#: tiny8.compiler.Lexer.tokenize tiny8.compiler.optimize_assembly
+#: tiny8.cpu.CPU.clear_traces tiny8.cpu.CPU.restore_snapshot
+#: tiny8.cpu.CPU.snapshot tiny8.memory.Memory.clear_changes
+#: tiny8.memory.Memory.restore_ram tiny8.tui.CacheProgressModalScreen.compose
+#: tiny8.tui.CheckpointManager.detect_loop
+#: tiny8.tui.CheckpointManager.invalidate_after
+#: tiny8.tui.CheckpointManager.precompute tiny8.tui.CheckpointManager.record
+#: tiny8.tui.CheckpointManager.record_if_interval
+#: tiny8.tui.CheckpointManager.restore_exact_step
+#: tiny8.tui.InstructionDetailModalScreen.compose
+#: tiny8.tui.InstructionReferenceScreen.compose
+#: tiny8.tui.MemoryWidget.get_heatmap_bg tiny8.tui.TUIHelpScreen.compose
+#: tiny8.tui.Tiny8App.action_cancel_command
+#: tiny8.tui.Tiny8App.action_continue_run tiny8.tui.Tiny8App.action_cycle_mode
+#: tiny8.tui.Tiny8App.action_exec_instruction tiny8.tui.Tiny8App.action_faster
+#: tiny8.tui.Tiny8App.action_open_command tiny8.tui.Tiny8App.action_open_editor
+#: tiny8.tui.Tiny8App.action_reverse_continue
+#: tiny8.tui.Tiny8App.action_scroll_down
+#: tiny8.tui.Tiny8App.action_scroll_page_down
+#: tiny8.tui.Tiny8App.action_scroll_page_up tiny8.tui.Tiny8App.action_scroll_up
+#: tiny8.tui.Tiny8App.action_show_help
+#: tiny8.tui.Tiny8App.action_show_instruction_detail
+#: tiny8.tui.Tiny8App.action_show_reference tiny8.tui.Tiny8App.action_slower
+#: tiny8.tui.Tiny8App.action_toggle_breakpoint
+#: tiny8.tui.Tiny8App.action_toggle_grayscale
+#: tiny8.tui.Tiny8App.action_toggle_hex tiny8.tui.Tiny8App.action_toggle_play
+#: tiny8.tui.Tiny8App.action_toggle_reverse_play tiny8.tui.Tiny8App.compose
+#: tiny8.tui.Tiny8App.on_input_submitted tiny8.tui.Tiny8App.watch_mem_start
+#: tiny8.tui.VimEditorScreen.compose tiny8.tui.eval_condition
+#: tiny8.tui.extract_call_frames tiny8.tui.get_widget_available_lines
+#: tiny8.tui.main tiny8.utils.ProgressBar.__enter__
+#: tiny8.utils.ProgressBar.__exit__ tiny8.utils.ProgressBar.close
+#: tiny8.utils.ProgressBar.reset
+msgid "Return type"
+msgstr ""
+
+#: of tiny8.assembler.parse_asm:1
+msgid "Parse assembly source text into an AsmResult structure."
+msgstr ""
+
+#: of tiny8.assembler.parse_asm:3
+msgid "Assembly source text."
+msgstr ""
+
+#: ../../api/tiny8.rst
+msgid "Returns"
+msgstr ""
+
+#: of tiny8.assembler.assemble:5 tiny8.assembler.assemble_file:5
+#: tiny8.assembler.parse_asm:5
+msgid "AsmResult containing parsed program, labels, and line mappings."
+msgstr ""
+
+#: of tiny8.assembler.assemble:1
+msgid "Assemble source text into program instructions and label mappings."
+msgstr ""
+
+#: of tiny8.assembler.assemble:3
+msgid "Assembly source code string."
+msgstr ""
+
+#: of tiny8.assembler.assemble_file:1
+msgid "Assemble source file into program instructions and label mappings."
+msgstr ""
+
+#: of tiny8.assembler.assemble_file:3
+msgid "Path to the assembly source file."
+msgstr ""
+
+#: ../../api/tiny8.rst
+msgid "Raises"
+msgstr ""
+
+#: of tiny8.assembler.assemble_file:7
+msgid "If the source file does not exist."
+msgstr ""
+
+#: of tiny8.assembler.assemble_file:8
+msgid "If reading the file fails."
+msgstr ""
+
+#: ../../api/tiny8.rst:16
+msgid "tiny8.cli module"
+msgstr ""
+
+#: of tiny8.cli:1
+msgid "Backward-compatibility wrapper forwarding to tiny8.tui."
+msgstr ""
+
+#: of tiny8.tui.main:1
+msgid "Entry point for tiny8 CLI supporting Assembly and C sources."
+msgstr ""
+
+#: of tiny8.tui.run_cli:1
+msgid ""
+"Launch modern Textual TUI debugger with OLED black theme and gradient "
+"heatmaps."
+msgstr ""
+
+#: of tiny8.tui.run_cli:3
+msgid "CPU emulator with execution history."
+msgstr ""
+
+#: of tiny8.tui.run_cli:4
+msgid "Start address for memory viewer."
+msgstr ""
+
+#: of tiny8.tui.run_cli:5
+msgid "End address for memory viewer."
+msgstr ""
+
+#: of tiny8.tui.run_cli:6
+msgid "Playback interval in seconds."
+msgstr ""
+
+#: of tiny8.tui.run_cli:7
+msgid "Source assembly or C lines."
+msgstr ""
+
+#: of tiny8.tui.run_cli:8
+msgid "C variable metadata symbols."
+msgstr ""
+
+#: ../../api/tiny8.rst:24
+msgid "tiny8.compiler module"
+msgstr ""
+
+#: of tiny8.compiler:1
+msgid "Simple C compiler for Tiny8 converting a subset of C into Tiny8 assembly."
+msgstr ""
+
+#: of tiny8.compiler:3
+msgid ""
+"Features: - Variable declarations and assignments (int/char) - Arithmetic"
+" (+, -, *, /, %), bitwise (&, |, ^, ~), logical (!), and relational (<, "
+"<=, >, >=, ==, !=) - Control structures: if / else, while, return - "
+"Functions with register-based parameter passing (R16..R19) and return "
+"value in R16 - Hardware builtins: peek(addr), poke(addr, val), in(port), "
+"out(port, val)"
+msgstr ""
+
+#: of tiny8.compiler.Token:1
+msgid "Lexical token."
+msgstr ""
+
+#: of tiny8.compiler.Lexer:1
+msgid "Tokenize C source code."
+msgstr ""
+
+#: of tiny8.compiler.Lexer.tokenize:1
+msgid "Convert input source into tokens, ignoring whitespace and comments."
+msgstr ""
+
+#: of tiny8.compiler.ASTNode:1
+msgid "Base AST node."
+msgstr ""
+
+#: of tiny8.compiler.ArrayAccess:1 tiny8.compiler.ArrayAssign:1
+#: tiny8.compiler.ArrayDecl:1 tiny8.compiler.Assign:1 tiny8.compiler.BinaryOp:1
+#: tiny8.compiler.Block:1 tiny8.compiler.BreakStmt:1 tiny8.compiler.Call:1
+#: tiny8.compiler.ExprStmt:1 tiny8.compiler.ForStmt:1
+#: tiny8.compiler.FunctionDef:1 tiny8.compiler.IfStmt:1
+#: tiny8.compiler.Literal:1 tiny8.compiler.Program:1
+#: tiny8.compiler.ReturnStmt:1 tiny8.compiler.StringLiteral:1
+#: tiny8.compiler.UnaryOp:1 tiny8.compiler.Var:1 tiny8.compiler.VarDecl:1
+#: tiny8.compiler.WhileStmt:1
+msgid "Bases: :py:class:`~tiny8.compiler.ASTNode`"
+msgstr ""
+
+#: of tiny8.compiler.Program:1
+msgid "Program root containing functions and global declarations."
+msgstr ""
+
+#: of tiny8.compiler.VarDecl:1
+msgid "Variable declaration."
+msgstr ""
+
+#: of tiny8.compiler.ArrayDecl:1
+msgid "Array variable declaration."
+msgstr ""
+
+#: of tiny8.compiler.ArrayAccess:1
+msgid "Array indexing expression: name[index]."
+msgstr ""
+
+#: of tiny8.compiler.ArrayAssign:1
+msgid "Array element assignment: name[index] = expr."
+msgstr ""
+
+#: of tiny8.compiler.FunctionDef:1
+msgid "Function definition."
+msgstr ""
+
+#: of tiny8.compiler.Block:1
+msgid "Block of statements."
+msgstr ""
+
+#: of tiny8.compiler.Assign:1
+msgid "Assignment statement."
+msgstr ""
+
+#: of tiny8.compiler.IfStmt:1
+msgid "If-else statement."
+msgstr ""
+
+#: of tiny8.compiler.WhileStmt:1
+msgid "While loop."
+msgstr ""
+
+#: of tiny8.compiler.ForStmt:1
+msgid "For loop."
+msgstr ""
+
+#: of tiny8.compiler.BreakStmt:1
+msgid "Break statement."
+msgstr ""
+
+#: of tiny8.compiler.ReturnStmt:1
+msgid "Return statement."
+msgstr ""
+
+#: of tiny8.compiler.ExprStmt:1
+msgid "Expression statement."
+msgstr ""
+
+#: of tiny8.compiler.BinaryOp:1
+msgid "Binary expression."
+msgstr ""
+
+#: of tiny8.compiler.UnaryOp:1
+msgid "Unary expression."
+msgstr ""
+
+#: of tiny8.compiler.Literal:1
+msgid "Literal integer value."
+msgstr ""
+
+#: of tiny8.compiler.StringLiteral:1
+msgid "String literal value."
+msgstr ""
+
+#: of tiny8.compiler.Var:1
+msgid "Variable reference."
+msgstr ""
+
+#: of tiny8.compiler.Call:1
+msgid "Function call expression."
+msgstr ""
+
+#: of tiny8.compiler.Parser:1
+msgid "Recursive descent parser."
+msgstr ""
+
+#: of tiny8.compiler.optimize_assembly:1
+msgid "Perform peephole optimizations on generated assembly lines."
+msgstr ""
+
+#: of tiny8.compiler.optimize_assembly:3
+msgid ""
+"Optimizations include: - Removing redundant self register moves (MOV Rx, "
+"Rx) - Simplifying PUSH Rx followed immediately by POP Ry into MOV Ry, Rx "
+"(or eliminating if Rx == Ry) - Removing redundant LD R16, R30 immediately"
+" after ST R30, R16 - Removing JMP <label> when the next line is <label>:"
+msgstr ""
+
+#: of tiny8.compiler.CodeGenerator:1
+msgid "Generate Tiny8 assembly from AST using register & stack model."
+msgstr ""
+
+#: of tiny8.compiler.CodeGenerator.gen_expr:1
+msgid "Evaluate expression, leaving the 8-bit result in R16."
+msgstr ""
+
+#: of tiny8.compiler.compile_c:1
+msgid "Compile C source code string into Tiny8 assembly."
+msgstr ""
+
+#: of tiny8.compiler.compile_c:3 tiny8.compiler.compile_c_with_symbols:3
+msgid "C language source code text."
+msgstr ""
+
+#: of tiny8.compiler.compile_c:4 tiny8.compiler.compile_c_file:4
+#: tiny8.compiler.compile_c_file_with_symbols:4
+#: tiny8.compiler.compile_c_with_symbols:4
+msgid "Whether to apply peephole optimization. Defaults to True."
+msgstr ""
+
+#: of tiny8.compiler.compile_c:6 tiny8.compiler.compile_c_file:6
+msgid "Generated Tiny8 assembly source string."
+msgstr ""
+
+#: of tiny8.compiler.compile_c_file:1
+msgid "Read and compile C source file into Tiny8 assembly."
+msgstr ""
+
+#: of tiny8.compiler.compile_c_file:3
+#: tiny8.compiler.compile_c_file_with_symbols:3
+msgid "Path to C source file."
+msgstr ""
+
+#: of tiny8.compiler.compile_c_with_symbols:1
+msgid "Compile C source into Tiny8 assembly alongside variable symbol table."
+msgstr ""
+
+#: of tiny8.compiler.compile_c_file_with_symbols:6
+#: tiny8.compiler.compile_c_with_symbols:6
+msgid "Tuple of (assembly_source_string, symbols_dict)."
+msgstr ""
+
+#: of tiny8.compiler.compile_c_file_with_symbols:1
+msgid "Read and compile C source file into Tiny8 assembly with symbol table."
+msgstr ""
+
+#: ../../api/tiny8.rst:32
+msgid "tiny8.cpu module"
+msgstr ""
+
+#: of tiny8.cpu:1
+msgid "Simplified AVR-like 8-bit CPU simulator."
+msgstr ""
+
+#: of tiny8.cpu.CPU:1
+msgid "Lightweight 8-bit AVR CPU emulator compliant with Microchip DS40002198A."
+msgstr ""
+
+#: of tiny8.cpu.CPU:3
+msgid "Optional Memory instance. Defaults to a new Memory instance."
+msgstr ""
+
+#: of tiny8.cpu.CPU:7
+msgid "Attached Memory instance."
+msgstr ""
+
+#: of tiny8.cpu.CPU:11
+msgid "List of 32 8-bit general purpose registers (R0..R31)."
+msgstr ""
+
+#: of tiny8.cpu.CPU:15 tiny8.cpu.CPU:17
+msgid "Current program counter address."
+msgstr ""
+
+#: of tiny8.cpu.CPU:19 tiny8.cpu.CPU:23
+msgid "Stack pointer pointing to current top of stack in RAM."
+msgstr ""
+
+#: of tiny8.cpu.CPU:23 tiny8.cpu.CPU:29
+msgid "Status register integer containing I, T, H, S, V, N, Z, C flags."
+msgstr ""
+
+#: of tiny8.cpu.CPU:27 tiny8.cpu.CPU:35
+msgid "Number of instructions executed so far."
+msgstr ""
+
+#: of tiny8.cpu.CPU:31 tiny8.cpu.CPU:41
+msgid "Mapping of interrupt vector addresses to enabled flags."
+msgstr ""
+
+#: of tiny8.cpu.CPU:35 tiny8.cpu.CPU:47
+msgid "Change history of registers as (step, reg_idx, new_val) tuples."
+msgstr ""
+
+#: of tiny8.cpu.CPU:39 tiny8.cpu.CPU:53
+msgid "Change history of RAM as (step, addr, new_val) tuples."
+msgstr ""
+
+#: of tiny8.cpu.CPU:43 tiny8.cpu.CPU:59
+msgid "Full per-step snapshots for tracing and visualization."
+msgstr ""
+
+#: of tiny8.cpu.CPU:51 tiny8.cpu.CPU:71
+msgid "Mapping of symbolic labels to program counter addresses."
+msgstr ""
+
+#: of tiny8.cpu.CPU:59 tiny8.cpu.CPU:83
+msgid "Original assembly source text lines."
+msgstr ""
+
+#: of tiny8.cpu.CPU:63 tiny8.cpu.CPU:89
+msgid "Flag indicating whether execution loop is active."
+msgstr ""
+
+#: of tiny8.cpu.CPU.clear_traces:1
+msgid "Clear execution traces and history to free memory."
+msgstr ""
+
+#: of tiny8.cpu.CPU.snapshot:1
+msgid "Capture complete CPU and memory execution state snapshot."
+msgstr ""
+
+#: of tiny8.cpu.CPU.restore_snapshot:1
+msgid "Restore CPU and memory execution state from a snapshot."
+msgstr ""
+
+#: of tiny8.cpu.CPU.set_flag:1
+msgid "Set or clear a status register flag bit."
+msgstr ""
+
+#: of tiny8.cpu.CPU.get_flag:3 tiny8.cpu.CPU.set_flag:3
+msgid "SREG bit index (0..7)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.set_flag:4
+msgid "True to set flag, False to clear."
+msgstr ""
+
+#: of tiny8.cpu.CPU.get_flag:1
+msgid "Return boolean status of a specific SREG bit."
+msgstr ""
+
+#: of tiny8.cpu.CPU.get_flag:5
+msgid "True if bit is set, False otherwise."
+msgstr ""
+
+#: of tiny8.cpu.CPU.read_reg:1
+msgid "Return 8-bit value from register r."
+msgstr ""
+
+#: of tiny8.cpu.CPU.read_reg:3 tiny8.cpu.CPU.write_reg:3
+msgid "Register index (0..31)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.read_reg:5
+msgid "8-bit unsigned integer value."
+msgstr ""
+
+#: of tiny8.cpu.CPU.write_reg:1
+msgid "Write 8-bit value to register r and trace changes."
+msgstr ""
+
+#: of tiny8.cpu.CPU.write_reg:4
+msgid "Integer value to store (masked to 8-bit)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.read_ram:1
+msgid "Read byte from RAM address."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_cbi:7 tiny8.cpu.CPU.op_sbi:7 tiny8.cpu.CPU.read_ram:3
+msgid "Memory address."
+msgstr ""
+
+#: of tiny8.cpu.CPU.read_ram:5
+msgid "Byte value stored at address."
+msgstr ""
+
+#: of tiny8.cpu.CPU.write_ram:1
+msgid "Write byte to RAM address and record memory trace."
+msgstr ""
+
+#: of tiny8.cpu.CPU.write_ram:3
+msgid "Target RAM address."
+msgstr ""
+
+#: of tiny8.cpu.CPU.write_ram:4
+msgid "Byte value to write."
+msgstr ""
+
+#: of tiny8.cpu.CPU.load_program:1
+msgid "Load assembled program instructions into CPU."
+msgstr ""
+
+#: of tiny8.cpu.CPU.load_program:3
+msgid "AsmResult object or list of (mnemonic, operands) tuples."
+msgstr ""
+
+#: of tiny8.cpu.CPU.load_program:4
+msgid "Label mapping if program is a raw list."
+msgstr ""
+
+#: of tiny8.cpu.CPU.load_program:5
+msgid "PC to line mapping if program is a raw list."
+msgstr ""
+
+#: of tiny8.cpu.CPU.load_program:6
+msgid "Source text lines if program is a raw list."
+msgstr ""
+
+#: of tiny8.cpu.CPU.step:1
+msgid "Execute next single instruction at current program counter."
+msgstr ""
+
+#: of tiny8.cpu.CPU.step:3
+msgid "Optional override to enable or disable trace recording for this step."
+msgstr ""
+
+#: of tiny8.cpu.CPU.step:5
+msgid "True if instruction executed successfully, False if PC is out of range."
+msgstr ""
+
+#: of tiny8.cpu.CPU.step:7
+msgid "If instruction mnemonic has no handler."
+msgstr ""
+
+#: of tiny8.cpu.CPU.run:1
+msgid "Run instructions until completion or max_steps limit is reached."
+msgstr ""
+
+#: of tiny8.cpu.CPU.run:3
+msgid "Maximum instruction step executions allowed."
+msgstr ""
+
+#: of tiny8.cpu.CPU.run:4
+msgid "Whether to show progress bar in terminal."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_nop:1
+msgid "No Operation (NOP)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_adc:3 tiny8.cpu.CPU.op_add:3 tiny8.cpu.CPU.op_adiw:3
+#: tiny8.cpu.CPU.op_and:3 tiny8.cpu.CPU.op_andi:3 tiny8.cpu.CPU.op_brcc:3
+#: tiny8.cpu.CPU.op_brcs:3 tiny8.cpu.CPU.op_breq:3 tiny8.cpu.CPU.op_brge:3
+#: tiny8.cpu.CPU.op_brlo:3 tiny8.cpu.CPU.op_brlt:3 tiny8.cpu.CPU.op_brmi:3
+#: tiny8.cpu.CPU.op_brne:3 tiny8.cpu.CPU.op_brpl:3 tiny8.cpu.CPU.op_brsh:3
+#: tiny8.cpu.CPU.op_call:3 tiny8.cpu.CPU.op_cbi:3 tiny8.cpu.CPU.op_cli:3
+#: tiny8.cpu.CPU.op_cp:3 tiny8.cpu.CPU.op_cpi:3 tiny8.cpu.CPU.op_cpse:3
+#: tiny8.cpu.CPU.op_dec:3 tiny8.cpu.CPU.op_eor:3 tiny8.cpu.CPU.op_in:3
+#: tiny8.cpu.CPU.op_inc:3 tiny8.cpu.CPU.op_jmp:3 tiny8.cpu.CPU.op_ld:3
+#: tiny8.cpu.CPU.op_ldi:3 tiny8.cpu.CPU.op_lds:3 tiny8.cpu.CPU.op_mov:3
+#: tiny8.cpu.CPU.op_nop:3 tiny8.cpu.CPU.op_or:3 tiny8.cpu.CPU.op_ori:3
+#: tiny8.cpu.CPU.op_out:3 tiny8.cpu.CPU.op_pop:3 tiny8.cpu.CPU.op_push:3
+#: tiny8.cpu.CPU.op_rcall:3 tiny8.cpu.CPU.op_ret:3 tiny8.cpu.CPU.op_reti:3
+#: tiny8.cpu.CPU.op_rjmp:3 tiny8.cpu.CPU.op_sbc:3 tiny8.cpu.CPU.op_sbci:3
+#: tiny8.cpu.CPU.op_sbi:3 tiny8.cpu.CPU.op_sbic:3 tiny8.cpu.CPU.op_sbis:3
+#: tiny8.cpu.CPU.op_sbiw:3 tiny8.cpu.CPU.op_sbrc:3 tiny8.cpu.CPU.op_sbrs:3
+#: tiny8.cpu.CPU.op_sei:3 tiny8.cpu.CPU.op_st:3 tiny8.cpu.CPU.op_sts:3
+#: tiny8.cpu.CPU.op_sub:3 tiny8.cpu.CPU.op_subi:3
+msgid "Per AVR Instruction Set Manual DS40002198A:"
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_nop:4
+msgid "Operation: No operation. Status Register (SREG): None."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_ldi:1
+msgid "Load Immediate (LDI)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_ldi:4
+msgid ""
+"Operation: Rd <- K (16 <= d <= 31, 0 <= K <= 255) Status Register (SREG):"
+" None."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_andi:7 tiny8.cpu.CPU.op_ldi:7 tiny8.cpu.CPU.op_ori:7
+#: tiny8.cpu.CPU.op_sbci:7 tiny8.cpu.CPU.op_subi:7
+msgid "Destination register index (16..31)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_cpi:8 tiny8.cpu.CPU.op_ldi:8
+msgid "Immediate byte value."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_mov:1
+msgid "Copy Register (MOV)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_mov:4
+msgid "Operation: Rd <- Rr (0 <= d, r <= 31) Status Register (SREG): None."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_adc:7 tiny8.cpu.CPU.op_add:7 tiny8.cpu.CPU.op_and:7
+#: tiny8.cpu.CPU.op_asr:7 tiny8.cpu.CPU.op_clr:7 tiny8.cpu.CPU.op_com:7
+#: tiny8.cpu.CPU.op_dec:7 tiny8.cpu.CPU.op_eor:7 tiny8.cpu.CPU.op_in:7
+#: tiny8.cpu.CPU.op_inc:7 tiny8.cpu.CPU.op_ld:9 tiny8.cpu.CPU.op_lds:7
+#: tiny8.cpu.CPU.op_lsl:7 tiny8.cpu.CPU.op_lsr:7 tiny8.cpu.CPU.op_mov:7
+#: tiny8.cpu.CPU.op_neg:6 tiny8.cpu.CPU.op_or:7 tiny8.cpu.CPU.op_pop:7
+#: tiny8.cpu.CPU.op_rol:7 tiny8.cpu.CPU.op_ror:7 tiny8.cpu.CPU.op_sbc:7
+#: tiny8.cpu.CPU.op_ser:6 tiny8.cpu.CPU.op_sub:7 tiny8.cpu.CPU.op_swap:6
+msgid "Destination register index."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_adc:8 tiny8.cpu.CPU.op_add:8 tiny8.cpu.CPU.op_and:8
+#: tiny8.cpu.CPU.op_eor:8 tiny8.cpu.CPU.op_mov:8 tiny8.cpu.CPU.op_or:8
+#: tiny8.cpu.CPU.op_out:8 tiny8.cpu.CPU.op_push:7 tiny8.cpu.CPU.op_sbc:8
+#: tiny8.cpu.CPU.op_st:10 tiny8.cpu.CPU.op_sts:8 tiny8.cpu.CPU.op_sub:8
+msgid "Source register index."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_add:1
+msgid "Add without Carry (ADD)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_add:4
+msgid "Operation: Rd <- Rd + Rr Status Register (SREG): H, S, V, N, Z, C"
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_and:1
+msgid "Logical AND (AND)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_and:4
+msgid ""
+"Operation: Rd <- Rd • Rr Status Register (SREG): S, V=0, N, Z (H, C "
+"unaffected)"
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_or:1
+msgid "Logical OR (OR)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_or:4
+msgid ""
+"Operation: Rd <- Rd v Rr Status Register (SREG): S, V=0, N, Z (H, C "
+"unaffected)"
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_eor:1
+msgid "Exclusive OR (EOR)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_eor:4
+msgid ""
+"Operation: Rd <- Rd ⊕ Rr Status Register (SREG): S, V=0, N, Z (H, C "
+"unaffected)"
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_sub:1
+msgid "Subtract without Carry (SUB)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_sub:4
+msgid "Operation: Rd <- Rd - Rr Status Register (SREG): H, S, V, N, Z, C"
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_inc:1
+msgid "Increment (INC)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_inc:4
+msgid "Operation: Rd <- Rd + 1 Status Register (SREG): S, V, N, Z (C unaffected)"
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_dec:1
+msgid "Decrement (DEC)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_dec:4
+msgid "Operation: Rd <- Rd - 1 Status Register (SREG): S, V, N, Z (C unaffected)"
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_mul:1
+msgid "Multiply Unsigned (MUL)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_mul:3
+msgid ""
+"AVR Instruction Set Manual DS40002198A: R1:R0 <- Rd * Rr (unsigned). SREG"
+" C: Set if bit 15 of result is set; cleared otherwise. SREG Z: Set if "
+"result is $0000; cleared otherwise."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_mul:8
+msgid "Multiplicand register index (0..31)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_mul:9
+msgid "Multiplier register index (0..31)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_muls:1
+msgid "Multiply Signed (MULS)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_muls:3
+msgid ""
+"AVR Instruction Set Manual DS40002198A: R1:R0 <- Rd * Rr (signed). SREG "
+"C: Set if bit 15 of result is set; cleared otherwise. SREG Z: Set if "
+"result is $0000; cleared otherwise."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_muls:8 tiny8.cpu.CPU.op_mulsu:8
+msgid "Multiplicand signed register index (0..31)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_muls:9
+msgid "Multiplier signed register index (0..31)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_mulsu:1
+msgid "Multiply Signed with Unsigned (MULSU)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_mulsu:3
+msgid ""
+"AVR Instruction Set Manual DS40002198A: R1:R0 <- Rd * Rr (Rd signed, Rr "
+"unsigned). SREG C: Set if bit 15 of result is set; cleared otherwise. "
+"SREG Z: Set if result is $0000; cleared otherwise."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_mulsu:9
+msgid "Multiplier unsigned register index (0..31)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_adc:1
+msgid "Add with Carry (ADC)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_adc:4
+msgid "Operation: Rd <- Rd + Rr + C Status Register (SREG): H, S, V, N, Z, C"
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_clr:1
+msgid "Clear Register: Rd <- Rd ⊕ Rd = $00 (EOR Rd, Rd)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_asr:3 tiny8.cpu.CPU.op_clr:3 tiny8.cpu.CPU.op_com:3
+#: tiny8.cpu.CPU.op_lsl:3 tiny8.cpu.CPU.op_lsr:3 tiny8.cpu.CPU.op_neg:3
+#: tiny8.cpu.CPU.op_rol:3 tiny8.cpu.CPU.op_ror:3 tiny8.cpu.CPU.op_ser:3
+#: tiny8.cpu.CPU.op_swap:3 tiny8.cpu.CPU.op_tst:3
+msgid "Status Register (SREG) per AVR Manual DS40002198A:"
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_clr:4
+msgid ""
+"S: 0, V: 0, N: 0, Z: 1; H, C, T, I unaffected. Alternative name to the "
+"EOR Rd, Rd instruction."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_ser:1
+msgid "Set Register: Rd <- $FF (LDI Rd, $FF)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_ser:4
+msgid "None affected. Alternative name to the LDI Rd, $FF instruction."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_in:1
+msgid "Load an I/O Location to Register (IN)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_in:4
+msgid "Operation: Rd <- P Status Register (SREG): None."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_in:8
+msgid "Port/memory address to read from."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_out:1
+msgid "Store Register to an I/O Location (OUT)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_out:4
+msgid "Operation: P <- Rr Status Register (SREG): None."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_out:7
+msgid "Port/memory address to write to."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_jmp:1
+msgid "Jump (JMP)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_jmp:4
+msgid "Operation: PC <- k Status Register (SREG): None."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_jmp:7
+msgid "Target label name or instruction address."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_jmp:9
+msgid "If target label string is not found."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_cpi:1
+msgid "Compare with Immediate (CPI)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_cpi:4
+msgid ""
+"Operation: Rd - K (16 <= d <= 31, 0 <= K <= 255) Status Register (SREG): "
+"H, S, V, N, Z, C"
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_cpi:7
+msgid "Register index to compare (16..31)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_cp:1
+msgid "Compare (CP)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_cp:4
+msgid "Operation: Rd - Rr Status Register (SREG): H, S, V, N, Z, C"
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_cp:7 tiny8.cpu.CPU.op_cpse:7
+msgid "First register index."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_cp:8 tiny8.cpu.CPU.op_cpse:8
+msgid "Second register index."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_lsl:1
+msgid "Logical Shift Left: C <- Rd7, Rd(n+1) <- Rd(n), Rd0 <- 0."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_lsl:4
+msgid ""
+"H: Rd3, S: N ⊕ V, V: N ⊕ C, N: R7, Z: Set if result is $00, C: Rd7 "
+"Alternative name to the ADD Rd, Rd instruction."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_lsr:1
+msgid "Logical Shift Right: 0 -> Rd7 -> ... -> Rd0 -> C."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_lsr:4
+msgid ""
+"S: N ⊕ V, V: C, N: 0, Z: Set if result is $00, C: Rd0 H, T, I unaffected "
+"(-)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_asr:1
+msgid "Arithmetic Shift Right: Rd7 -> Rd7 -> ... -> Rd0 -> C."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_asr:4 tiny8.cpu.CPU.op_ror:4
+msgid ""
+"S: N ⊕ V, V: N ⊕ C, N: R7, Z: Set if result is $00, C: Rd0 H, T, I "
+"unaffected (-)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_rol:1
+msgid "Rotate Left Through Carry: C <- Rd7, Rd(n+1) <- Rd(n), Rd0 <- C."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_rol:4
+msgid ""
+"H: Rd3, S: N ⊕ V, V: N ⊕ C, N: R7, Z: Set if result is $00, C: Rd7 "
+"Alternative name to the ADC Rd, Rd instruction."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_ror:1
+msgid "Rotate Right Through Carry: Rd7 <- C, Rd(n) <- Rd(n+1), C <- Rd0."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_com:1
+msgid "One's Complement: Rd <- $FF - Rd."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_com:4
+msgid ""
+"S: N ⊕ V, V: 0, N: R7, Z: Set if result is $00, C: 1 H, T, I unaffected "
+"(-)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_neg:1
+msgid "Two's Complement: Rd <- $00 - Rd."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_neg:4
+msgid ""
+"H: R3 + ~Rd3, S: N ⊕ V, V: Rd == $80, N: R7, Z: Set if result is $00, C: "
+"Rd != $00"
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_swap:1
+msgid "Swap Nibbles: Rd(7..4) <-> Rd(3..0)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_swap:4
+msgid "None affected."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_tst:1
+msgid "Test for Zero or Minus: Rd & Rd."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_tst:4
+msgid ""
+"S: N ⊕ V, V: 0, N: R7, Z: Set if Rd is $00 Alternative name to the AND "
+"Rd, Rd instruction."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_tst:7
+msgid "Register index to test."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_andi:1
+msgid "Logical AND with Immediate (ANDI)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_andi:4
+msgid ""
+"Operation: Rd <- Rd • K (16 <= d <= 31, 0 <= K <= 255) Status Register "
+"(SREG): S, V=0, N, Z (H, C unaffected)"
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_andi:8 tiny8.cpu.CPU.op_ori:8 tiny8.cpu.CPU.op_sbci:8
+#: tiny8.cpu.CPU.op_subi:8
+msgid "Immediate value."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_ori:1
+msgid "Logical OR with Immediate (ORI)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_ori:4
+msgid ""
+"Operation: Rd <- Rd v K (16 <= d <= 31, 0 <= K <= 255) Status Register "
+"(SREG): S, V=0, N, Z (H, C unaffected)"
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_subi:1
+msgid "Subtract Immediate (SUBI)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_subi:4
+msgid ""
+"Operation: Rd <- Rd - K (16 <= d <= 31, 0 <= K <= 255) Status Register "
+"(SREG): H, S, V, N, Z, C"
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_sbc:1
+msgid "Subtract with Carry (SBC)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_sbc:4
+msgid "Operation: Rd <- Rd - Rr - C Status Register (SREG): H, S, V, N, Z, C"
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_sbci:1
+msgid "Subtract Immediate with Carry (SBCI)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_sbci:4
+msgid ""
+"Operation: Rd <- Rd - K - C (16 <= d <= 31, 0 <= K <= 255) Status "
+"Register (SREG): H, S, V, N, Z, C"
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_sei:1
+msgid "Set Global Interrupt Flag (SEI)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_sei:4
+msgid "Operation: I <- 1 Status Register (SREG): I"
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_cli:1
+msgid "Clear Global Interrupt Flag (CLI)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_cli:4
+msgid "Operation: I <- 0 Status Register (SREG): I"
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_cpse:1
+msgid "Compare Skip if Equal (CPSE)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_cpse:4
+msgid ""
+"Operation: If Rd = Rr then PC <- PC + 2 (or 3) Status Register (SREG): "
+"None (all flags unaffected)"
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_sbrs:1
+msgid "Skip if Bit in Register is Set (SBRS)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_sbrs:4
+msgid ""
+"Operation: If Rd(b) = 1 then PC <- PC + 2 (or 3) Status Register (SREG): "
+"None."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_sbrc:7 tiny8.cpu.CPU.op_sbrs:7
+msgid "Register index."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_cbi:8 tiny8.cpu.CPU.op_sbi:8 tiny8.cpu.CPU.op_sbic:8
+#: tiny8.cpu.CPU.op_sbis:8 tiny8.cpu.CPU.op_sbrc:8 tiny8.cpu.CPU.op_sbrs:8
+msgid "Bit index (0..7)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_sbrc:1
+msgid "Skip if Bit in Register is Cleared (SBRC)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_sbrc:4
+msgid ""
+"Operation: If Rd(b) = 0 then PC <- PC + 2 (or 3) Status Register (SREG): "
+"None."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_sbis:1
+msgid "Skip if Bit in I/O Register is Set (SBIS)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_sbis:4
+msgid ""
+"Operation: If P(b) = 1 then PC <- PC + 2 (or 3) Status Register (SREG): "
+"None."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_sbic:7 tiny8.cpu.CPU.op_sbis:7
+msgid "I/O or RAM address."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_sbic:1
+msgid "Skip if Bit in I/O Register is Cleared (SBIC)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_sbic:4
+msgid ""
+"Operation: If P(b) = 0 then PC <- PC + 2 (or 3) Status Register (SREG): "
+"None."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_sbiw:1
+msgid "Subtract Immediate from Word (SBIW)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_sbiw:4
+#, python-brace-format
+msgid ""
+"Operation: Rd+1:Rd <- Rd+1:Rd - K (d in {24, 26, 28, 30}, 0 <= K <= 63) "
+"Status Register (SREG): S, V, N, Z, C"
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_adiw:7 tiny8.cpu.CPU.op_sbiw:7
+msgid "Low register index of register pair (e.g. 24, 26, 28, 30)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_sbiw:8
+msgid "Immediate value to subtract."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_adiw:1
+msgid "Add Immediate to Word (ADIW)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_adiw:4
+#, python-brace-format
+msgid ""
+"Operation: Rd+1:Rd <- Rd+1:Rd + K (d in {24, 26, 28, 30}, 0 <= K <= 63) "
+"Status Register (SREG): S, V, N, Z, C"
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_adiw:8
+msgid "Immediate value to add."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_rjmp:1
+msgid "Relative Jump (RJMP)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_rjmp:4
+msgid "Operation: PC <- PC + k + 1 Status Register (SREG): None."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_rjmp:7
+msgid "Jump target offset or symbolic label."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_rcall:1
+msgid "Relative Call to Subroutine (RCALL)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_rcall:4
+msgid "Operation: PC <- PC + k + 1, STACK <- PC + 1 Status Register (SREG): None."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_rcall:7
+msgid "Call target offset or symbolic label."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_sbi:1
+msgid "Set Bit in I/O Register (SBI)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_sbi:4
+msgid "Operation: I/O(P, b) <- 1 Status Register (SREG): None."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_cbi:1
+msgid "Clear Bit in I/O Register (CBI)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_cbi:4
+msgid "Operation: I/O(P, b) <- 0 Status Register (SREG): None."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_ld:1
+msgid "Load Indirect from Data Space to Register (LD)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_ld:4
+msgid "Operation: Rd <- (X / Y / Z) Status Register (SREG): None."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_ld:7 tiny8.cpu.CPU.op_st:7
+msgid ""
+"Supports 16-bit pointer pairs (X=R27:R26, Y=R29:R28, Z=R31:R30) when high"
+" byte is set."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_ld:10 tiny8.cpu.CPU.op_st:9
+msgid "Pointer register index."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_st:1
+msgid "Store Indirect from Register to Data Space (ST)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_st:4
+msgid "Operation: (X / Y / Z) <- Rr Status Register (SREG): None."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_lds:1
+msgid "Load Direct from Data Space (LDS)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_lds:4
+msgid "Operation: Rd <- (k) Status Register (SREG): None."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_lds:8 tiny8.cpu.CPU.op_sts:7
+msgid "Memory address (0..ram_size-1)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_sts:1
+msgid "Store Direct to Data Space (STS)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_sts:4
+msgid "Operation: (k) <- Rr Status Register (SREG): None."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_brne:1
+msgid "Branch if Not Equal (BRNE)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_brne:4
+msgid "Operation: If Z = 0 then PC <- PC + k + 1 Status Register (SREG): None."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_brcc:7 tiny8.cpu.CPU.op_brcs:7 tiny8.cpu.CPU.op_breq:7
+#: tiny8.cpu.CPU.op_brge:7 tiny8.cpu.CPU.op_brlo:7 tiny8.cpu.CPU.op_brlt:7
+#: tiny8.cpu.CPU.op_brmi:7 tiny8.cpu.CPU.op_brne:7 tiny8.cpu.CPU.op_brpl:7
+#: tiny8.cpu.CPU.op_brsh:7
+msgid "Jump target label or numeric address."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_breq:1
+msgid "Branch if Equal (BREQ)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_breq:4
+msgid "Operation: If Z = 1 then PC <- PC + k + 1 Status Register (SREG): None."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_brcs:1
+msgid "Branch if Carry Set (BRCS)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_brcs:4
+msgid "Operation: If C = 1 then PC <- PC + k + 1 Status Register (SREG): None."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_brcc:1
+msgid "Branch if Carry Cleared (BRCC)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_brcc:4
+msgid "Operation: If C = 0 then PC <- PC + k + 1 Status Register (SREG): None."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_brlo:1
+msgid "Branch if Lower Unsigned (BRLO)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_brlo:4
+msgid ""
+"Operation: If C = 1 then PC <- PC + k + 1 (alias for BRCS) Status "
+"Register (SREG): None."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_brsh:1
+msgid "Branch if Same or Higher Unsigned (BRSH)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_brsh:4
+msgid ""
+"Operation: If C = 0 then PC <- PC + k + 1 (alias for BRCC) Status "
+"Register (SREG): None."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_brge:1
+msgid "Branch if Greater or Equal Signed (BRGE)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_brge:4
+msgid ""
+"Operation: If S = 0 (N ⊕ V = 0) then PC <- PC + k + 1 Status Register "
+"(SREG): None."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_brlt:1
+msgid "Branch if Less Than Signed (BRLT)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_brlt:4
+msgid ""
+"Operation: If S = 1 (N ⊕ V = 1) then PC <- PC + k + 1 Status Register "
+"(SREG): None."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_brmi:1
+msgid "Branch if Minus (BRMI)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_brmi:4
+msgid "Operation: If N = 1 then PC <- PC + k + 1 Status Register (SREG): None."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_brpl:1
+msgid "Branch if Plus (BRPL)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_brpl:4
+msgid "Operation: If N = 0 then PC <- PC + k + 1 Status Register (SREG): None."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_push:1
+msgid "Push Register on Stack (PUSH)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_push:4
+msgid "Operation: STACK <- Rr, SP <- SP - 1 Status Register (SREG): None."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_pop:1
+msgid "Pop Register from Stack (POP)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_pop:4
+msgid "Operation: SP <- SP + 1, Rd <- STACK Status Register (SREG): None."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_call:1
+msgid "Long Call to Subroutine (CALL)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_call:4
+msgid "Operation: STACK <- PC + 1, PC <- k Status Register (SREG): None."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_call:7
+msgid "Subroutine target label or address."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_ret:1
+msgid "Return from Subroutine (RET)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_ret:4
+msgid "Operation: PC <- STACK Status Register (SREG): None."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_reti:1
+msgid "Return from Interrupt (RETI)."
+msgstr ""
+
+#: of tiny8.cpu.CPU.op_reti:4
+msgid "Operation: PC <- STACK, I <- 1 Status Register (SREG): I"
+msgstr ""
+
+#: of tiny8.cpu.CPU.trigger_interrupt:1
+msgid "Trigger an interrupt if enabled in vector configuration."
+msgstr ""
+
+#: of tiny8.cpu.CPU.trigger_interrupt:3
+msgid "Vector entry address in RAM."
+msgstr ""
+
+#: ../../api/tiny8.rst:40
+msgid "tiny8.memory module"
+msgstr ""
+
+#: of tiny8.memory:1
+msgid "Memory model for tiny8 providing RAM and ROM with change tracking."
+msgstr ""
+
+#: of tiny8.memory.Memory:1
+msgid "Byte-addressable RAM/ROM memory subsystem."
+msgstr ""
+
+#: of tiny8.memory.Memory:3
+msgid ""
+"Maintains separate RAM and ROM buffers as 8-bit unsigned bytes (0-255) "
+"and logs modifications for tracing and visualization."
+msgstr ""
+
+#: of tiny8.memory.Memory:6
+msgid "Number of bytes in RAM. Defaults to 65536."
+msgstr ""
+
+#: of tiny8.memory.Memory:7
+msgid "Number of bytes in ROM. Defaults to 2048."
+msgstr ""
+
+#: of tiny8.memory.Memory:11
+msgid "Size of RAM in bytes."
+msgstr ""
+
+#: of tiny8.memory.Memory:15
+msgid "Size of ROM in bytes."
+msgstr ""
+
+#: of tiny8.memory.Memory:19
+msgid "Bytearray representing RAM contents."
+msgstr ""
+
+#: of tiny8.memory.Memory:23
+msgid "Bytearray representing ROM contents."
+msgstr ""
+
+#: of tiny8.memory.Memory:27
+msgid "Log of RAM writes as (addr, old_val, new_val, step) tuples."
+msgstr ""
+
+#: of tiny8.memory.Memory:31
+msgid "Log of ROM writes as (addr, old_val, new_val, step) tuples."
+msgstr ""
+
+#: of tiny8.memory.Memory.read_ram:1
+msgid "Read a byte from RAM."
+msgstr ""
+
+#: of tiny8.memory.Memory.read_ram:3 tiny8.memory.Memory.write_ram:3
+msgid "Memory address in the range [0, ram_size)."
+msgstr ""
+
+#: of tiny8.memory.Memory.read_ram:5 tiny8.memory.Memory.read_rom:5
+msgid "The byte value stored at the address."
+msgstr ""
+
+#: of tiny8.memory.Memory.read_ram:7 tiny8.memory.Memory.write_ram:7
+msgid "If addr is outside valid RAM boundaries."
+msgstr ""
+
+#: of tiny8.memory.Memory.write_ram:1
+msgid "Write a byte to RAM and log change if value changed."
+msgstr ""
+
+#: of tiny8.memory.Memory.write_ram:4
+msgid "Byte value to store (masked to 8-bit)."
+msgstr ""
+
+#: of tiny8.memory.Memory.write_ram:5
+msgid "Step index associated with this write. Defaults to 0."
+msgstr ""
+
+#: of tiny8.memory.Memory.clear_changes:1
+msgid "Clear memory modification history to free memory."
+msgstr ""
+
+#: of tiny8.memory.Memory.restore_ram:1
+msgid "Restore RAM contents from a dictionary of non-zero entries."
+msgstr ""
+
+#: of tiny8.memory.Memory.load_rom:1
+msgid "Load byte sequence into ROM and record changes."
+msgstr ""
+
+#: of tiny8.memory.Memory.load_rom:3
+msgid "Sequence of byte values to load into ROM."
+msgstr ""
+
+#: of tiny8.memory.Memory.load_rom:5
+msgid "If data length exceeds configured rom_size."
+msgstr ""
+
+#: of tiny8.memory.Memory.read_rom:1
+msgid "Read a byte from ROM."
+msgstr ""
+
+#: of tiny8.memory.Memory.read_rom:3
+msgid "ROM address in the range [0, rom_size)."
+msgstr ""
+
+#: of tiny8.memory.Memory.read_rom:7
+msgid "If addr is outside valid ROM boundaries."
+msgstr ""
+
+#: of tiny8.memory.Memory.snapshot_ram:1
+msgid "Return a shallow copy of RAM contents."
+msgstr ""
+
+#: of tiny8.memory.Memory.snapshot_ram:3
+msgid "List of integers representing current RAM."
+msgstr ""
+
+#: of tiny8.memory.Memory.snapshot_rom:1
+msgid "Return a shallow copy of ROM contents."
+msgstr ""
+
+#: of tiny8.memory.Memory.snapshot_rom:3
+msgid "List of integers representing current ROM."
+msgstr ""
+
+#: ../../api/tiny8.rst:48
+msgid "tiny8.tui module"
+msgstr ""
+
+#: of tiny8.tui:1
+msgid "Modern Textual-based interactive debugger and dashboard for Tiny8."
+msgstr ""
+
+#: of tiny8.tui:3
+msgid ""
+"Provides an OLED black themed TUI with real-time registers, memory, SREG "
+"flags, gradient heatmap bars, stack explorer, breakpoints, and telemetry."
+msgstr ""
+
+#: of tiny8.tui.CheckpointManager:1
+msgid "Manages sparse snapshots and loop detection for time-travel."
+msgstr ""
+
+#: of tiny8.tui.CheckpointManager:3
+msgid ""
+"Stores complete CPU state snapshots every `interval` steps (default 100),"
+" enabling instant seeking and reverse playback without heavy RAM "
+"overhead."
+msgstr ""
+
+#: of tiny8.tui.CheckpointManager.record:1
+msgid "Store a CPU snapshot at the given step."
+msgstr ""
+
+#: of tiny8.tui.CheckpointManager.record_if_interval:1
+msgid "Record snapshot if step is a multiple of interval."
+msgstr ""
+
+#: of tiny8.tui.CheckpointManager.restore_exact_step:1
+msgid "Restore CPU to exact target_step using the closest preceding snapshot."
+msgstr ""
+
+#: of tiny8.tui.CheckpointManager.invalidate_after:1
+msgid "Invalidate checkpoints after modified step on memory/register edit."
+msgstr ""
+
+#: of tiny8.tui.CheckpointManager.detect_loop:1
+msgid "Detect infinite loop (e.g. self-jump HALT or cycling registers/PC)."
+msgstr ""
+
+#: of tiny8.tui.CheckpointManager.precompute:1
+msgid ""
+"Precompute execution checkpoints until an infinite loop or halt is "
+"detected."
+msgstr ""
+
+#: of tiny8.tui.interpolate_color:1
+msgid "Interpolate RGB color matching authentic Viridis style."
+msgstr ""
+
+#: of tiny8.tui.interpolate_color:3
+msgid "Float value from 0.0 to 1.0."
+msgstr ""
+
+#: of tiny8.tui.interpolate_color:5
+msgid "Hex RGB color string (e.g. '#FDE725')."
+msgstr ""
+
+#: of tiny8.tui.get_widget_available_lines:1
+msgid ""
+"Calculate visible content lines available for widget based on "
+"terminal/screen height."
+msgstr ""
+
+#: of tiny8.tui.render_btop_bar:1
+msgid "Render horizontal gradient heatmap bar with trailing dot fill."
+msgstr ""
+
+#: of tiny8.tui.render_btop_bar:3
+msgid "Current numerical value."
+msgstr ""
+
+#: of tiny8.tui.render_btop_bar:4
+msgid "Upper scale limit."
+msgstr ""
+
+#: of tiny8.tui.render_btop_bar:5
+msgid "Character width of bar."
+msgstr ""
+
+#: of tiny8.tui.render_btop_bar:7
+msgid "Rich Text object containing gradient blocks and shade dots."
+msgstr ""
+
+#: of tiny8.tui.BtopRegistersWidget:1 tiny8.tui.CVariablesWidget:1
+#: tiny8.tui.CallStackWidget:1 tiny8.tui.CodeViewWidget:1
+#: tiny8.tui.InstructionDetailWidget:1 tiny8.tui.LazyStatusWidget:1
+#: tiny8.tui.MemoryMatrixWidget:1 tiny8.tui.MemoryWidget:1
+#: tiny8.tui.RegistersWidget:1 tiny8.tui.SregWidget:1 tiny8.tui.StackWidget:1
+#: tiny8.tui.TelemetryWidget:1
+msgid "Bases: :py:class:`~textual.widgets._static.Static`"
+msgstr ""
+
+#: of tiny8.tui.SregWidget:1
+msgid "Badge-style display for SREG condition flags."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.prev_regs:1
+#: tiny8.tui.BtopRegistersWidget.regs:1 tiny8.tui.BtopRegistersWidget.start_r:1
+#: tiny8.tui.BtopRegistersWidget.visible_count:1
+#: tiny8.tui.CVariablesWidget.mem:1 tiny8.tui.CVariablesWidget.prev_mem:1
+#: tiny8.tui.CVariablesWidget.var_symbols:1
+#: tiny8.tui.CallStackWidget.current_pc:1 tiny8.tui.CallStackWidget.frames:1
+#: tiny8.tui.CodeViewWidget.breakpoints:1 tiny8.tui.CodeViewWidget.current_pc:1
+#: tiny8.tui.CodeViewWidget.pc_to_line:1 tiny8.tui.CodeViewWidget.program:1
+#: tiny8.tui.CodeViewWidget.source_lines:1
+#: tiny8.tui.InstructionDetailWidget.current_instr:1
+#: tiny8.tui.InstructionDetailWidget.pc:1
+#: tiny8.tui.InstructionDetailWidget.source_line:1
+#: tiny8.tui.InstructionDetailWidget.source_text:1
+#: tiny8.tui.InstructionDetailWidget.sp:1
+#: tiny8.tui.LazyStatusWidget.current_instr:1
+#: tiny8.tui.LazyStatusWidget.current_pc:1
+#: tiny8.tui.LazyStatusWidget.current_sp:1
+#: tiny8.tui.LazyStatusWidget.current_step:1
+#: tiny8.tui.LazyStatusWidget.filename:1 tiny8.tui.LazyStatusWidget.hint:1
+#: tiny8.tui.LazyStatusWidget.mode:1 tiny8.tui.LazyStatusWidget.sub_info:1
+#: tiny8.tui.LazyStatusWidget.total_steps:1
+#: tiny8.tui.MemoryMatrixWidget.base_addr:1 tiny8.tui.MemoryMatrixWidget.mem:1
+#: tiny8.tui.MemoryMatrixWidget.read_counts:1
+#: tiny8.tui.MemoryMatrixWidget.write_counts:1
+#: tiny8.tui.MemoryWidget.color_mode:1 tiny8.tui.MemoryWidget.mem:1
+#: tiny8.tui.MemoryWidget.prev_mem:1 tiny8.tui.MemoryWidget.show_hex:1
+#: tiny8.tui.MemoryWidget.start_addr:1 tiny8.tui.RegistersWidget.prev_regs:1
+#: tiny8.tui.RegistersWidget.regs:1 tiny8.tui.SregWidget.sreg:1
+#: tiny8.tui.StackWidget.mem:1 tiny8.tui.StackWidget.ram_size:1
+#: tiny8.tui.StackWidget.sp:1 tiny8.tui.TelemetryWidget.current_step:1
+#: tiny8.tui.TelemetryWidget.instr_counts:1
+#: tiny8.tui.TelemetryWidget.total_steps:1 tiny8.tui.Tiny8App.batch_size:1
+#: tiny8.tui.Tiny8App.breakpoints:1 tiny8.tui.Tiny8App.color_mode:1
+#: tiny8.tui.Tiny8App.current_idx:1 tiny8.tui.Tiny8App.execution_mode:1
+#: tiny8.tui.Tiny8App.mem_start:1 tiny8.tui.Tiny8App.play_direction:1
+#: tiny8.tui.Tiny8App.playback_rate_idx:1 tiny8.tui.Tiny8App.playing:1
+#: tiny8.tui.Tiny8App.reg_start:1 tiny8.tui.Tiny8App.show_hex:1
+#: tiny8.tui.Tiny8App.speed_ms:1 tiny8.tui.VimTextArea.is_modified:1
+#: tiny8.tui.VimTextArea.mode:1
+msgid "Create a reactive attribute."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.prev_regs:3
+#: tiny8.tui.BtopRegistersWidget.regs:3 tiny8.tui.BtopRegistersWidget.start_r:3
+#: tiny8.tui.BtopRegistersWidget.visible_count:3
+#: tiny8.tui.CVariablesWidget.mem:3 tiny8.tui.CVariablesWidget.prev_mem:3
+#: tiny8.tui.CVariablesWidget.var_symbols:3
+#: tiny8.tui.CallStackWidget.current_pc:3 tiny8.tui.CallStackWidget.frames:3
+#: tiny8.tui.CodeViewWidget.breakpoints:3 tiny8.tui.CodeViewWidget.current_pc:3
+#: tiny8.tui.CodeViewWidget.pc_to_line:3 tiny8.tui.CodeViewWidget.program:3
+#: tiny8.tui.CodeViewWidget.source_lines:3
+#: tiny8.tui.InstructionDetailWidget.current_instr:3
+#: tiny8.tui.InstructionDetailWidget.pc:3
+#: tiny8.tui.InstructionDetailWidget.source_line:3
+#: tiny8.tui.InstructionDetailWidget.source_text:3
+#: tiny8.tui.InstructionDetailWidget.sp:3
+#: tiny8.tui.LazyStatusWidget.current_instr:3
+#: tiny8.tui.LazyStatusWidget.current_pc:3
+#: tiny8.tui.LazyStatusWidget.current_sp:3
+#: tiny8.tui.LazyStatusWidget.current_step:3
+#: tiny8.tui.LazyStatusWidget.filename:3 tiny8.tui.LazyStatusWidget.hint:3
+#: tiny8.tui.LazyStatusWidget.mode:3 tiny8.tui.LazyStatusWidget.sub_info:3
+#: tiny8.tui.LazyStatusWidget.total_steps:3
+#: tiny8.tui.MemoryMatrixWidget.base_addr:3 tiny8.tui.MemoryMatrixWidget.mem:3
+#: tiny8.tui.MemoryMatrixWidget.read_counts:3
+#: tiny8.tui.MemoryMatrixWidget.write_counts:3
+#: tiny8.tui.MemoryWidget.color_mode:3 tiny8.tui.MemoryWidget.mem:3
+#: tiny8.tui.MemoryWidget.prev_mem:3 tiny8.tui.MemoryWidget.show_hex:3
+#: tiny8.tui.MemoryWidget.start_addr:3 tiny8.tui.RegistersWidget.prev_regs:3
+#: tiny8.tui.RegistersWidget.regs:3 tiny8.tui.SregWidget.sreg:3
+#: tiny8.tui.StackWidget.mem:3 tiny8.tui.StackWidget.ram_size:3
+#: tiny8.tui.StackWidget.sp:3 tiny8.tui.TelemetryWidget.current_step:3
+#: tiny8.tui.TelemetryWidget.instr_counts:3
+#: tiny8.tui.TelemetryWidget.total_steps:3 tiny8.tui.Tiny8App.batch_size:3
+#: tiny8.tui.Tiny8App.breakpoints:3 tiny8.tui.Tiny8App.color_mode:3
+#: tiny8.tui.Tiny8App.current_idx:3 tiny8.tui.Tiny8App.execution_mode:3
+#: tiny8.tui.Tiny8App.mem_start:3 tiny8.tui.Tiny8App.play_direction:3
+#: tiny8.tui.Tiny8App.playback_rate_idx:3 tiny8.tui.Tiny8App.playing:3
+#: tiny8.tui.Tiny8App.reg_start:3 tiny8.tui.Tiny8App.show_hex:3
+#: tiny8.tui.Tiny8App.speed_ms:3 tiny8.tui.VimTextArea.is_modified:3
+#: tiny8.tui.VimTextArea.mode:3
+msgid "A default value or callable that returns a default."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.prev_regs:4
+#: tiny8.tui.BtopRegistersWidget.regs:4 tiny8.tui.BtopRegistersWidget.start_r:4
+#: tiny8.tui.BtopRegistersWidget.visible_count:4
+#: tiny8.tui.CVariablesWidget.mem:4 tiny8.tui.CVariablesWidget.prev_mem:4
+#: tiny8.tui.CVariablesWidget.var_symbols:4
+#: tiny8.tui.CallStackWidget.current_pc:4 tiny8.tui.CallStackWidget.frames:4
+#: tiny8.tui.CodeViewWidget.breakpoints:4 tiny8.tui.CodeViewWidget.current_pc:4
+#: tiny8.tui.CodeViewWidget.pc_to_line:4 tiny8.tui.CodeViewWidget.program:4
+#: tiny8.tui.CodeViewWidget.source_lines:4
+#: tiny8.tui.InstructionDetailWidget.current_instr:4
+#: tiny8.tui.InstructionDetailWidget.pc:4
+#: tiny8.tui.InstructionDetailWidget.source_line:4
+#: tiny8.tui.InstructionDetailWidget.source_text:4
+#: tiny8.tui.InstructionDetailWidget.sp:4
+#: tiny8.tui.LazyStatusWidget.current_instr:4
+#: tiny8.tui.LazyStatusWidget.current_pc:4
+#: tiny8.tui.LazyStatusWidget.current_sp:4
+#: tiny8.tui.LazyStatusWidget.current_step:4
+#: tiny8.tui.LazyStatusWidget.filename:4 tiny8.tui.LazyStatusWidget.hint:4
+#: tiny8.tui.LazyStatusWidget.mode:4 tiny8.tui.LazyStatusWidget.sub_info:4
+#: tiny8.tui.LazyStatusWidget.total_steps:4
+#: tiny8.tui.MemoryMatrixWidget.base_addr:4 tiny8.tui.MemoryMatrixWidget.mem:4
+#: tiny8.tui.MemoryMatrixWidget.read_counts:4
+#: tiny8.tui.MemoryMatrixWidget.write_counts:4
+#: tiny8.tui.MemoryWidget.color_mode:4 tiny8.tui.MemoryWidget.mem:4
+#: tiny8.tui.MemoryWidget.prev_mem:4 tiny8.tui.MemoryWidget.show_hex:4
+#: tiny8.tui.MemoryWidget.start_addr:4 tiny8.tui.RegistersWidget.prev_regs:4
+#: tiny8.tui.RegistersWidget.regs:4 tiny8.tui.SregWidget.sreg:4
+#: tiny8.tui.StackWidget.mem:4 tiny8.tui.StackWidget.ram_size:4
+#: tiny8.tui.StackWidget.sp:4 tiny8.tui.TelemetryWidget.current_step:4
+#: tiny8.tui.TelemetryWidget.instr_counts:4
+#: tiny8.tui.TelemetryWidget.total_steps:4 tiny8.tui.Tiny8App.batch_size:4
+#: tiny8.tui.Tiny8App.breakpoints:4 tiny8.tui.Tiny8App.color_mode:4
+#: tiny8.tui.Tiny8App.current_idx:4 tiny8.tui.Tiny8App.execution_mode:4
+#: tiny8.tui.Tiny8App.mem_start:4 tiny8.tui.Tiny8App.play_direction:4
+#: tiny8.tui.Tiny8App.playback_rate_idx:4 tiny8.tui.Tiny8App.playing:4
+#: tiny8.tui.Tiny8App.reg_start:4 tiny8.tui.Tiny8App.show_hex:4
+#: tiny8.tui.Tiny8App.speed_ms:4 tiny8.tui.VimTextArea.is_modified:4
+#: tiny8.tui.VimTextArea.mode:4
+msgid "Perform a layout on change."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.prev_regs:5
+#: tiny8.tui.BtopRegistersWidget.regs:5 tiny8.tui.BtopRegistersWidget.start_r:5
+#: tiny8.tui.BtopRegistersWidget.visible_count:5
+#: tiny8.tui.CVariablesWidget.mem:5 tiny8.tui.CVariablesWidget.prev_mem:5
+#: tiny8.tui.CVariablesWidget.var_symbols:5
+#: tiny8.tui.CallStackWidget.current_pc:5 tiny8.tui.CallStackWidget.frames:5
+#: tiny8.tui.CodeViewWidget.breakpoints:5 tiny8.tui.CodeViewWidget.current_pc:5
+#: tiny8.tui.CodeViewWidget.pc_to_line:5 tiny8.tui.CodeViewWidget.program:5
+#: tiny8.tui.CodeViewWidget.source_lines:5
+#: tiny8.tui.InstructionDetailWidget.current_instr:5
+#: tiny8.tui.InstructionDetailWidget.pc:5
+#: tiny8.tui.InstructionDetailWidget.source_line:5
+#: tiny8.tui.InstructionDetailWidget.source_text:5
+#: tiny8.tui.InstructionDetailWidget.sp:5
+#: tiny8.tui.LazyStatusWidget.current_instr:5
+#: tiny8.tui.LazyStatusWidget.current_pc:5
+#: tiny8.tui.LazyStatusWidget.current_sp:5
+#: tiny8.tui.LazyStatusWidget.current_step:5
+#: tiny8.tui.LazyStatusWidget.filename:5 tiny8.tui.LazyStatusWidget.hint:5
+#: tiny8.tui.LazyStatusWidget.mode:5 tiny8.tui.LazyStatusWidget.sub_info:5
+#: tiny8.tui.LazyStatusWidget.total_steps:5
+#: tiny8.tui.MemoryMatrixWidget.base_addr:5 tiny8.tui.MemoryMatrixWidget.mem:5
+#: tiny8.tui.MemoryMatrixWidget.read_counts:5
+#: tiny8.tui.MemoryMatrixWidget.write_counts:5
+#: tiny8.tui.MemoryWidget.color_mode:5 tiny8.tui.MemoryWidget.mem:5
+#: tiny8.tui.MemoryWidget.prev_mem:5 tiny8.tui.MemoryWidget.show_hex:5
+#: tiny8.tui.MemoryWidget.start_addr:5 tiny8.tui.RegistersWidget.prev_regs:5
+#: tiny8.tui.RegistersWidget.regs:5 tiny8.tui.SregWidget.sreg:5
+#: tiny8.tui.StackWidget.mem:5 tiny8.tui.StackWidget.ram_size:5
+#: tiny8.tui.StackWidget.sp:5 tiny8.tui.TelemetryWidget.current_step:5
+#: tiny8.tui.TelemetryWidget.instr_counts:5
+#: tiny8.tui.TelemetryWidget.total_steps:5 tiny8.tui.Tiny8App.batch_size:5
+#: tiny8.tui.Tiny8App.breakpoints:5 tiny8.tui.Tiny8App.color_mode:5
+#: tiny8.tui.Tiny8App.current_idx:5 tiny8.tui.Tiny8App.execution_mode:5
+#: tiny8.tui.Tiny8App.mem_start:5 tiny8.tui.Tiny8App.play_direction:5
+#: tiny8.tui.Tiny8App.playback_rate_idx:5 tiny8.tui.Tiny8App.playing:5
+#: tiny8.tui.Tiny8App.reg_start:5 tiny8.tui.Tiny8App.show_hex:5
+#: tiny8.tui.Tiny8App.speed_ms:5 tiny8.tui.VimTextArea.is_modified:5
+#: tiny8.tui.VimTextArea.mode:5
+msgid "Perform a repaint on change."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.prev_regs:6
+#: tiny8.tui.BtopRegistersWidget.regs:6 tiny8.tui.BtopRegistersWidget.start_r:6
+#: tiny8.tui.BtopRegistersWidget.visible_count:6
+#: tiny8.tui.CVariablesWidget.mem:6 tiny8.tui.CVariablesWidget.prev_mem:6
+#: tiny8.tui.CVariablesWidget.var_symbols:6
+#: tiny8.tui.CallStackWidget.current_pc:6 tiny8.tui.CallStackWidget.frames:6
+#: tiny8.tui.CodeViewWidget.breakpoints:6 tiny8.tui.CodeViewWidget.current_pc:6
+#: tiny8.tui.CodeViewWidget.pc_to_line:6 tiny8.tui.CodeViewWidget.program:6
+#: tiny8.tui.CodeViewWidget.source_lines:6
+#: tiny8.tui.InstructionDetailWidget.current_instr:6
+#: tiny8.tui.InstructionDetailWidget.pc:6
+#: tiny8.tui.InstructionDetailWidget.source_line:6
+#: tiny8.tui.InstructionDetailWidget.source_text:6
+#: tiny8.tui.InstructionDetailWidget.sp:6
+#: tiny8.tui.LazyStatusWidget.current_instr:6
+#: tiny8.tui.LazyStatusWidget.current_pc:6
+#: tiny8.tui.LazyStatusWidget.current_sp:6
+#: tiny8.tui.LazyStatusWidget.current_step:6
+#: tiny8.tui.LazyStatusWidget.filename:6 tiny8.tui.LazyStatusWidget.hint:6
+#: tiny8.tui.LazyStatusWidget.mode:6 tiny8.tui.LazyStatusWidget.sub_info:6
+#: tiny8.tui.LazyStatusWidget.total_steps:6
+#: tiny8.tui.MemoryMatrixWidget.base_addr:6 tiny8.tui.MemoryMatrixWidget.mem:6
+#: tiny8.tui.MemoryMatrixWidget.read_counts:6
+#: tiny8.tui.MemoryMatrixWidget.write_counts:6
+#: tiny8.tui.MemoryWidget.color_mode:6 tiny8.tui.MemoryWidget.mem:6
+#: tiny8.tui.MemoryWidget.prev_mem:6 tiny8.tui.MemoryWidget.show_hex:6
+#: tiny8.tui.MemoryWidget.start_addr:6 tiny8.tui.RegistersWidget.prev_regs:6
+#: tiny8.tui.RegistersWidget.regs:6 tiny8.tui.SregWidget.sreg:6
+#: tiny8.tui.StackWidget.mem:6 tiny8.tui.StackWidget.ram_size:6
+#: tiny8.tui.StackWidget.sp:6 tiny8.tui.TelemetryWidget.current_step:6
+#: tiny8.tui.TelemetryWidget.instr_counts:6
+#: tiny8.tui.TelemetryWidget.total_steps:6 tiny8.tui.Tiny8App.batch_size:6
+#: tiny8.tui.Tiny8App.breakpoints:6 tiny8.tui.Tiny8App.color_mode:6
+#: tiny8.tui.Tiny8App.current_idx:6 tiny8.tui.Tiny8App.execution_mode:6
+#: tiny8.tui.Tiny8App.mem_start:6 tiny8.tui.Tiny8App.play_direction:6
+#: tiny8.tui.Tiny8App.playback_rate_idx:6 tiny8.tui.Tiny8App.playing:6
+#: tiny8.tui.Tiny8App.reg_start:6 tiny8.tui.Tiny8App.show_hex:6
+#: tiny8.tui.Tiny8App.speed_ms:6 tiny8.tui.VimTextArea.is_modified:6
+#: tiny8.tui.VimTextArea.mode:6
+msgid "Call watchers on initialize (post mount)."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.prev_regs:7
+#: tiny8.tui.BtopRegistersWidget.regs:7 tiny8.tui.BtopRegistersWidget.start_r:7
+#: tiny8.tui.BtopRegistersWidget.visible_count:7
+#: tiny8.tui.CVariablesWidget.mem:7 tiny8.tui.CVariablesWidget.prev_mem:7
+#: tiny8.tui.CVariablesWidget.var_symbols:7
+#: tiny8.tui.CallStackWidget.current_pc:7 tiny8.tui.CallStackWidget.frames:7
+#: tiny8.tui.CodeViewWidget.breakpoints:7 tiny8.tui.CodeViewWidget.current_pc:7
+#: tiny8.tui.CodeViewWidget.pc_to_line:7 tiny8.tui.CodeViewWidget.program:7
+#: tiny8.tui.CodeViewWidget.source_lines:7
+#: tiny8.tui.InstructionDetailWidget.current_instr:7
+#: tiny8.tui.InstructionDetailWidget.pc:7
+#: tiny8.tui.InstructionDetailWidget.source_line:7
+#: tiny8.tui.InstructionDetailWidget.source_text:7
+#: tiny8.tui.InstructionDetailWidget.sp:7
+#: tiny8.tui.LazyStatusWidget.current_instr:7
+#: tiny8.tui.LazyStatusWidget.current_pc:7
+#: tiny8.tui.LazyStatusWidget.current_sp:7
+#: tiny8.tui.LazyStatusWidget.current_step:7
+#: tiny8.tui.LazyStatusWidget.filename:7 tiny8.tui.LazyStatusWidget.hint:7
+#: tiny8.tui.LazyStatusWidget.mode:7 tiny8.tui.LazyStatusWidget.sub_info:7
+#: tiny8.tui.LazyStatusWidget.total_steps:7
+#: tiny8.tui.MemoryMatrixWidget.base_addr:7 tiny8.tui.MemoryMatrixWidget.mem:7
+#: tiny8.tui.MemoryMatrixWidget.read_counts:7
+#: tiny8.tui.MemoryMatrixWidget.write_counts:7
+#: tiny8.tui.MemoryWidget.color_mode:7 tiny8.tui.MemoryWidget.mem:7
+#: tiny8.tui.MemoryWidget.prev_mem:7 tiny8.tui.MemoryWidget.show_hex:7
+#: tiny8.tui.MemoryWidget.start_addr:7 tiny8.tui.RegistersWidget.prev_regs:7
+#: tiny8.tui.RegistersWidget.regs:7 tiny8.tui.SregWidget.sreg:7
+#: tiny8.tui.StackWidget.mem:7 tiny8.tui.StackWidget.ram_size:7
+#: tiny8.tui.StackWidget.sp:7 tiny8.tui.TelemetryWidget.current_step:7
+#: tiny8.tui.TelemetryWidget.instr_counts:7
+#: tiny8.tui.TelemetryWidget.total_steps:7 tiny8.tui.Tiny8App.batch_size:7
+#: tiny8.tui.Tiny8App.breakpoints:7 tiny8.tui.Tiny8App.color_mode:7
+#: tiny8.tui.Tiny8App.current_idx:7 tiny8.tui.Tiny8App.execution_mode:7
+#: tiny8.tui.Tiny8App.mem_start:7 tiny8.tui.Tiny8App.play_direction:7
+#: tiny8.tui.Tiny8App.playback_rate_idx:7 tiny8.tui.Tiny8App.playing:7
+#: tiny8.tui.Tiny8App.reg_start:7 tiny8.tui.Tiny8App.show_hex:7
+#: tiny8.tui.Tiny8App.speed_ms:7 tiny8.tui.VimTextArea.is_modified:7
+#: tiny8.tui.VimTextArea.mode:7
+msgid "Call watchers even when the new value equals the old value."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.prev_regs:8
+#: tiny8.tui.BtopRegistersWidget.regs:8 tiny8.tui.BtopRegistersWidget.start_r:8
+#: tiny8.tui.BtopRegistersWidget.visible_count:8
+#: tiny8.tui.CVariablesWidget.mem:8 tiny8.tui.CVariablesWidget.prev_mem:8
+#: tiny8.tui.CVariablesWidget.var_symbols:8
+#: tiny8.tui.CallStackWidget.current_pc:8 tiny8.tui.CallStackWidget.frames:8
+#: tiny8.tui.CodeViewWidget.breakpoints:8 tiny8.tui.CodeViewWidget.current_pc:8
+#: tiny8.tui.CodeViewWidget.pc_to_line:8 tiny8.tui.CodeViewWidget.program:8
+#: tiny8.tui.CodeViewWidget.source_lines:8
+#: tiny8.tui.InstructionDetailWidget.current_instr:8
+#: tiny8.tui.InstructionDetailWidget.pc:8
+#: tiny8.tui.InstructionDetailWidget.source_line:8
+#: tiny8.tui.InstructionDetailWidget.source_text:8
+#: tiny8.tui.InstructionDetailWidget.sp:8
+#: tiny8.tui.LazyStatusWidget.current_instr:8
+#: tiny8.tui.LazyStatusWidget.current_pc:8
+#: tiny8.tui.LazyStatusWidget.current_sp:8
+#: tiny8.tui.LazyStatusWidget.current_step:8
+#: tiny8.tui.LazyStatusWidget.filename:8 tiny8.tui.LazyStatusWidget.hint:8
+#: tiny8.tui.LazyStatusWidget.mode:8 tiny8.tui.LazyStatusWidget.sub_info:8
+#: tiny8.tui.LazyStatusWidget.total_steps:8
+#: tiny8.tui.MemoryMatrixWidget.base_addr:8 tiny8.tui.MemoryMatrixWidget.mem:8
+#: tiny8.tui.MemoryMatrixWidget.read_counts:8
+#: tiny8.tui.MemoryMatrixWidget.write_counts:8
+#: tiny8.tui.MemoryWidget.color_mode:8 tiny8.tui.MemoryWidget.mem:8
+#: tiny8.tui.MemoryWidget.prev_mem:8 tiny8.tui.MemoryWidget.show_hex:8
+#: tiny8.tui.MemoryWidget.start_addr:8 tiny8.tui.RegistersWidget.prev_regs:8
+#: tiny8.tui.RegistersWidget.regs:8 tiny8.tui.SregWidget.sreg:8
+#: tiny8.tui.StackWidget.mem:8 tiny8.tui.StackWidget.ram_size:8
+#: tiny8.tui.StackWidget.sp:8 tiny8.tui.TelemetryWidget.current_step:8
+#: tiny8.tui.TelemetryWidget.instr_counts:8
+#: tiny8.tui.TelemetryWidget.total_steps:8 tiny8.tui.Tiny8App.batch_size:8
+#: tiny8.tui.Tiny8App.breakpoints:8 tiny8.tui.Tiny8App.color_mode:8
+#: tiny8.tui.Tiny8App.current_idx:8 tiny8.tui.Tiny8App.execution_mode:8
+#: tiny8.tui.Tiny8App.mem_start:8 tiny8.tui.Tiny8App.play_direction:8
+#: tiny8.tui.Tiny8App.playback_rate_idx:8 tiny8.tui.Tiny8App.playing:8
+#: tiny8.tui.Tiny8App.reg_start:8 tiny8.tui.Tiny8App.show_hex:8
+#: tiny8.tui.Tiny8App.speed_ms:8 tiny8.tui.VimTextArea.is_modified:8
+#: tiny8.tui.VimTextArea.mode:8
+msgid "Compose the widget again when the attribute changes."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.prev_regs:9
+#: tiny8.tui.BtopRegistersWidget.regs:9 tiny8.tui.BtopRegistersWidget.start_r:9
+#: tiny8.tui.BtopRegistersWidget.visible_count:9
+#: tiny8.tui.CVariablesWidget.mem:9 tiny8.tui.CVariablesWidget.prev_mem:9
+#: tiny8.tui.CVariablesWidget.var_symbols:9
+#: tiny8.tui.CallStackWidget.current_pc:9 tiny8.tui.CallStackWidget.frames:9
+#: tiny8.tui.CodeViewWidget.breakpoints:9 tiny8.tui.CodeViewWidget.current_pc:9
+#: tiny8.tui.CodeViewWidget.pc_to_line:9 tiny8.tui.CodeViewWidget.program:9
+#: tiny8.tui.CodeViewWidget.source_lines:9
+#: tiny8.tui.InstructionDetailWidget.current_instr:9
+#: tiny8.tui.InstructionDetailWidget.pc:9
+#: tiny8.tui.InstructionDetailWidget.source_line:9
+#: tiny8.tui.InstructionDetailWidget.source_text:9
+#: tiny8.tui.InstructionDetailWidget.sp:9
+#: tiny8.tui.LazyStatusWidget.current_instr:9
+#: tiny8.tui.LazyStatusWidget.current_pc:9
+#: tiny8.tui.LazyStatusWidget.current_sp:9
+#: tiny8.tui.LazyStatusWidget.current_step:9
+#: tiny8.tui.LazyStatusWidget.filename:9 tiny8.tui.LazyStatusWidget.hint:9
+#: tiny8.tui.LazyStatusWidget.mode:9 tiny8.tui.LazyStatusWidget.sub_info:9
+#: tiny8.tui.LazyStatusWidget.total_steps:9
+#: tiny8.tui.MemoryMatrixWidget.base_addr:9 tiny8.tui.MemoryMatrixWidget.mem:9
+#: tiny8.tui.MemoryMatrixWidget.read_counts:9
+#: tiny8.tui.MemoryMatrixWidget.write_counts:9
+#: tiny8.tui.MemoryWidget.color_mode:9 tiny8.tui.MemoryWidget.mem:9
+#: tiny8.tui.MemoryWidget.prev_mem:9 tiny8.tui.MemoryWidget.show_hex:9
+#: tiny8.tui.MemoryWidget.start_addr:9 tiny8.tui.RegistersWidget.prev_regs:9
+#: tiny8.tui.RegistersWidget.regs:9 tiny8.tui.SregWidget.sreg:9
+#: tiny8.tui.StackWidget.mem:9 tiny8.tui.StackWidget.ram_size:9
+#: tiny8.tui.StackWidget.sp:9 tiny8.tui.TelemetryWidget.current_step:9
+#: tiny8.tui.TelemetryWidget.instr_counts:9
+#: tiny8.tui.TelemetryWidget.total_steps:9 tiny8.tui.Tiny8App.batch_size:9
+#: tiny8.tui.Tiny8App.breakpoints:9 tiny8.tui.Tiny8App.color_mode:9
+#: tiny8.tui.Tiny8App.current_idx:9 tiny8.tui.Tiny8App.execution_mode:9
+#: tiny8.tui.Tiny8App.mem_start:9 tiny8.tui.Tiny8App.play_direction:9
+#: tiny8.tui.Tiny8App.playback_rate_idx:9 tiny8.tui.Tiny8App.playing:9
+#: tiny8.tui.Tiny8App.reg_start:9 tiny8.tui.Tiny8App.show_hex:9
+#: tiny8.tui.Tiny8App.speed_ms:9 tiny8.tui.VimTextArea.is_modified:9
+#: tiny8.tui.VimTextArea.mode:9
+msgid "Refresh bindings when the reactive changes."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.prev_regs:10
+#: tiny8.tui.BtopRegistersWidget.regs:10
+#: tiny8.tui.BtopRegistersWidget.start_r:10
+#: tiny8.tui.BtopRegistersWidget.visible_count:10
+#: tiny8.tui.CVariablesWidget.mem:10 tiny8.tui.CVariablesWidget.prev_mem:10
+#: tiny8.tui.CVariablesWidget.var_symbols:10
+#: tiny8.tui.CallStackWidget.current_pc:10 tiny8.tui.CallStackWidget.frames:10
+#: tiny8.tui.CodeViewWidget.breakpoints:10
+#: tiny8.tui.CodeViewWidget.current_pc:10
+#: tiny8.tui.CodeViewWidget.pc_to_line:10 tiny8.tui.CodeViewWidget.program:10
+#: tiny8.tui.CodeViewWidget.source_lines:10
+#: tiny8.tui.InstructionDetailWidget.current_instr:10
+#: tiny8.tui.InstructionDetailWidget.pc:10
+#: tiny8.tui.InstructionDetailWidget.source_line:10
+#: tiny8.tui.InstructionDetailWidget.source_text:10
+#: tiny8.tui.InstructionDetailWidget.sp:10
+#: tiny8.tui.LazyStatusWidget.current_instr:10
+#: tiny8.tui.LazyStatusWidget.current_pc:10
+#: tiny8.tui.LazyStatusWidget.current_sp:10
+#: tiny8.tui.LazyStatusWidget.current_step:10
+#: tiny8.tui.LazyStatusWidget.filename:10 tiny8.tui.LazyStatusWidget.hint:10
+#: tiny8.tui.LazyStatusWidget.mode:10 tiny8.tui.LazyStatusWidget.sub_info:10
+#: tiny8.tui.LazyStatusWidget.total_steps:10
+#: tiny8.tui.MemoryMatrixWidget.base_addr:10
+#: tiny8.tui.MemoryMatrixWidget.mem:10
+#: tiny8.tui.MemoryMatrixWidget.read_counts:10
+#: tiny8.tui.MemoryMatrixWidget.write_counts:10
+#: tiny8.tui.MemoryWidget.color_mode:10 tiny8.tui.MemoryWidget.mem:10
+#: tiny8.tui.MemoryWidget.prev_mem:10 tiny8.tui.MemoryWidget.show_hex:10
+#: tiny8.tui.MemoryWidget.start_addr:10 tiny8.tui.RegistersWidget.prev_regs:10
+#: tiny8.tui.RegistersWidget.regs:10 tiny8.tui.SregWidget.sreg:10
+#: tiny8.tui.StackWidget.mem:10 tiny8.tui.StackWidget.ram_size:10
+#: tiny8.tui.StackWidget.sp:10 tiny8.tui.TelemetryWidget.current_step:10
+#: tiny8.tui.TelemetryWidget.instr_counts:10
+#: tiny8.tui.TelemetryWidget.total_steps:10 tiny8.tui.Tiny8App.batch_size:10
+#: tiny8.tui.Tiny8App.breakpoints:10 tiny8.tui.Tiny8App.color_mode:10
+#: tiny8.tui.Tiny8App.current_idx:10 tiny8.tui.Tiny8App.execution_mode:10
+#: tiny8.tui.Tiny8App.mem_start:10 tiny8.tui.Tiny8App.play_direction:10
+#: tiny8.tui.Tiny8App.playback_rate_idx:10 tiny8.tui.Tiny8App.playing:10
+#: tiny8.tui.Tiny8App.reg_start:10 tiny8.tui.Tiny8App.show_hex:10
+#: tiny8.tui.Tiny8App.speed_ms:10 tiny8.tui.VimTextArea.is_modified:10
+#: tiny8.tui.VimTextArea.mode:10
+msgid ""
+"An optional TCSS classname(s) to toggle based on the truthiness of the "
+"value."
+msgstr ""
+
+#: of tiny8.tui.BtopRegistersWidget.render:1
+#: tiny8.tui.CVariablesWidget.render:1 tiny8.tui.CallStackWidget.render:1
+#: tiny8.tui.CodeViewWidget.render:1 tiny8.tui.InstructionDetailWidget.render:1
+#: tiny8.tui.LazyStatusWidget.render:1 tiny8.tui.MemoryMatrixWidget.render:1
+#: tiny8.tui.MemoryWidget.render:1 tiny8.tui.RegistersWidget.render:1
+#: tiny8.tui.SregWidget.render:1 tiny8.tui.StackWidget.render:1
+#: tiny8.tui.TelemetryWidget.render:1
+msgid "Get a rich renderable for the widget's content."
+msgstr ""
+
+#: of tiny8.tui.BtopRegistersWidget.render:3
+#: tiny8.tui.CVariablesWidget.render:3 tiny8.tui.CallStackWidget.render:3
+#: tiny8.tui.CodeViewWidget.render:3 tiny8.tui.InstructionDetailWidget.render:3
+#: tiny8.tui.LazyStatusWidget.render:3 tiny8.tui.MemoryMatrixWidget.render:3
+#: tiny8.tui.MemoryWidget.render:3 tiny8.tui.RegistersWidget.render:3
+#: tiny8.tui.SregWidget.render:3 tiny8.tui.StackWidget.render:3
+#: tiny8.tui.TelemetryWidget.render:3
+msgid "A rich renderable."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.can_focus:1
+#: tiny8.tui.CVariablesWidget.can_focus:1
+#: tiny8.tui.CacheProgressModalScreen.can_focus:1
+#: tiny8.tui.CallStackWidget.can_focus:1 tiny8.tui.CodeViewWidget.can_focus:1
+#: tiny8.tui.InstructionDetailModalScreen.can_focus:1
+#: tiny8.tui.InstructionDetailWidget.can_focus:1
+#: tiny8.tui.InstructionReferenceScreen.can_focus:1
+#: tiny8.tui.LazyStatusWidget.can_focus:1
+#: tiny8.tui.MemoryMatrixWidget.can_focus:1 tiny8.tui.MemoryWidget.can_focus:1
+#: tiny8.tui.RegistersWidget.can_focus:1 tiny8.tui.SregWidget.can_focus:1
+#: tiny8.tui.StackWidget.can_focus:1 tiny8.tui.TUIHelpScreen.can_focus:1
+#: tiny8.tui.TelemetryWidget.can_focus:1 tiny8.tui.VimEditorScreen.can_focus:1
+#: tiny8.tui.VimTextArea.can_focus:1
+msgid "Widget may receive focus."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.can_focus_children:1
+#: tiny8.tui.CVariablesWidget.can_focus_children:1
+#: tiny8.tui.CacheProgressModalScreen.can_focus_children:1
+#: tiny8.tui.CallStackWidget.can_focus_children:1
+#: tiny8.tui.CodeViewWidget.can_focus_children:1
+#: tiny8.tui.InstructionDetailModalScreen.can_focus_children:1
+#: tiny8.tui.InstructionDetailWidget.can_focus_children:1
+#: tiny8.tui.InstructionReferenceScreen.can_focus_children:1
+#: tiny8.tui.LazyStatusWidget.can_focus_children:1
+#: tiny8.tui.MemoryMatrixWidget.can_focus_children:1
+#: tiny8.tui.MemoryWidget.can_focus_children:1
+#: tiny8.tui.RegistersWidget.can_focus_children:1
+#: tiny8.tui.SregWidget.can_focus_children:1
+#: tiny8.tui.StackWidget.can_focus_children:1
+#: tiny8.tui.TUIHelpScreen.can_focus_children:1
+#: tiny8.tui.TelemetryWidget.can_focus_children:1
+#: tiny8.tui.VimEditorScreen.can_focus_children:1
+#: tiny8.tui.VimTextArea.can_focus_children:1
+msgid "Widget's children may receive focus."
+msgstr ""
+
+#: of tiny8.tui.BtopRegistersWidget:1
+msgid "Register bars with graphical gradient heatmaps in a 2-column layout."
+msgstr ""
+
+#: of tiny8.tui.RegistersWidget:1
+msgid "Grid displaying 32 8-bit general purpose registers."
+msgstr ""
+
+#: of tiny8.tui.MemoryWidget:1
+msgid ""
+"32x32 Memory Dump with rich heatmap background coloring for direct visual"
+" rendering."
+msgstr ""
+
+#: of tiny8.tui.MemoryWidget.get_heatmap_bg:1
+msgid "Calculate rich heat color background for byte value 0..255."
+msgstr ""
+
+#: of tiny8.tui.StackWidget:1
+msgid "Call stack and stack pointer inspector."
+msgstr ""
+
+#: of tiny8.tui.InstructionDetailWidget:1
+msgid ""
+"Deep-dive inspector displaying current instruction details, syntax, and "
+"effects."
+msgstr ""
+
+#: of tiny8.tui.TelemetryWidget:1
+msgid "Real-time execution metrics and instruction distribution dashboard."
+msgstr ""
+
+#: of tiny8.tui.CodeViewWidget:1
+msgid ""
+"Assembly and source line inspection with execution pointer and "
+"breakpoints."
+msgstr ""
+
+#: of tiny8.tui.eval_condition:1
+msgid "Safely evaluate debugger watch and conditional breakpoint expressions."
+msgstr ""
+
+#: of tiny8.tui.extract_call_frames:1
+msgid "Reconstruct active function call frames up to current trace index."
+msgstr ""
+
+#: of tiny8.tui.CVariablesWidget:1
+msgid "Live C variable table showing symbol names, addresses, and runtime values."
+msgstr ""
+
+#: of tiny8.tui.CallStackWidget:1
+msgid "Dynamic function backtrace reconstructed from execution calls and returns."
+msgstr ""
+
+#: of tiny8.tui.MemoryMatrixWidget:1
+msgid "2D RAM access heatmap showing read and write activity across addresses."
+msgstr ""
+
+#: of tiny8.tui.CacheProgressModalScreen:1
+#: tiny8.tui.InstructionDetailModalScreen:1
+#: tiny8.tui.InstructionReferenceScreen:1 tiny8.tui.TUIHelpScreen:1
+msgid "Bases: :py:class:`~textual.screen.ModalScreen`"
+msgstr ""
+
+#: of tiny8.tui.CacheProgressModalScreen:1
+msgid ""
+"Sleek modal dialog displaying a progress bar while precomputing cache "
+"checkpoints."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.CacheProgressModalScreen.CSS:1
+#: tiny8.tui.InstructionDetailModalScreen.CSS:1
+#: tiny8.tui.InstructionReferenceScreen.CSS:1 tiny8.tui.TUIHelpScreen.CSS:1
+#: tiny8.tui.VimEditorScreen.CSS:1
+msgid ""
+"Inline CSS, useful for quick scripts. Rules here take priority over "
+"CSS_PATH."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.CacheProgressModalScreen.CSS:3
+#: tiny8.tui.InstructionDetailModalScreen.CSS:3
+#: tiny8.tui.InstructionReferenceScreen.CSS:3 tiny8.tui.TUIHelpScreen.CSS:3
+#: tiny8.tui.VimEditorScreen.CSS:3
+msgid "This CSS applies to the whole app."
+msgstr ""
+
+#: of tiny8.tui.CacheProgressModalScreen.__init__:1
+#: tiny8.tui.InstructionDetailModalScreen.__init__:1
+#: tiny8.tui.VimEditorScreen.__init__:1
+msgid "Initialize the screen."
+msgstr ""
+
+#: of tiny8.tui.CacheProgressModalScreen.__init__:3
+#: tiny8.tui.InstructionDetailModalScreen.__init__:3
+#: tiny8.tui.VimEditorScreen.__init__:3
+msgid "The name of the screen."
+msgstr ""
+
+#: of tiny8.tui.CacheProgressModalScreen.__init__:4
+#: tiny8.tui.InstructionDetailModalScreen.__init__:4
+#: tiny8.tui.VimEditorScreen.__init__:4
+msgid "The ID of the screen in the DOM."
+msgstr ""
+
+#: of tiny8.tui.CacheProgressModalScreen.__init__:5
+#: tiny8.tui.InstructionDetailModalScreen.__init__:5
+#: tiny8.tui.VimEditorScreen.__init__:5
+msgid "The CSS classes for the screen."
+msgstr ""
+
+#: of tiny8.tui.CacheProgressModalScreen.compose:1
+msgid "Compose modal progress bar widgets."
+msgstr ""
+
+#: of tiny8.tui.TUIHelpScreen:1
+msgid ""
+"Full-screen modal displaying TUI application usage, keyboard shortcuts, "
+"and guides."
+msgstr ""
+
+#: of tiny8.tui.TUIHelpScreen.compose:1
+msgid "Compose help screen dialog widgets."
+msgstr ""
+
+#: of tiny8.tui.InstructionDetailModalScreen:1
+msgid ""
+"Full-screen modal displaying in-depth specifications for the currently "
+"selected instruction."
+msgstr ""
+
+#: of tiny8.tui.InstructionDetailModalScreen.compose:1
+msgid "Compose instruction detail modal widgets."
+msgstr ""
+
+#: of tiny8.tui.InstructionReferenceScreen:1
+msgid "Full-screen reference modal showing all instruction details."
+msgstr ""
+
+#: of tiny8.tui.InstructionReferenceScreen.compose:1
+msgid "Compose instruction reference modal widgets."
+msgstr ""
+
+#: of tiny8.tui.LazyStatusWidget:1
+msgid "Bottom statusline with mode badge, file stats, and help hint."
+msgstr ""
+
+#: of tiny8.tui.VimTextArea:1
+msgid "Bases: :py:class:`~textual.widgets._text_area.TextArea`"
+msgstr ""
+
+#: of tiny8.tui.VimTextArea:1
+msgid "TextArea enhanced with Vim modal navigation and editing."
+msgstr ""
+
+#: of tiny8.tui.VimEditorScreen:1
+msgid "Bases: :py:class:`~textual.screen.Screen`"
+msgstr ""
+
+#: of tiny8.tui.VimEditorScreen:1
+msgid "Full-screen modal Vim editor for creating and modifying C and ASM files."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.VimEditorScreen.BINDINGS:1
+msgid "A list of key bindings."
+msgstr ""
+
+#: of tiny8.tui.VimEditorScreen.compose:1
+msgid "Compose widgets for the Vim editor screen."
+msgstr ""
+
+#: of tiny8.tui.Tiny8App:1
+msgid "Bases: :py:class:`~textual.app.App`"
+msgstr ""
+
+#: of tiny8.tui.Tiny8App:1
+msgid ""
+"Textual application with OLED black background and advanced debugger "
+"features."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.Tiny8App.TITLE:1
+msgid "A class variable to set the *default* title for the application."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.Tiny8App.TITLE:3
+msgid ""
+"To update the title while the app is running, you can set the "
+"[title][textual.app.App.title] attribute. See also [the `Screen.TITLE` "
+"attribute][textual.screen.Screen.TITLE]."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.Tiny8App.CSS:1
+msgid ""
+"Inline CSS, useful for quick scripts. This is loaded after CSS_PATH, and "
+"therefore takes priority in the event of a specificity clash."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.Tiny8App.BINDINGS:1
+msgid "The default key bindings."
+msgstr ""
+
+#: of tiny8.tui.Tiny8App.__init__:1
+msgid "Create an instance of an app."
+msgstr ""
+
+#: of tiny8.tui.Tiny8App.__init__:3
+msgid ""
+"Driver class or `None` to auto-detect. This will be used by some Textual "
+"tools."
+msgstr ""
+
+#: of tiny8.tui.Tiny8App.__init__:5
+msgid ""
+"Path to CSS or `None` to use the `CSS_PATH` class variable. To load "
+"multiple CSS files, pass a list of strings or paths which will be loaded "
+"in order."
+msgstr ""
+
+#: of tiny8.tui.Tiny8App.__init__:8
+msgid ""
+"Reload CSS if the files changed. This is set automatically if you are "
+"using `textual run` with the `dev` switch."
+msgstr ""
+
+#: of tiny8.tui.Tiny8App.__init__:10
+msgid ""
+"Allow ANSI colors if `True`, or convert ANSI colors to RGB if `False`, "
+"`None` to use \"ansi\" parameter from themes."
+msgstr ""
+
+#: of tiny8.tui.Tiny8App.__init__:12
+msgid "When the supplied CSS path(s) are an unexpected type."
+msgstr ""
+
+#: of tiny8.tui.Tiny8App.compose:1
+msgid "Compose the root application layout and widgets."
+msgstr ""
+
+#: of tiny8.tui.Tiny8App.action_open_editor:1
+msgid "Open full-screen Vim editor for source code."
+msgstr ""
+
+#: of tiny8.tui.Tiny8App.action_toggle_breakpoint:1
+msgid "Toggle breakpoint on current PC."
+msgstr ""
+
+#: of tiny8.tui.Tiny8App.action_continue_run:1
+msgid "Run forward until next breakpoint, watchpoint, or program completion."
+msgstr ""
+
+#: of tiny8.tui.Tiny8App.action_reverse_continue:1
+msgid "Run backward until previous breakpoint, watchpoint, or program start."
+msgstr ""
+
+#: of tiny8.tui.Tiny8App.action_exec_instruction:1
+msgid "Execute an assembly instruction dynamically in REPL mode."
+msgstr ""
+
+#: of tiny8.tui.Tiny8App.watch_mem_start:1
+msgid "Update only the memory widget when mem_start changes."
+msgstr ""
+
+#: of tiny8.tui.Tiny8App.action_scroll_down:1
+msgid "Scroll memory down (1 row = 32 bytes)."
+msgstr ""
+
+#: of tiny8.tui.Tiny8App.action_scroll_up:1
+msgid "Scroll memory up (1 row = 32 bytes)."
+msgstr ""
+
+#: of tiny8.tui.Tiny8App.action_scroll_page_down:1
+msgid "Fast scroll memory down (4 rows = 128 bytes)."
+msgstr ""
+
+#: of tiny8.tui.Tiny8App.action_scroll_page_up:1
+msgid "Fast scroll memory up (4 rows = 128 bytes)."
+msgstr ""
+
+#: of tiny8.tui.Tiny8App.action_open_command:1
+msgid "Open command bar input."
+msgstr ""
+
+#: of tiny8.tui.Tiny8App.action_cancel_command:1
+msgid "Cancel and close command input or dismiss modal dialog."
+msgstr ""
+
+#: of tiny8.tui.Tiny8App.on_input_submitted:1
+msgid "Process entered command."
+msgstr ""
+
+#: of tiny8.tui.Tiny8App.action_toggle_grayscale:1
+msgid "Toggle between Viridis and Grayscale color palette."
+msgstr ""
+
+#: of tiny8.tui.Tiny8App.action_toggle_hex:1
+msgid "Toggle between Hexadecimal digits (02X) and Graphic Pixel blocks."
+msgstr ""
+
+#: of tiny8.tui.Tiny8App.action_cycle_mode:1
+msgid ""
+"Cycle view modes (Viridis+Hex -> Viridis+Pixel -> Grayscale+Pixel -> "
+"Grayscale+Hex)."
+msgstr ""
+
+#: of tiny8.tui.Tiny8App.action_show_help:1
+msgid "Show full TUI application usage and keyboard guide."
+msgstr ""
+
+#: of tiny8.tui.Tiny8App.action_show_instruction_detail:1
+msgid ""
+"Show in-depth specification and effects for the currently selected "
+"instruction."
+msgstr ""
+
+#: of tiny8.tui.Tiny8App.action_show_reference:1
+msgid "Show full instruction set reference modal."
+msgstr ""
+
+#: of tiny8.tui.Tiny8App.action_toggle_play:1
+msgid "Toggle forward automatic playback."
+msgstr ""
+
+#: of tiny8.tui.Tiny8App.action_toggle_reverse_play:1
+msgid "Toggle reverse automatic playback (time-travel replay)."
+msgstr ""
+
+#: of tiny8.tui.Tiny8App.action_faster:1
+msgid "Increase playback execution speed."
+msgstr ""
+
+#: of tiny8.tui.Tiny8App.action_faster:3
+msgid ""
+"Decreases timer interval down to visual limit (30ms / ~33 fps), then "
+"automatically transitions to adaptive batch processing scaling up to "
+"50,000 steps per tick."
+msgstr ""
+
+#: of tiny8.tui.Tiny8App.action_slower:1
+msgid "Decrease playback execution speed."
+msgstr ""
+
+#: of tiny8.tui.Tiny8App.action_slower:3
+msgid ""
+"Scales down batch processing first, then transitions back to observable "
+"visual delay."
+msgstr ""
+
+#: ../../api/tiny8.rst:56
+msgid "tiny8.utils module"
+msgstr ""
+
+#: of tiny8.utils:1
+msgid "Utility helpers for tiny8 including terminal progress bar."
+msgstr ""
+
+#: of tiny8.utils.ProgressBar:1
+msgid "Terminal progress bar indicator adapting to terminal width."
+msgstr ""
+
+#: of tiny8.utils.ProgressBar:3
+msgid "Total number of iterations, or None for indeterminate progress."
+msgstr ""
+
+#: of tiny8.utils.ProgressBar:4
+msgid "Prefix description string. Defaults to \"\"."
+msgstr ""
+
+#: of tiny8.utils.ProgressBar:5
+msgid "True to disable output completely. Defaults to False."
+msgstr ""
+
+#: of tiny8.utils.ProgressBar:6
+msgid "Explicit width in characters, or None for auto-detection."
+msgstr ""
+
+#: of tiny8.utils.ProgressBar:7
+msgid "Minimum interval in seconds between screen refreshes."
+msgstr ""
+
+#: of tiny8.utils.ProgressBar:11
+msgid "Total iterations expected."
+msgstr ""
+
+#: of tiny8.utils.ProgressBar:15
+msgid "Description prefix text."
+msgstr ""
+
+#: of tiny8.utils.ProgressBar:19
+msgid "Flag controlling output suppression."
+msgstr ""
+
+#: of tiny8.utils.ProgressBar:23
+msgid "Target bar character width."
+msgstr ""
+
+#: of tiny8.utils.ProgressBar:27
+msgid "Refresh rate throttle in seconds."
+msgstr ""
+
+#: of tiny8.utils.ProgressBar:31
+msgid "Current iteration step count."
+msgstr ""
+
+#: of tiny8.utils.ProgressBar:35
+msgid "Monotonic start timestamp."
+msgstr ""
+
+#: of tiny8.utils.ProgressBar:39
+msgid "Timestamp of last bar render."
+msgstr ""
+
+#: of tiny8.utils.ProgressBar.__enter__:1
+msgid "Enter context manager."
+msgstr ""
+
+#: of tiny8.utils.ProgressBar.__exit__:1
+msgid "Exit context manager and flush output."
+msgstr ""
+
+#: of tiny8.utils.ProgressBar.update:1
+msgid "Increment progress by n steps."
+msgstr ""
+
+#: of tiny8.utils.ProgressBar.update:3
+msgid "Number of iterations to increment. Defaults to 1."
+msgstr ""
+
+#: of tiny8.utils.ProgressBar.set_description:1
+msgid "Update description prefix and re-render bar."
+msgstr ""
+
+#: of tiny8.utils.ProgressBar.set_description:3
+msgid "New description text."
+msgstr ""
+
+#: of tiny8.utils.ProgressBar.close:1
+msgid "Finalize progress bar and print trailing newline."
+msgstr ""
+
+#: of tiny8.utils.ProgressBar.reset:1
+msgid "Reset progress counter and timers to initial state."
+msgstr ""
+
+#: ../../api/tiny8.rst:64
+msgid "Module contents"
+msgstr ""
+
+#: of tiny8:1
+msgid "A tiny AVR-like 8-bit CPU simulator package."
+msgstr ""
+
+#: of tiny8:3
+msgid ""
+"Provides a compact CPU implementation, assembler, C compiler, and "
+"interactive Textual CLI for experimentation and teaching."
+msgstr ""
+
+#: of tiny8.cpu.CPU:13
+msgid "list[int]"
+msgstr ""
+
+#: of tiny8.cpu.CPU:19 tiny8.cpu.CPU:25 tiny8.cpu.CPU:31 tiny8.cpu.CPU:37
+msgid "int"
+msgstr ""
+
+#: of tiny8.cpu.CPU:43
+msgid "dict[int, bool]"
+msgstr ""
+
+#: of tiny8.cpu.CPU:49 tiny8.cpu.CPU:55
+msgid "collections.deque[tuple[int, int, int]]"
+msgstr ""
+
+#: of tiny8.cpu.CPU:61
+msgid "collections.deque[dict]"
+msgstr ""
+
+#: of tiny8.cpu.CPU:91
+msgid "bool"
+msgstr ""
+
+#~ msgid ""
+#~ "Launch modern Textual TUI debugger with"
+#~ " OLED black theme and btop heatmaps."
+#~ msgstr ""
+
+#~ msgid ""
+#~ "Provides an OLED black themed TUI "
+#~ "with real-time registers, memory, SREG"
+#~ " flags, btop-style gradient heatmap "
+#~ "bars, stack explorer, breakpoints, and "
+#~ "telemetry."
+#~ msgstr ""
+
+#~ msgid ""
+#~ "Btop-style register bars with graphical"
+#~ " gradient heatmaps in a 2-column "
+#~ "layout."
+#~ msgstr ""
+
+#~ msgid "Number of bytes in RAM. Defaults to 2048."
+#~ msgstr ""
+
+#~ msgid "Exclusive OR with Immediate (EORI)."
+#~ msgstr ""
+
+#~ msgid ""
+#~ "Operation: Rd <- Rd ⊕ K (16 "
+#~ "<= d <= 31, 0 <= K <= "
+#~ "255) Status Register (SREG): S, V=0, "
+#~ "N, Z (H, C unaffected)"
+#~ msgstr ""
+
diff --git a/docs/locales/ja/LC_MESSAGES/architecture.po b/docs/locales/ja/LC_MESSAGES/architecture.po
new file mode 100644
index 0000000..46bb3c8
--- /dev/null
+++ b/docs/locales/ja/LC_MESSAGES/architecture.po
@@ -0,0 +1,1020 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, 2026.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-25 01:27+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language: ja\n"
+"Language-Team: ja <LL@li.org>\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=utf-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Generated-By: Babel 2.17.0\n"
+
+#: ../../architecture.rst:2
+msgid "Architecture"
+msgstr "アーキテクチャ"
+
+#: ../../architecture.rst:4
+msgid ""
+"This guide provides a detailed overview of the Tiny8 CPU architecture, "
+"including its registers, memory model, instruction execution, and status "
+"flags."
+msgstr "本ガイドでは、レジスタ、メモリモデル、命令実行、ステータスフラグなど、Tiny8 CPUアーキテクチャの詳細な概要を解説します。"
+
+#: ../../architecture.rst:7
+msgid "CPU Overview"
+msgstr "CPU概要"
+
+#: ../../architecture.rst:9
+msgid ""
+"Tiny8 implements an 8-bit RISC CPU architecture modeled directly after "
+"the Atmel / Microchip AVR instruction set architecture. Instruction "
+"semantics, flag behaviors, and operations strictly adhere to the official"
+" specification:"
+msgstr ""
+"Tiny8は、Atmel / Microchip AVR命令セットアーキテクチャを忠実にモデル化した8ビットRISC "
+"CPUアーキテクチャを実装しています。命令の動作仕様、フラグ動作、演算仕様は公式仕様に厳密に準拠しています:"
+
+#: ../../architecture.rst:11
+msgid ""
+"**Official Specification**: `Microchip AVR® Instruction Set Manual "
+"(DS40002198A) <https://ww1.microchip.com/downloads/en/DeviceDoc/AVR-"
+"Instruction-Set-Manual-DS40002198A.pdf>`_"
+msgstr ""
+"**公式仕様書**: `Microchip AVR® Instruction Set Manual (DS40002198A) "
+"<https://ww1.microchip.com/downloads/en/DeviceDoc/AVR-Instruction-Set-"
+"Manual-DS40002198A.pdf>`_"
+
+#: ../../architecture.rst:13
+msgid ""
+"The design balances hardware realism with educational clarity, providing "
+"full visibility and interactive step debugging."
+msgstr "ハードウェアの現実性と教育的な分かりやすさを両立し、高い可視性とインタラクティブなステップ実行デバッグを提供します。"
+
+#: ../../architecture.rst:16
+msgid "Key Specifications"
+msgstr "主要仕様"
+
+#: ../../architecture.rst:18
+msgid "**Word size**: 8 bits"
+msgstr "**ワード長**: 8ビット"
+
+#: ../../architecture.rst:19
+msgid "**Registers**: 32 general-purpose 8-bit registers (R0-R31)"
+msgstr "**レジスタ**: 32本の8ビット汎用レジスタ (R0-R31)"
+
+#: ../../architecture.rst:20
+msgid "**Memory**: 64KB RAM (configurable)"
+msgstr "**メモリ**: 64KB RAM (設定変更可能)"
+
+#: ../../architecture.rst:21
+msgid "**Stack**: Grows downward from high memory (SP decrements on push)"
+msgstr "**スタック**: 高位アドレスから下位へ伸長 (プッシュ時にSPがデクリメント)"
+
+#: ../../architecture.rst:22
+msgid "**Instruction set**: 67 instructions compliant with AVR DS40002198A"
+msgstr "**命令セット**: AVR DS40002198A準拠の67命令"
+
+#: ../../architecture.rst:23
+msgid "**Status register**: 8 flags (SREG: I, T, H, S, V, N, Z, C)"
+msgstr "**ステータスレジスタ**: 8個の条件フラグ (SREG: I, T, H, S, V, N, Z, C)"
+
+#: ../../architecture.rst:26
+msgid "Register Architecture"
+msgstr "レジスタアーキテクチャ"
+
+#: ../../architecture.rst:28
+msgid ""
+"In strict alignment with the **Microchip AVR® Instruction Set Manual "
+"(DS40002198A, Section 4)**, the CPU register file consists of 32 8-bit "
+"general-purpose working registers, labeled **R0** through **R31**. All 32"
+" registers have direct, single-cycle access to the Arithmetic Logic Unit "
+"(ALU)."
+msgstr ""
+"**Microchip AVR® Instruction Set Manual (DS40002198A, 第4章)** "
+"に厳密に準拠し、CPUのレジスタファイルは **R0** から **R31** "
+"までの32本の8ビット汎用作業レジスタで構成されます。全32本のレジスタが算術論理演算装置 (ALU) へ直接アクセス可能です。"
+
+#: ../../architecture.rst:45
+msgid "Register Organization & Special Functions"
+msgstr ""
+
+#: ../../architecture.rst:47
+msgid ""
+"**General Working Registers (R0–R15)**: Operate with all two-register "
+"arithmetic, logical, and bit operations (e.g., ``ADD``, ``SUB``, ``AND``,"
+" ``OR``, ``EOR``, ``MOV``, ``CP``)."
+msgstr ""
+
+#: ../../architecture.rst:49
+msgid ""
+"**Upper Registers (R16–R31)**: Support direct immediate instructions "
+"(``LDI``, ``SUBI``, ``SBCI``, ``ANDI``, ``ORI``, ``CPI``) where an 8-bit "
+"constant :math:`K` is supplied in the instruction."
+msgstr ""
+
+#: ../../architecture.rst:51
+msgid ""
+"**16-bit Word Operand Pairs (R25:R24, X, Y, Z)**: The word operations "
+"``ADIW`` (Add Immediate to Word) and ``SBIW`` (Subtract Immediate from "
+"Word) operate exclusively on the upper register pairs: * ``R25:R24`` * "
+"``R27:R26`` (X-register) * ``R29:R28`` (Y-register) * ``R31:R30`` "
+"(Z-register)"
+msgstr ""
+
+#: ../../architecture.rst:57
+msgid ""
+"**16-bit Pointer Registers (X, Y, Z)**: Six registers (R26–R31) serve as "
+"three 16-bit indirect address pointers for Data Space memory addressing: "
+"* **X-register**: ``XL = R26`` (low byte), ``XH = R27`` (high byte) * "
+"**Y-register**: ``YL = R28`` (low byte), ``YH = R29`` (high byte) * "
+"**Z-register**: ``ZL = R30`` (low byte), ``ZH = R31`` (high byte)"
+msgstr ""
+
+#: ../../architecture.rst:64
+msgid "Special Registers"
+msgstr "特殊レジスタ"
+
+#: ../../architecture.rst:67
+msgid "Program Counter (PC)"
+msgstr "プログラムカウンタ (PC)"
+
+#: ../../architecture.rst:69
+msgid "16-bit program address pointer referencing instructions in program memory."
+msgstr "プログラムメモリ上の命令を参照する16ビットのアドレスポインタです。"
+
+#: ../../architecture.rst:70
+msgid "Automatically increments during sequential execution."
+msgstr "通常の逐次実行中は自動的にインクリメントされます。"
+
+#: ../../architecture.rst:71
+msgid ""
+"Modified by jump (``JMP``, ``RJMP``), subroutine call/return (``CALL``, "
+"``RCALL``, ``RET``, ``RETI``), skip instructions (``CPSE``, ``SBRS``, "
+"``SBRC``, ``SBIS``, ``SBIC``), and conditional branches (``BRxx``)."
+msgstr ""
+"ジャンプ命令 (``JMP``, ``RJMP``)、サブルーチン呼び出し/復帰 (``CALL``, ``RCALL``, ``RET``, "
+"``RETI``)、スキップ命令 (``CPSE``, ``SBRS``, ``SBRC``, ``SBIS``, "
+"``SBIC``)、および条件分岐命令 (``BRxx``) によって更新されます。"
+
+#: ../../architecture.rst:74
+msgid "Stack Pointer (SP)"
+msgstr "スタックポインタ (SP)"
+
+#: ../../architecture.rst:76
+msgid ""
+"16-bit stack pointer pointing to the current top of the stack in Data "
+"SRAM."
+msgstr "データSRAM内の現在のスタックトップを指す16ビットのポインタです。"
+
+#: ../../architecture.rst:77
+msgid "Initialized to the end of RAM (default: ``0xFFFF`` with 64KB RAM)."
+msgstr "RAMの末尾アドレスに初期化されます (64KB RAMの場合、デフォルトは ``0xFFFF``)。"
+
+#: ../../architecture.rst:78
+msgid "Decrements during ``PUSH``, ``CALL``, and ``RCALL`` (post-decrement)."
+msgstr "``PUSH``, ``CALL``, ``RCALL`` の実行時にデクリメントされます (後置デクリメント)。"
+
+#: ../../architecture.rst:79
+msgid "Increments during ``POP``, ``RET``, and ``RETI`` (pre-increment)."
+msgstr "``POP``, ``RET``, ``RETI`` の実行時にインクリメントされます (前置インクリメント)。"
+
+#: ../../architecture.rst:82
+msgid "Status Register (SREG)"
+msgstr "ステータスレジスタ (SREG)"
+
+#: ../../architecture.rst:84
+msgid ""
+"8-bit condition flag register containing flags: ``I``, ``T``, ``H``, "
+"``S``, ``V``, ``N``, ``Z``, ``C``."
+msgstr ""
+"条件フラグ ``I``, ``T``, ``H``, ``S``, ``V``, ``N``, ``Z``, ``C`` "
+"を格納する8ビットレジスタです。"
+
+#: ../../architecture.rst:85
+msgid ""
+"Updated by arithmetic, logical, and shift operations according to exact "
+"Boolean algebra defined in DS40002198A."
+msgstr "DS40002198Aで定義された厳密なブール代数に基づき、算術演算、論理演算、シフト演算によって更新されます。"
+
+#: ../../architecture.rst:93
+msgid "Memory Model & Addressing Modes"
+msgstr "メモリモデルとアドレッシングモード"
+
+#: ../../architecture.rst:96
+msgid "Data Memory Space"
+msgstr ""
+
+#: ../../architecture.rst:98
+msgid ""
+"Tiny8 provides a flat, byte-addressable memory space modeled after AVR "
+"SRAM with configurable capacity (default: 65536 bytes / 64KB, addressable"
+" range ``0x0000`` to ``0xFFFF``)."
+msgstr ""
+"Tiny8は、設定可能な容量を持つAVR SRAMをモデルにしたフラットなバイト単位のアドレス空間を提供します (デフォルト: 65,536バイト"
+" / 64KB、アドレス可能範囲 ``0x0000`` から ``0xFFFF``)。"
+
+#: ../../architecture.rst:117
+msgid "AVR Addressing Modes"
+msgstr ""
+
+#: ../../architecture.rst:119
+msgid ""
+"Tiny8 strictly adheres to the standard AVR addressing modes specified in "
+"DS40002198A:"
+msgstr ""
+
+#: ../../architecture.rst:121
+msgid ""
+"**Direct Single Register**: Operates on a single working register "
+":math:`Rd` (e.g. ``INC Rd``, ``DEC Rd``, ``NEG Rd``, ``COM Rd``, ``CLR "
+"Rd``, ``SER Rd``, ``SWAP Rd``, ``LSL Rd``, ``LSR Rd``)."
+msgstr ""
+
+#: ../../architecture.rst:122
+msgid ""
+"**Direct Two-Register**: Operates on two working registers :math:`Rd` and"
+" :math:`Rr` (e.g. ``ADD Rd, Rr``, ``ADC Rd, Rr``, ``SUB Rd, Rr``, ``SBC "
+"Rd, Rr``, ``AND Rd, Rr``, ``OR Rd, Rr``, ``EOR Rd, Rr``, ``CP Rd, Rr``, "
+"``MOV Rd, Rr``)."
+msgstr ""
+
+#: ../../architecture.rst:123
+msgid ""
+"**Immediate Addressing**: An 8-bit constant :math:`K` operates on an "
+"upper register :math:`R16 \\le Rd \\le R31` (e.g. ``LDI Rd, K``, ``SUBI "
+"Rd, K``, ``SBCI Rd, K``, ``ANDI Rd, K``, ``ORI Rd, K``, ``CPI Rd, K``)."
+msgstr ""
+
+#: ../../architecture.rst:124
+msgid ""
+"**Word Immediate Addressing**: A 6-bit constant :math:`0 \\le K \\le 63` "
+"operates on register pairs :math:`R25:R24`, :math:`X`, :math:`Y`, or "
+":math:`Z` (e.g. ``ADIW Rd, K``, ``SBIW Rd, K``)."
+msgstr ""
+
+#: ../../architecture.rst:125
+msgid ""
+"**Direct Data Addressing**: 16-bit absolute memory address :math:`k` "
+"loads or stores directly to Data Space (e.g. ``LDS Rd, k``, ``STS k, "
+"Rr``)."
+msgstr ""
+
+#: ../../architecture.rst:126
+msgid ""
+"**Data Indirect Addressing with Pointer Registers (X, Y, Z)**: Accesses "
+"Data Space through 16-bit register pointers :math:`X` (R27:R26), "
+":math:`Y` (R29:R28), or :math:`Z` (R31:R30) (e.g. ``LD Rd, X``, ``ST X, "
+"Rr``)."
+msgstr ""
+
+#: ../../architecture.rst:127
+msgid ""
+"**I/O Direct Addressing**: Reads or writes to 6-bit I/O addresses "
+":math:`0 \\le P \\le 63` (e.g. ``IN Rd, P``, ``OUT P, Rr``, ``SBI P, b``,"
+" ``CBI P, b``, ``SBIS P, b``, ``SBIC P, b``)."
+msgstr ""
+
+#: ../../architecture.rst:128
+msgid ""
+"**Relative Program Addressing**: Jumps or branches relative to the "
+"current Program Counter within range :math:`PC + k + 1` (e.g. ``RJMP k``,"
+" ``RCALL k``, ``BREQ k``, ``BRNE k``, ``BRCS k``, ``BRCC k``, ``BRLO k``,"
+" ``BRSH k``, ``BRGE k``, ``BRLT k``, ``BRMI k``, ``BRPL k``)."
+msgstr ""
+
+#: ../../architecture.rst:129
+msgid ""
+"**Direct Program Addressing**: Unconditional jump or long subroutine call"
+" directly to 16-bit program address :math:`k` (e.g. ``JMP k``, ``CALL "
+"k``)."
+msgstr ""
+
+#: ../../architecture.rst:130
+msgid ""
+"**Indirect Program Addressing**: Return from subroutine or interrupt "
+"through return address popped from the stack (e.g. ``RET``, ``RETI``)."
+msgstr ""
+
+#: ../../architecture.rst:133
+msgid "Memory Access Examples"
+msgstr ""
+
+#: ../../architecture.rst:155
+msgid "All memory is initialized to 0 on CPU creation"
+msgstr ""
+
+#: ../../architecture.rst:156
+msgid "The assembler loads program instructions starting at address 0"
+msgstr ""
+
+#: ../../architecture.rst:157
+msgid "Stack pointer is initialized to the top of memory"
+msgstr ""
+
+#: ../../architecture.rst:160
+msgid "Status Flags"
+msgstr ""
+
+#: ../../architecture.rst:162
+msgid ""
+"The Status Register (SREG) contains 8 condition flags that reflect the "
+"result of operations and control program flow. In accordance with the "
+"**Microchip AVR® Instruction Set Manual (DS40002198A)**, each flag is "
+"defined and updated according to exact Boolean algebraic formulas."
+msgstr ""
+
+#: ../../architecture.rst:165
+msgid "Flag Descriptions & Boolean Formulas"
+msgstr ""
+
+#: ../../architecture.rst:171
+msgid "Bit"
+msgstr ""
+
+#: ../../architecture.rst:172
+msgid "Flag"
+msgstr ""
+
+#: ../../architecture.rst:173
+msgid "Name"
+msgstr ""
+
+#: ../../architecture.rst:174
+msgid "DS40002198A Definition & Formula"
+msgstr ""
+
+#: ../../architecture.rst:175
+msgid "7"
+msgstr ""
+
+#: ../../architecture.rst:176
+msgid "**I**"
+msgstr ""
+
+#: ../../architecture.rst:177
+msgid "Global Interrupt"
+msgstr ""
+
+#: ../../architecture.rst:178
+msgid "Set by ``SEI``, cleared by ``CLI`` or hardware interrupt entry."
+msgstr ""
+
+#: ../../architecture.rst:179
+msgid "6"
+msgstr ""
+
+#: ../../architecture.rst:180
+msgid "**T**"
+msgstr ""
+
+#: ../../architecture.rst:181
+msgid "Bit Copy Storage"
+msgstr ""
+
+#: ../../architecture.rst:182
+msgid "Transferred between SREG and register bit locations by ``BST`` / ``BLD``."
+msgstr ""
+
+#: ../../architecture.rst:183
+msgid "5"
+msgstr ""
+
+#: ../../architecture.rst:184
+msgid "**H**"
+msgstr ""
+
+#: ../../architecture.rst:185
+msgid "Half Carry"
+msgstr ""
+
+#: ../../architecture.rst:186
+#, python-brace-format
+msgid ""
+"Indicates carry/borrow across nibble boundary (bit 3 to bit 4). ADD: "
+":math:`Rd3 \\cdot Rr3 + Rr3 \\cdot \\overline{R3} + \\overline{R3} \\cdot"
+" Rd3`. SUB: :math:`\\overline{Rd3} \\cdot Rr3 + Rr3 \\cdot R3 + R3 \\cdot"
+" \\overline{Rd3}`."
+msgstr ""
+
+#: ../../architecture.rst:187
+msgid "4"
+msgstr ""
+
+#: ../../architecture.rst:188
+msgid "**S**"
+msgstr ""
+
+#: ../../architecture.rst:189
+msgid "Sign Bit"
+msgstr ""
+
+#: ../../architecture.rst:190
+msgid ""
+"True algebraic sign test considering two's complement overflow: :math:`S "
+"= N \\oplus V`."
+msgstr ""
+
+#: ../../architecture.rst:191
+msgid "3"
+msgstr ""
+
+#: ../../architecture.rst:192
+msgid "**V**"
+msgstr ""
+
+#: ../../architecture.rst:193
+msgid "Overflow"
+msgstr ""
+
+#: ../../architecture.rst:194
+#, python-brace-format
+msgid ""
+"Two's complement signed overflow flag. ADD: :math:`Rd7 \\cdot Rr7 \\cdot "
+"\\overline{R7} + \\overline{Rd7} \\cdot \\overline{Rr7} \\cdot R7`. SUB: "
+":math:`Rd7 \\cdot \\overline{Rr7} \\cdot \\overline{R7} + \\overline{Rd7}"
+" \\cdot Rr7 \\cdot R7`."
+msgstr ""
+
+#: ../../architecture.rst:195
+msgid "2"
+msgstr ""
+
+#: ../../architecture.rst:196
+msgid "**N**"
+msgstr ""
+
+#: ../../architecture.rst:197
+msgid "Negative"
+msgstr ""
+
+#: ../../architecture.rst:198
+msgid ""
+"Set if the most significant bit (MSB, bit 7) of the result is 1: :math:`N"
+" = R7`."
+msgstr ""
+
+#: ../../architecture.rst:199
+msgid "1"
+msgstr ""
+
+#: ../../architecture.rst:200
+msgid "**Z**"
+msgstr ""
+
+#: ../../architecture.rst:201
+msgid "Zero"
+msgstr ""
+
+#: ../../architecture.rst:202
+#, python-brace-format
+msgid ""
+"Set if the result equals zero: :math:`Z = \\overline{R7} \\cdot "
+"\\overline{R6} \\cdot \\overline{R5} \\cdot \\overline{R4} \\cdot "
+"\\overline{R3} \\cdot \\overline{R2} \\cdot \\overline{R1} \\cdot "
+"\\overline{R0}`."
+msgstr ""
+
+#: ../../architecture.rst:203
+msgid "0"
+msgstr ""
+
+#: ../../architecture.rst:204
+msgid "**C**"
+msgstr ""
+
+#: ../../architecture.rst:205
+msgid "Carry / Borrow"
+msgstr ""
+
+#: ../../architecture.rst:206
+#, python-brace-format
+msgid ""
+"Unsigned carry out of bit 7 or borrow. ADD: :math:`Rd7 \\cdot Rr7 + Rr7 "
+"\\cdot \\overline{R7} + \\overline{R7} \\cdot Rd7`. SUB: "
+":math:`\\overline{Rd7} \\cdot Rr7 + Rr7 \\cdot R7 + R7 \\cdot "
+"\\overline{Rd7}`."
+msgstr ""
+
+#: ../../architecture.rst:209
+msgid "Flag Updates by Instruction Category"
+msgstr ""
+
+#: ../../architecture.rst:211
+msgid "According to AVR Instruction Set Manual DS40002198A:"
+msgstr ""
+
+#: ../../architecture.rst:213
+msgid "**Arithmetic (ADD, ADC, SUB, SUBI, SBC, SBCI)**"
+msgstr ""
+
+#: ../../architecture.rst:214
+msgid "Updates all condition flags: ``H``, ``S``, ``V``, ``N``, ``Z``, ``C``."
+msgstr ""
+
+#: ../../architecture.rst:216
+msgid "**Comparisons (CP, CPI)**"
+msgstr ""
+
+#: ../../architecture.rst:217
+msgid ""
+"Identical flag updates to subtraction (``SUB`` / ``SUBI``), but the "
+"register value is discarded."
+msgstr ""
+
+#: ../../architecture.rst:219
+msgid "**Bitwise Logical (AND, ANDI, OR, ORI, EOR, TST)**"
+msgstr ""
+
+#: ../../architecture.rst:220
+msgid ""
+"Updates ``S``, ``V=0`` (cleared), ``N``, ``Z``. Carry ``C`` and Half-"
+"Carry ``H`` are **unaffected** (``-``). ``TST Rd`` is an alias for ``AND "
+"Rd, Rd``."
+msgstr ""
+
+#: ../../architecture.rst:222
+msgid "**Register Clearing & Setting (CLR, SER)**"
+msgstr ""
+
+#: ../../architecture.rst:223
+msgid ""
+"``CLR Rd`` is an alias for ``EOR Rd, Rd``: sets ``Z=1``, ``S=0``, "
+"``V=0``, ``N=0``; leaves ``C`` and ``H`` unaffected."
+msgstr ""
+
+#: ../../architecture.rst:224
+msgid "``SER Rd`` is an alias for ``LDI Rd, $FF``: **no flags affected**."
+msgstr ""
+
+#: ../../architecture.rst:226
+msgid "**Single-Operand Arithmetic (INC, DEC, NEG, COM)**"
+msgstr ""
+
+#: ../../architecture.rst:227
+msgid ""
+"``INC`` / ``DEC``: Update ``S``, ``V``, ``N``, ``Z``. Carry ``C`` is "
+"**unaffected** (allows loop counters without clobbering carry)."
+msgstr ""
+
+#: ../../architecture.rst:228
+msgid ""
+"``NEG``: Two's complement negation (:math:`R = 0 - Rd`). Updates ``H``, "
+"``S``, ``V``, ``N``, ``Z``, ``C``. (:math:`C = (R \\neq 0)`, :math:`V = "
+"(Rd = \\$80)`)."
+msgstr ""
+
+#: ../../architecture.rst:229
+msgid ""
+"``COM``: One's complement inversion (:math:`R = \\$FF - Rd`). Updates "
+"``S``, ``V=0``, ``N``, ``Z``, and forces ``C=1``."
+msgstr ""
+
+#: ../../architecture.rst:231
+msgid "**Shifts & Rotates (LSL, LSR, ROL, ROR, SWAP)**"
+msgstr ""
+
+#: ../../architecture.rst:232
+msgid "``LSL Rd``: Alias for ``ADD Rd, Rd``."
+msgstr ""
+
+#: ../../architecture.rst:233
+msgid "``ROL Rd``: Alias for ``ADC Rd, Rd``."
+msgstr ""
+
+#: ../../architecture.rst:234
+msgid ""
+"``LSR Rd``: Logical shift right. Sets :math:`C = Rd0`, :math:`N = 0`, "
+":math:`Z = (R = 0)`, :math:`V = N \\oplus C = C`, :math:`S = N \\oplus V "
+"= C`."
+msgstr ""
+
+#: ../../architecture.rst:235
+msgid ""
+"``ROR Rd``: Rotate right through carry. Sets :math:`C = Rd0`, :math:`N = "
+"R7`, :math:`Z = (R = 0)`, :math:`V = N \\oplus C`, :math:`S = N \\oplus "
+"V`."
+msgstr ""
+
+#: ../../architecture.rst:236
+msgid "``SWAP Rd``: Swaps nibbles. **No flags affected**."
+msgstr ""
+
+#: ../../architecture.rst:238
+msgid "**Word Operations (ADIW, SBIW)**"
+msgstr ""
+
+#: ../../architecture.rst:239
+msgid ""
+"16-bit word addition / subtraction on pointer register pairs (R25:R24, "
+"R27:R26, R29:R28, R31:R30). Updates ``S``, ``V``, ``N``, ``Z``, ``C``."
+msgstr ""
+
+#: ../../architecture.rst:241
+msgid ""
+"**Data Transfer & Branches (LDI, MOV, LD, ST, LDS, STS, PUSH, POP, IN, "
+"OUT, JMP, RJMP, CALL, RCALL, RET, BRxx)**"
+msgstr ""
+
+#: ../../architecture.rst:242
+msgid ""
+"Do not affect status flags, except ``RETI`` which sets the Global "
+"Interrupt Flag ``I = 1``."
+msgstr ""
+
+#: ../../architecture.rst:245
+msgid "Using Flags for Branches"
+msgstr ""
+
+#: ../../architecture.rst:247
+msgid ""
+"Conditional branch instructions inspect specific SREG condition flags "
+"(all branches take target label or relative offset without altering "
+"flags):"
+msgstr ""
+
+#: ../../architecture.rst:253
+msgid "Mnemonic"
+msgstr ""
+
+#: ../../architecture.rst:254
+msgid "Condition"
+msgstr ""
+
+#: ../../architecture.rst:255
+msgid "Description (per DS40002198A)"
+msgstr ""
+
+#: ../../architecture.rst:256
+msgid "``BREQ label``"
+msgstr ""
+
+#: ../../architecture.rst:257
+msgid ":math:`Z = 1`"
+msgstr ""
+
+#: ../../architecture.rst:258
+msgid "Branch if Equal"
+msgstr ""
+
+#: ../../architecture.rst:259
+msgid "``BRNE label``"
+msgstr ""
+
+#: ../../architecture.rst:260
+msgid ":math:`Z = 0`"
+msgstr ""
+
+#: ../../architecture.rst:261
+msgid "Branch if Not Equal"
+msgstr ""
+
+#: ../../architecture.rst:262
+msgid "``BRCS label``"
+msgstr ""
+
+#: ../../architecture.rst:263 ../../architecture.rst:269
+msgid ":math:`C = 1`"
+msgstr ""
+
+#: ../../architecture.rst:264
+msgid "Branch if Carry Set"
+msgstr ""
+
+#: ../../architecture.rst:265
+msgid "``BRCC label``"
+msgstr ""
+
+#: ../../architecture.rst:266 ../../architecture.rst:272
+msgid ":math:`C = 0`"
+msgstr ""
+
+#: ../../architecture.rst:267
+msgid "Branch if Carry Clear"
+msgstr ""
+
+#: ../../architecture.rst:268
+msgid "``BRLO label``"
+msgstr ""
+
+#: ../../architecture.rst:270
+msgid "Branch if Lower (Unsigned, alias for ``BRCS``)"
+msgstr ""
+
+#: ../../architecture.rst:271
+msgid "``BRSH label``"
+msgstr ""
+
+#: ../../architecture.rst:273
+msgid "Branch if Same or Higher (Unsigned, alias for ``BRCC``)"
+msgstr ""
+
+#: ../../architecture.rst:274
+msgid "``BRGE label``"
+msgstr ""
+
+#: ../../architecture.rst:275
+msgid ":math:`S = 0` (:math:`N \\oplus V = 0`)"
+msgstr ""
+
+#: ../../architecture.rst:276
+msgid "Branch if Greater or Equal (Signed)"
+msgstr ""
+
+#: ../../architecture.rst:277
+msgid "``BRLT label``"
+msgstr ""
+
+#: ../../architecture.rst:278
+msgid ":math:`S = 1` (:math:`N \\oplus V = 1`)"
+msgstr ""
+
+#: ../../architecture.rst:279
+msgid "Branch if Less Than (Signed)"
+msgstr ""
+
+#: ../../architecture.rst:280
+msgid "``BRMI label``"
+msgstr ""
+
+#: ../../architecture.rst:281
+msgid ":math:`N = 1`"
+msgstr ""
+
+#: ../../architecture.rst:282
+msgid "Branch if Minus"
+msgstr ""
+
+#: ../../architecture.rst:283
+msgid "``BRPL label``"
+msgstr ""
+
+#: ../../architecture.rst:284
+msgid ":math:`N = 0`"
+msgstr ""
+
+#: ../../architecture.rst:285
+msgid "Branch if Plus"
+msgstr ""
+
+#: ../../architecture.rst:288
+msgid "Instruction Execution & ALU"
+msgstr ""
+
+#: ../../architecture.rst:291
+msgid "ALU Operation & Register Access"
+msgstr ""
+
+#: ../../architecture.rst:293
+msgid ""
+"In strict compliance with the **AVR® Instruction Set Manual (DS40002198A,"
+" Section 4)**, the high-performance AVR Arithmetic Logic Unit (ALU) "
+"operates in direct connection with all 32 general-purpose registers:"
+msgstr ""
+
+#: ../../architecture.rst:295
+msgid ""
+"**Single-Cycle Operation**: Arithmetic and logical register-to-register "
+"operations execute within a single instruction transition. In this cycle:"
+" 1. Two operand registers are read from the Register File. 2. The "
+"operation (Arithmetic, Logical, or Bit manipulation) is evaluated. 3. The"
+" result is written back to the destination register :math:`Rd`. 4. The "
+"Status Register (SREG) condition flags are updated according to exact "
+"Boolean algebraic formulas."
+msgstr ""
+
+#: ../../architecture.rst:300
+msgid ""
+"**ALU Functional Blocks**: * **Arithmetic**: Addition (``ADD``, ``ADC``, "
+"``ADIW``), Subtraction (``SUB``, ``SUBI``, ``SBC``, ``SBCI``, ``SBIW``), "
+"Comparison (``CP``, ``CPI``), Negation (``NEG``), Increment (``INC``), "
+"Decrement (``DEC``), and Multiplication (``MUL``, ``MULS``, ``MULSU``). *"
+" **Logical**: Bitwise AND (``AND``, ``ANDI``, ``TST``), OR (``OR``, "
+"``ORI``), Exclusive-OR (``EOR``, ``CLR``), and One's Complement "
+"(``COM``). * **Bit & Shift Functions**: Bit set/clear (``SBI``, ``CBI``),"
+" Shifts (``LSL``, ``LSR``, ``ASR``), Rotates through carry (``ROL``, "
+"``ROR``), and Nibble swap (``SWAP``)."
+msgstr ""
+
+#: ../../architecture.rst:306
+msgid "Fetch-Decode-Execute Cycle"
+msgstr ""
+
+#: ../../architecture.rst:308
+msgid "Tiny8 executes programs through the classical CPU cycle:"
+msgstr ""
+
+#: ../../architecture.rst:321
+msgid "Instruction Format & Encoding"
+msgstr ""
+
+#: ../../architecture.rst:323
+msgid ""
+"In physical AVR microcontrollers: * Most instructions are **16-bit "
+"(1-word)** opcodes. * Direct memory instructions (``LDS``, ``STS``) and "
+"long jumps/calls (``JMP``, ``CALL``) are **32-bit (2-word)** opcodes."
+msgstr ""
+
+#: ../../architecture.rst:327
+msgid ""
+"In Tiny8, the assembler validates operands according to AVR DS40002198A "
+"constraints (e.g., verifying that ``LDI``, ``SUBI``, ``CPI`` only target "
+"upper registers R16–R31, and that ``ADIW`` / ``SBIW`` target valid "
+"pointer register pairs), then stores them as pre-decoded execution "
+"tuples:"
+msgstr ""
+
+#: ../../architecture.rst:340
+msgid "Step Tracing & State Inspection"
+msgstr ""
+
+#: ../../architecture.rst:342
+msgid ""
+"During each execution step, Tiny8 records changes to facilitate visual "
+"debugging:"
+msgstr ""
+
+#: ../../architecture.rst:344
+msgid ""
+"**Register Trace**: Tracks register writes as ``(step, register_index, "
+"new_value)``."
+msgstr ""
+
+#: ../../architecture.rst:345
+msgid "**Memory Trace**: Tracks SRAM writes as ``(step, address, new_value)``."
+msgstr ""
+
+#: ../../architecture.rst:346
+msgid ""
+"**Step Telemetry**: Records PC, SREG flags, cycle counts, and call stack "
+"backtraces."
+msgstr ""
+
+#: ../../architecture.rst:349
+msgid "Hardware Realism & AVR Compliance"
+msgstr ""
+
+#: ../../architecture.rst:351
+msgid ""
+"Tiny8 is strictly grounded in the **Microchip AVR® Instruction Set Manual"
+" (DS40002198A)**:"
+msgstr ""
+
+#: ../../architecture.rst:353
+msgid ""
+"**Instruction Set Fidelity**: All 61 supported instructions strictly "
+"follow official Microchip AVR definitions, operands, and SREG Boolean "
+"formulas without non-standard instruction extensions."
+msgstr ""
+
+#: ../../architecture.rst:354
+msgid ""
+"**Hardware MUL Compliance**: In accordance with AVR DS40002198A, ``MUL "
+"Rd, Rr`` writes the 16-bit unsigned product strictly into the dedicated "
+"register pair ``R1:R0`` (R0 = low byte, R1 = high byte)."
+msgstr ""
+
+#: ../../architecture.rst:355
+msgid ""
+"**Software Division**: Conforming to physical AVR silicon, integer "
+"division is performed via standard software routines (e.g., subtraction "
+"loops or shift-and-subtract) rather than non-standard hardware "
+"instructions."
+msgstr ""
+
+#: ../../architecture.rst:356
+msgid ""
+"**Execution & Memory Model**: Instructions execute in discrete single-"
+"step transitions across a unified flat address space with memory-mapped "
+"I/O (ports 0x00..0x3F including CRT matrix and keyboard buffer) for full "
+"visibility and educational inspectability."
+msgstr ""
+
+#: ../../architecture.rst:359
+msgid "Design Philosophy"
+msgstr ""
+
+#: ../../architecture.rst:361
+msgid "Tiny8's architecture is designed with these principles:"
+msgstr ""
+
+#: ../../architecture.rst:363
+msgid "**Simplicity**: Easy to understand and implement"
+msgstr ""
+
+#: ../../architecture.rst:364
+msgid "**Educational value**: Teaches fundamental concepts"
+msgstr ""
+
+#: ../../architecture.rst:365
+msgid "**Inspectability**: Full visibility into CPU state"
+msgstr ""
+
+#: ../../architecture.rst:366
+msgid "**Extensibility**: Easy to add new instructions"
+msgstr ""
+
+#: ../../architecture.rst:367
+msgid "**Practicality**: Can run real algorithms and demonstrate CS concepts"
+msgstr ""
+
+#: ../../architecture.rst:369
+msgid ""
+"The architecture strikes a balance between realism (standard AVR "
+"architecture) and pedagogy (simplified execution model), making it "
+"suitable for:"
+msgstr "このアーキテクチャは、現実性（標準AVRアーキテクチャ）と教育的配慮（簡素化された実行モデル）のバランスを取っており、以下のような用途に適しています:"
+
+#: ../../architecture.rst:371
+msgid "Computer architecture courses"
+msgstr "コンピュータアーキテクチャの講義"
+
+#: ../../architecture.rst:372
+msgid "Assembly language learning"
+msgstr "アセンブリ言語の学習"
+
+#: ../../architecture.rst:373
+msgid "Algorithm visualization"
+msgstr "アルゴリズムの可視化"
+
+#: ../../architecture.rst:374
+msgid "Embedded systems concepts"
+msgstr "組み込みシステムの概念学習"
+
+#: ../../architecture.rst:375
+msgid "Compiler/assembler development"
+msgstr "コンパイラ・アセンブラの開発"
+
+#~ msgid ""
+#~ "**Supplementary Reference**: `Wikipedia: Atmel "
+#~ "AVR instruction set "
+#~ "<https://en.wikipedia.org/wiki/Atmel_AVR_instruction_set>`_"
+#~ msgstr ""
+#~ "**補足参考資料**: `Wikipedia: Atmel AVR instruction"
+#~ " set "
+#~ "<https://en.wikipedia.org/wiki/Atmel_AVR_instruction_set>`_"
+
+#~ msgid ""
+#~ "The architecture strikes a balance "
+#~ "between realism (AVR-inspired) and "
+#~ "pedagogy (simplified execution model), making"
+#~ " it suitable for:"
+#~ msgstr ""
+
+#~ msgid ""
+#~ "Tiny8 provides a flat, byte-addressable"
+#~ " memory space modeled after AVR SRAM"
+#~ " with configurable capacity (default: 4096"
+#~ " bytes / 4KB, addressable range "
+#~ "``0x0000`` to ``0x0FFF``)."
+#~ msgstr ""
+
+#~ msgid ""
+#~ "**Upper Registers (R16–R31)**: Support direct"
+#~ " immediate instructions (``LDI``, ``SUBI``, "
+#~ "``SBCI``, ``ANDI``, ``ORI``, ``EORI``, "
+#~ "``CPI``) where an 8-bit constant "
+#~ ":math:`K` is supplied in the "
+#~ "instruction."
+#~ msgstr ""
+
+#~ msgid ""
+#~ "**Immediate Addressing**: An 8-bit constant"
+#~ " :math:`K` operates on an upper "
+#~ "register :math:`R16 \\le Rd \\le R31`"
+#~ " (e.g. ``LDI Rd, K``, ``SUBI Rd, "
+#~ "K``, ``SBCI Rd, K``, ``ANDI Rd, "
+#~ "K``, ``ORI Rd, K``, ``EORI Rd, "
+#~ "K``, ``CPI Rd, K``)."
+#~ msgstr ""
+
+#~ msgid "**Bitwise Logical (AND, ANDI, OR, ORI, EOR, EORI, TST)**"
+#~ msgstr ""
+
+#~ msgid ""
+#~ "**ALU Functional Blocks**: * **Arithmetic**:"
+#~ " Addition (``ADD``, ``ADC``, ``ADIW``), "
+#~ "Subtraction (``SUB``, ``SUBI``, ``SBC``, "
+#~ "``SBCI``, ``SBIW``), Comparison (``CP``, "
+#~ "``CPI``), Negation (``NEG``), Increment "
+#~ "(``INC``), Decrement (``DEC``), and "
+#~ "Multiplication (``MUL``). * **Logical**: "
+#~ "Bitwise AND (``AND``, ``ANDI``, ``TST``), "
+#~ "OR (``OR``, ``ORI``), Exclusive-OR "
+#~ "(``EOR``, ``EORI``, ``CLR``), and One's "
+#~ "Complement (``COM``). * **Bit & Shift"
+#~ " Functions**: Bit set/clear (``SBI``, "
+#~ "``CBI``), Shifts (``LSL``, ``LSR``), Rotates"
+#~ " through carry (``ROL``, ``ROR``), and "
+#~ "Nibble swap (``SWAP``)."
+#~ msgstr ""
+
diff --git a/docs/locales/ja/LC_MESSAGES/assembly_language.po b/docs/locales/ja/LC_MESSAGES/assembly_language.po
new file mode 100644
index 0000000..8d1decc
--- /dev/null
+++ b/docs/locales/ja/LC_MESSAGES/assembly_language.po
@@ -0,0 +1,1443 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, 2026.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-25 01:27+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language: ja\n"
+"Language-Team: ja <LL@li.org>\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=utf-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Generated-By: Babel 2.17.0\n"
+
+#: ../../assembly_language.rst:2
+msgid "Assembly Language"
+msgstr "アセンブリ言語"
+
+#: ../../assembly_language.rst:4
+msgid ""
+"This guide covers the Tiny8 assembly language syntax, including "
+"instruction format, operand types, labels, and assembler directives."
+msgstr "本ガイドでは、命令フォーマット、オペランドの種類、ラベル、アセンブラ構文など、Tiny8アセンブリ言語の構文体系について解説します。"
+
+#: ../../assembly_language.rst:7
+msgid "Syntax Overview"
+msgstr "構文の概要"
+
+#: ../../assembly_language.rst:10
+msgid "Basic Structure"
+msgstr "基本構造"
+
+#: ../../assembly_language.rst:12
+msgid "A Tiny8 assembly program consists of:"
+msgstr "Tiny8のアセンブリプログラムは以下の要素で構成されます:"
+
+#: ../../assembly_language.rst:14
+msgid "**Instructions**: CPU operations (e.g., ``add``, ``mov``, ``ldi``)"
+msgstr "**命令**: CPUの演算操作 (例: ``add``, ``mov``, ``ldi``)"
+
+#: ../../assembly_language.rst:15
+msgid "**Labels**: Named locations in the program"
+msgstr "**ラベル**: プログラム内の指定位置を示す識別子"
+
+#: ../../assembly_language.rst:16
+msgid "**Comments**: Documentation prefixed with ``;``"
+msgstr "**コメント**: ``;`` で始まる注釈記述"
+
+#: ../../assembly_language.rst:17
+msgid "**Blank lines**: For readability (ignored by assembler)"
+msgstr "**空行**: 可読性向上のための空白行 (アセンブラにより無視)"
+
+#: ../../assembly_language.rst:20
+msgid "Example Program"
+msgstr "プログラム例"
+
+#: ../../assembly_language.rst:42
+msgid "Comments"
+msgstr "コメント"
+
+#: ../../assembly_language.rst:45
+msgid "Single-Line Comments"
+msgstr "単一行コメント"
+
+#: ../../assembly_language.rst:47
+msgid "Comments start with a semicolon (``;``) and extend to the end of the line:"
+msgstr "コメントはセミコロン (``;``) で始まり、その行の末尾まで続きます:"
+
+#: ../../assembly_language.rst:55
+msgid ""
+"Comments are stripped during assembly and don't affect the generated "
+"program."
+msgstr "コメントはアセンブル時に除去され、生成される実行コードには影響しません。"
+
+#: ../../assembly_language.rst:58
+msgid "Whitespace"
+msgstr ""
+
+#: ../../assembly_language.rst:60
+msgid "Leading and trailing whitespace is ignored"
+msgstr ""
+
+#: ../../assembly_language.rst:61
+msgid "Multiple spaces between tokens are treated as single space"
+msgstr ""
+
+#: ../../assembly_language.rst:62
+msgid "Blank lines are allowed and ignored"
+msgstr ""
+
+#: ../../assembly_language.rst:65
+msgid "Labels"
+msgstr ""
+
+#: ../../assembly_language.rst:68
+msgid "Defining Labels"
+msgstr ""
+
+#: ../../assembly_language.rst:70
+msgid ""
+"Labels mark locations in your program and can be used as jump/branch "
+"targets:"
+msgstr ""
+
+#: ../../assembly_language.rst:81
+msgid "Label Rules"
+msgstr ""
+
+#: ../../assembly_language.rst:83
+msgid "Labels must end with a colon (``:``)"
+msgstr ""
+
+#: ../../assembly_language.rst:84
+msgid "Label names are case-sensitive"
+msgstr ""
+
+#: ../../assembly_language.rst:85
+msgid "Valid characters: letters, digits, underscore"
+msgstr ""
+
+#: ../../assembly_language.rst:86
+msgid "Cannot start with a digit"
+msgstr ""
+
+#: ../../assembly_language.rst:87
+msgid "Cannot be a reserved instruction mnemonic"
+msgstr ""
+
+#: ../../assembly_language.rst:89
+msgid "**Valid labels:**"
+msgstr ""
+
+#: ../../assembly_language.rst:98
+msgid "**Invalid labels:**"
+msgstr ""
+
+#: ../../assembly_language.rst:107
+msgid "Using Labels"
+msgstr ""
+
+#: ../../assembly_language.rst:109
+msgid "Labels are most commonly used with control flow instructions:"
+msgstr ""
+
+#: ../../assembly_language.rst:129
+msgid "Operand Types"
+msgstr ""
+
+#: ../../assembly_language.rst:132
+msgid "Registers"
+msgstr ""
+
+#: ../../assembly_language.rst:134
+msgid ""
+"Register operands are specified as ``r`` followed by the register number "
+"(0-31):"
+msgstr ""
+
+#: ../../assembly_language.rst:143
+msgid "Some instructions (like ``ldi``) only work with registers R16-R31."
+msgstr ""
+
+#: ../../assembly_language.rst:146
+msgid "Immediate Values"
+msgstr ""
+
+#: ../../assembly_language.rst:148
+msgid "Immediate values are constants embedded in the instruction:"
+msgstr ""
+
+#: ../../assembly_language.rst:150
+msgid "**Decimal** (default)"
+msgstr ""
+
+#: ../../assembly_language.rst:158
+msgid "**Hexadecimal** (prefix with ``0x`` or ``$``)"
+msgstr ""
+
+#: ../../assembly_language.rst:166
+msgid "**Binary** (prefix with ``0b``)"
+msgstr ""
+
+#: ../../assembly_language.rst:174
+msgid "**With Immediate Marker** (optional ``#`` prefix)"
+msgstr ""
+
+#: ../../assembly_language.rst:182
+msgid "Memory Addresses"
+msgstr ""
+
+#: ../../assembly_language.rst:184
+msgid "Memory addresses are used with load and store instructions:"
+msgstr ""
+
+#: ../../assembly_language.rst:193
+msgid "Label References"
+msgstr ""
+
+#: ../../assembly_language.rst:195
+msgid "Labels can be used as operands for jumps, branches, and calls:"
+msgstr ""
+
+#: ../../assembly_language.rst:214
+msgid "Instruction Format"
+msgstr ""
+
+#: ../../assembly_language.rst:217
+msgid "General Pattern"
+msgstr ""
+
+#: ../../assembly_language.rst:219
+msgid "Instructions follow this pattern:"
+msgstr ""
+
+#: ../../assembly_language.rst:225
+msgid "**label**: Optional label ending with ``:``"
+msgstr ""
+
+#: ../../assembly_language.rst:226
+msgid "**mnemonic**: Instruction name (e.g., ``add``, ``mov``, ``ldi``)"
+msgstr ""
+
+#: ../../assembly_language.rst:227
+msgid "**operands**: Zero or more operands separated by commas"
+msgstr ""
+
+#: ../../assembly_language.rst:230
+msgid "Operand Count"
+msgstr ""
+
+#: ../../assembly_language.rst:232
+msgid "Different instructions take different numbers of operands:"
+msgstr ""
+
+#: ../../assembly_language.rst:253
+msgid "Case Sensitivity"
+msgstr ""
+
+#: ../../assembly_language.rst:255
+msgid ""
+"**Instructions**: Case-insensitive (``ADD``, ``add``, ``Add`` are all "
+"valid)"
+msgstr ""
+
+#: ../../assembly_language.rst:256
+msgid "**Registers**: Case-insensitive (``r16``, ``R16`` are both valid)"
+msgstr ""
+
+#: ../../assembly_language.rst:257
+msgid "**Labels**: Case-sensitive (``Loop`` and ``loop`` are different)"
+msgstr ""
+
+#: ../../assembly_language.rst:272
+msgid "Program Structure"
+msgstr ""
+
+#: ../../assembly_language.rst:275
+msgid "Typical Program Layout"
+msgstr ""
+
+#: ../../assembly_language.rst:277
+msgid "Most Tiny8 programs follow this structure:"
+msgstr ""
+
+#: ../../assembly_language.rst:310
+msgid "Initialization"
+msgstr ""
+
+#: ../../assembly_language.rst:312
+msgid "Initialize registers and memory at the start of your program:"
+msgstr ""
+
+#: ../../assembly_language.rst:326
+msgid "Main Loop"
+msgstr ""
+
+#: ../../assembly_language.rst:328
+msgid "Most programs have a main execution loop:"
+msgstr ""
+
+#: ../../assembly_language.rst:346
+msgid "Program Termination"
+msgstr ""
+
+#: ../../assembly_language.rst:348
+msgid ""
+"Since Tiny8 doesn't have a \"halt\" instruction, programs typically end "
+"with an infinite loop:"
+msgstr ""
+
+#: ../../assembly_language.rst:361
+msgid "Assembler Behavior"
+msgstr ""
+
+#: ../../assembly_language.rst:364
+msgid "Two-Pass Assembly"
+msgstr ""
+
+#: ../../assembly_language.rst:366
+msgid "The assembler makes two passes through your code:"
+msgstr ""
+
+#: ../../assembly_language.rst:368
+msgid "**First pass**: Collect all labels and their addresses"
+msgstr ""
+
+#: ../../assembly_language.rst:369
+msgid "**Second pass**: Resolve label references and generate instructions"
+msgstr ""
+
+#: ../../assembly_language.rst:371
+msgid "This allows forward references:"
+msgstr ""
+
+#: ../../assembly_language.rst:383
+msgid "Number Parsing"
+msgstr ""
+
+#: ../../assembly_language.rst:385
+msgid "The assembler recognizes several number formats:"
+msgstr ""
+
+#: ../../assembly_language.rst:391
+msgid "Format"
+msgstr ""
+
+#: ../../assembly_language.rst:392
+msgid "Example"
+msgstr ""
+
+#: ../../assembly_language.rst:393
+msgid "Value"
+msgstr ""
+
+#: ../../assembly_language.rst:394
+msgid "Decimal"
+msgstr ""
+
+#: ../../assembly_language.rst:395
+msgid "``42``"
+msgstr ""
+
+#: ../../assembly_language.rst:396
+msgid "42"
+msgstr ""
+
+#: ../../assembly_language.rst:397
+msgid "Negative decimal"
+msgstr ""
+
+#: ../../assembly_language.rst:398
+msgid "``-10``"
+msgstr ""
+
+#: ../../assembly_language.rst:399
+msgid "-10 (stored as 246 in 8-bit)"
+msgstr ""
+
+#: ../../assembly_language.rst:400
+msgid "Hexadecimal (0x)"
+msgstr ""
+
+#: ../../assembly_language.rst:401
+msgid "``0xFF``"
+msgstr ""
+
+#: ../../assembly_language.rst:402 ../../assembly_language.rst:405
+#: ../../assembly_language.rst:408
+msgid "255"
+msgstr ""
+
+#: ../../assembly_language.rst:403
+msgid "Hexadecimal ($)"
+msgstr ""
+
+#: ../../assembly_language.rst:404
+msgid "``$FF``"
+msgstr ""
+
+#: ../../assembly_language.rst:406
+msgid "Binary"
+msgstr ""
+
+#: ../../assembly_language.rst:407
+msgid "``0b11111111``"
+msgstr ""
+
+#: ../../assembly_language.rst:411
+msgid "Error Handling"
+msgstr ""
+
+#: ../../assembly_language.rst:413
+msgid "The assembler will report errors for:"
+msgstr ""
+
+#: ../../assembly_language.rst:415
+msgid "Invalid instruction mnemonics"
+msgstr ""
+
+#: ../../assembly_language.rst:416
+msgid "Wrong number of operands"
+msgstr ""
+
+#: ../../assembly_language.rst:417
+msgid "Invalid register numbers (< 0 or > 31)"
+msgstr ""
+
+#: ../../assembly_language.rst:418
+msgid "Undefined label references"
+msgstr ""
+
+#: ../../assembly_language.rst:419
+msgid "Invalid number formats"
+msgstr ""
+
+#: ../../assembly_language.rst:422
+msgid "Best Practices"
+msgstr ""
+
+#: ../../assembly_language.rst:425
+msgid "Code Organization"
+msgstr ""
+
+#: ../../assembly_language.rst:427
+msgid "**Use meaningful labels**: ``calculate_sum`` not ``label1``"
+msgstr ""
+
+#: ../../assembly_language.rst:428
+msgid "**Comment liberally**: Explain what and why, not just how"
+msgstr ""
+
+#: ../../assembly_language.rst:429
+msgid "**Group related code**: Keep subroutines together"
+msgstr ""
+
+#: ../../assembly_language.rst:430
+msgid "**Use blank lines**: Separate logical sections"
+msgstr ""
+
+#: ../../assembly_language.rst:448
+msgid "Naming Conventions"
+msgstr ""
+
+#: ../../assembly_language.rst:450
+msgid "**Labels**: Use ``snake_case`` or ``CamelCase`` consistently"
+msgstr ""
+
+#: ../../assembly_language.rst:451
+msgid "**Constants**: Use ``UPPER_CASE`` for important constants"
+msgstr ""
+
+#: ../../assembly_language.rst:452
+msgid "**Temporary values**: Use lower registers (R0-R15)"
+msgstr ""
+
+#: ../../assembly_language.rst:453
+msgid "**Important data**: Use upper registers (R16-R31)"
+msgstr ""
+
+#: ../../assembly_language.rst:456
+msgid "Register Allocation"
+msgstr ""
+
+#: ../../assembly_language.rst:458
+msgid "Plan your register usage:"
+msgstr ""
+
+#: ../../assembly_language.rst:469
+msgid "Value Ranges"
+msgstr ""
+
+#: ../../assembly_language.rst:471
+msgid "Remember that Tiny8 uses 8-bit values:"
+msgstr ""
+
+#: ../../assembly_language.rst:473
+msgid "Unsigned range: 0 to 255"
+msgstr ""
+
+#: ../../assembly_language.rst:474
+msgid "Signed range: -128 to +127"
+msgstr ""
+
+#: ../../assembly_language.rst:475
+msgid "Overflow wraps around"
+msgstr ""
+
+#: ../../assembly_language.rst:486
+msgid "Common Patterns"
+msgstr ""
+
+#: ../../assembly_language.rst:488
+msgid ""
+"See the :doc:`getting_started` guide for common assembly patterns like "
+"loops, conditionals, and memory operations."
+msgstr ""
+
+#: ../../assembly_language.rst:491
+msgid "Instruction Set Reference"
+msgstr ""
+
+#: ../../assembly_language.rst:493
+msgid ""
+"The Tiny8 instruction set strictly follows the **Microchip AVR® "
+"Instruction Set Manual (DS40002198A)**. All mnemonics and register "
+"identifiers are case-insensitive. Immediates can be specified in decimal,"
+" hexadecimal (``$FF`` or ``0xFF``), or binary (``0b11111111``)."
+msgstr ""
+
+#: ../../assembly_language.rst:496
+msgid "Arithmetic and Logic Instructions"
+msgstr ""
+
+#: ../../assembly_language.rst:502 ../../assembly_language.rst:606
+#: ../../assembly_language.rst:694 ../../assembly_language.rst:746
+#: ../../assembly_language.rst:806
+msgid "Mnemonic & Operands"
+msgstr ""
+
+#: ../../assembly_language.rst:503 ../../assembly_language.rst:607
+#: ../../assembly_language.rst:695 ../../assembly_language.rst:747
+#: ../../assembly_language.rst:807
+msgid "Description (DS40002198A)"
+msgstr ""
+
+#: ../../assembly_language.rst:504 ../../assembly_language.rst:608
+#: ../../assembly_language.rst:696 ../../assembly_language.rst:748
+#: ../../assembly_language.rst:808
+msgid "Operation"
+msgstr ""
+
+#: ../../assembly_language.rst:505 ../../assembly_language.rst:609
+#: ../../assembly_language.rst:697 ../../assembly_language.rst:749
+#: ../../assembly_language.rst:809
+msgid "Flags"
+msgstr ""
+
+#: ../../assembly_language.rst:506
+msgid "``ADD Rd, Rr``"
+msgstr ""
+
+#: ../../assembly_language.rst:507
+msgid "Add without Carry"
+msgstr ""
+
+#: ../../assembly_language.rst:508
+msgid ":math:`Rd \\leftarrow Rd + Rr`"
+msgstr ""
+
+#: ../../assembly_language.rst:509 ../../assembly_language.rst:513
+#: ../../assembly_language.rst:521 ../../assembly_language.rst:525
+#: ../../assembly_language.rst:529 ../../assembly_language.rst:533
+#: ../../assembly_language.rst:565 ../../assembly_language.rst:641
+#: ../../assembly_language.rst:645 ../../assembly_language.rst:761
+#: ../../assembly_language.rst:773
+msgid "H, S, V, N, Z, C"
+msgstr ""
+
+#: ../../assembly_language.rst:510
+msgid "``ADC Rd, Rr``"
+msgstr ""
+
+#: ../../assembly_language.rst:511
+msgid "Add with Carry"
+msgstr ""
+
+#: ../../assembly_language.rst:512
+msgid ":math:`Rd \\leftarrow Rd + Rr + C`"
+msgstr ""
+
+#: ../../assembly_language.rst:514
+msgid "``ADIW Rd, K``"
+msgstr ""
+
+#: ../../assembly_language.rst:515
+msgid "Add Immediate to Word"
+msgstr ""
+
+#: ../../assembly_language.rst:516
+msgid ":math:`Rd+1:Rd \\leftarrow Rd+1:Rd + K`"
+msgstr ""
+
+#: ../../assembly_language.rst:517 ../../assembly_language.rst:537
+#: ../../assembly_language.rst:765 ../../assembly_language.rst:769
+#: ../../assembly_language.rst:777
+msgid "S, V, N, Z, C"
+msgstr ""
+
+#: ../../assembly_language.rst:518
+msgid "``SUB Rd, Rr``"
+msgstr ""
+
+#: ../../assembly_language.rst:519
+msgid "Subtract without Carry"
+msgstr ""
+
+#: ../../assembly_language.rst:520
+msgid ":math:`Rd \\leftarrow Rd - Rr`"
+msgstr ""
+
+#: ../../assembly_language.rst:522
+msgid "``SUBI Rd, K``"
+msgstr ""
+
+#: ../../assembly_language.rst:523
+msgid "Subtract Immediate"
+msgstr ""
+
+#: ../../assembly_language.rst:524
+msgid ":math:`Rd \\leftarrow Rd - K`"
+msgstr ""
+
+#: ../../assembly_language.rst:526
+msgid "``SBC Rd, Rr``"
+msgstr ""
+
+#: ../../assembly_language.rst:527
+msgid "Subtract with Carry"
+msgstr ""
+
+#: ../../assembly_language.rst:528
+msgid ":math:`Rd \\leftarrow Rd - Rr - C`"
+msgstr ""
+
+#: ../../assembly_language.rst:530
+msgid "``SBCI Rd, K``"
+msgstr ""
+
+#: ../../assembly_language.rst:531
+msgid "Subtract Immediate with Carry"
+msgstr ""
+
+#: ../../assembly_language.rst:532
+msgid ":math:`Rd \\leftarrow Rd - K - C`"
+msgstr ""
+
+#: ../../assembly_language.rst:534
+msgid "``SBIW Rd, K``"
+msgstr ""
+
+#: ../../assembly_language.rst:535
+msgid "Subtract Immediate from Word"
+msgstr ""
+
+#: ../../assembly_language.rst:536
+msgid ":math:`Rd+1:Rd \\leftarrow Rd+1:Rd - K`"
+msgstr ""
+
+#: ../../assembly_language.rst:538
+msgid "``AND Rd, Rr``"
+msgstr ""
+
+#: ../../assembly_language.rst:539
+msgid "Logical AND"
+msgstr ""
+
+#: ../../assembly_language.rst:540
+msgid ":math:`Rd \\leftarrow Rd \\cdot Rr`"
+msgstr ""
+
+#: ../../assembly_language.rst:541 ../../assembly_language.rst:545
+#: ../../assembly_language.rst:549 ../../assembly_language.rst:553
+#: ../../assembly_language.rst:557 ../../assembly_language.rst:577
+msgid "S, V=0, N, Z"
+msgstr ""
+
+#: ../../assembly_language.rst:542
+msgid "``ANDI Rd, K``"
+msgstr ""
+
+#: ../../assembly_language.rst:543
+msgid "Logical AND with Immediate"
+msgstr ""
+
+#: ../../assembly_language.rst:544
+msgid ":math:`Rd \\leftarrow Rd \\cdot K`"
+msgstr ""
+
+#: ../../assembly_language.rst:546
+msgid "``OR Rd, Rr``"
+msgstr ""
+
+#: ../../assembly_language.rst:547
+msgid "Logical OR"
+msgstr ""
+
+#: ../../assembly_language.rst:548
+msgid ":math:`Rd \\leftarrow Rd \\lor Rr`"
+msgstr ""
+
+#: ../../assembly_language.rst:550
+msgid "``ORI Rd, K``"
+msgstr ""
+
+#: ../../assembly_language.rst:551
+msgid "Logical OR with Immediate"
+msgstr ""
+
+#: ../../assembly_language.rst:552
+msgid ":math:`Rd \\leftarrow Rd \\lor K`"
+msgstr ""
+
+#: ../../assembly_language.rst:554
+msgid "``EOR Rd, Rr``"
+msgstr ""
+
+#: ../../assembly_language.rst:555
+msgid "Exclusive OR"
+msgstr ""
+
+#: ../../assembly_language.rst:556
+msgid ":math:`Rd \\leftarrow Rd \\oplus Rr`"
+msgstr ""
+
+#: ../../assembly_language.rst:558
+msgid "``COM Rd``"
+msgstr ""
+
+#: ../../assembly_language.rst:559
+msgid "One's Complement"
+msgstr ""
+
+#: ../../assembly_language.rst:560
+msgid ":math:`Rd \\leftarrow \\$FF - Rd`"
+msgstr ""
+
+#: ../../assembly_language.rst:561
+msgid "S, V=0, N, Z, C=1"
+msgstr ""
+
+#: ../../assembly_language.rst:562
+msgid "``NEG Rd``"
+msgstr ""
+
+#: ../../assembly_language.rst:563
+msgid "Two's Complement Negation"
+msgstr ""
+
+#: ../../assembly_language.rst:564
+msgid ":math:`Rd \\leftarrow \\$00 - Rd`"
+msgstr ""
+
+#: ../../assembly_language.rst:566
+msgid "``INC Rd``"
+msgstr ""
+
+#: ../../assembly_language.rst:567
+msgid "Increment"
+msgstr ""
+
+#: ../../assembly_language.rst:568
+msgid ":math:`Rd \\leftarrow Rd + 1`"
+msgstr ""
+
+#: ../../assembly_language.rst:569 ../../assembly_language.rst:573
+msgid "S, V, N, Z"
+msgstr ""
+
+#: ../../assembly_language.rst:570
+msgid "``DEC Rd``"
+msgstr ""
+
+#: ../../assembly_language.rst:571
+msgid "Decrement"
+msgstr ""
+
+#: ../../assembly_language.rst:572
+msgid ":math:`Rd \\leftarrow Rd - 1`"
+msgstr ""
+
+#: ../../assembly_language.rst:574
+msgid "``TST Rd``"
+msgstr ""
+
+#: ../../assembly_language.rst:575
+msgid "Test for Zero or Minus"
+msgstr ""
+
+#: ../../assembly_language.rst:576
+msgid ":math:`Rd \\leftarrow Rd \\cdot Rd` (alias for AND)"
+msgstr ""
+
+#: ../../assembly_language.rst:578
+msgid "``CLR Rd``"
+msgstr ""
+
+#: ../../assembly_language.rst:579
+msgid "Clear Register"
+msgstr ""
+
+#: ../../assembly_language.rst:580
+msgid ":math:`Rd \\leftarrow Rd \\oplus Rd` (alias for EOR)"
+msgstr ""
+
+#: ../../assembly_language.rst:581
+msgid "S=0, V=0, N=0, Z=1"
+msgstr ""
+
+#: ../../assembly_language.rst:582
+msgid "``SER Rd``"
+msgstr ""
+
+#: ../../assembly_language.rst:583
+msgid "Set Register"
+msgstr ""
+
+#: ../../assembly_language.rst:584
+msgid ":math:`Rd \\leftarrow \\$FF` (alias for LDI)"
+msgstr ""
+
+#: ../../assembly_language.rst:585 ../../assembly_language.rst:613
+#: ../../assembly_language.rst:617 ../../assembly_language.rst:621
+#: ../../assembly_language.rst:625 ../../assembly_language.rst:629
+#: ../../assembly_language.rst:637 ../../assembly_language.rst:649
+#: ../../assembly_language.rst:653 ../../assembly_language.rst:657
+#: ../../assembly_language.rst:661 ../../assembly_language.rst:665
+#: ../../assembly_language.rst:669 ../../assembly_language.rst:673
+#: ../../assembly_language.rst:677 ../../assembly_language.rst:681
+#: ../../assembly_language.rst:685 ../../assembly_language.rst:701
+#: ../../assembly_language.rst:705 ../../assembly_language.rst:709
+#: ../../assembly_language.rst:713 ../../assembly_language.rst:717
+#: ../../assembly_language.rst:721 ../../assembly_language.rst:725
+#: ../../assembly_language.rst:729 ../../assembly_language.rst:733
+#: ../../assembly_language.rst:737 ../../assembly_language.rst:753
+#: ../../assembly_language.rst:757 ../../assembly_language.rst:781
+#: ../../assembly_language.rst:785 ../../assembly_language.rst:789
+#: ../../assembly_language.rst:793 ../../assembly_language.rst:797
+#: ../../assembly_language.rst:813
+msgid "None"
+msgstr ""
+
+#: ../../assembly_language.rst:586
+msgid "``MUL Rd, Rr``"
+msgstr ""
+
+#: ../../assembly_language.rst:587
+msgid "Multiply Unsigned"
+msgstr ""
+
+#: ../../assembly_language.rst:588
+msgid ":math:`R1:R0 \\leftarrow Rd \\times Rr`"
+msgstr ""
+
+#: ../../assembly_language.rst:589 ../../assembly_language.rst:593
+#: ../../assembly_language.rst:597
+msgid "Z, C"
+msgstr ""
+
+#: ../../assembly_language.rst:590
+msgid "``MULS Rd, Rr``"
+msgstr ""
+
+#: ../../assembly_language.rst:591
+msgid "Multiply Signed"
+msgstr ""
+
+#: ../../assembly_language.rst:592
+msgid ":math:`R1:R0 \\leftarrow Rd \\times Rr` (signed)"
+msgstr ""
+
+#: ../../assembly_language.rst:594
+msgid "``MULSU Rd, Rr``"
+msgstr ""
+
+#: ../../assembly_language.rst:595
+msgid "Multiply Signed with Unsigned"
+msgstr ""
+
+#: ../../assembly_language.rst:596
+msgid ""
+":math:`R1:R0 \\leftarrow Rd \\times Rr` (:math:`Rd` signed, :math:`Rr` "
+"unsigned)"
+msgstr ""
+
+#: ../../assembly_language.rst:600
+msgid "Branch Instructions"
+msgstr ""
+
+#: ../../assembly_language.rst:610
+msgid "``JMP target``"
+msgstr ""
+
+#: ../../assembly_language.rst:611
+msgid "Jump"
+msgstr ""
+
+#: ../../assembly_language.rst:612
+msgid ":math:`PC \\leftarrow target`"
+msgstr ""
+
+#: ../../assembly_language.rst:614
+msgid "``RJMP offset``"
+msgstr ""
+
+#: ../../assembly_language.rst:615
+msgid "Relative Jump"
+msgstr ""
+
+#: ../../assembly_language.rst:616
+msgid ":math:`PC \\leftarrow PC + offset + 1`"
+msgstr ""
+
+#: ../../assembly_language.rst:618
+msgid "``CALL target``"
+msgstr ""
+
+#: ../../assembly_language.rst:619
+msgid "Long Call to Subroutine"
+msgstr ""
+
+#: ../../assembly_language.rst:620
+msgid ":math:`STACK \\leftarrow PC + 1, PC \\leftarrow target`"
+msgstr ""
+
+#: ../../assembly_language.rst:622
+msgid "``RCALL offset``"
+msgstr ""
+
+#: ../../assembly_language.rst:623
+msgid "Relative Call to Subroutine"
+msgstr ""
+
+#: ../../assembly_language.rst:624
+msgid ":math:`STACK \\leftarrow PC + 1, PC \\leftarrow PC + offset + 1`"
+msgstr ""
+
+#: ../../assembly_language.rst:626
+msgid "``RET``"
+msgstr ""
+
+#: ../../assembly_language.rst:627
+msgid "Return from Subroutine"
+msgstr ""
+
+#: ../../assembly_language.rst:628
+msgid ":math:`PC \\leftarrow STACK`"
+msgstr ""
+
+#: ../../assembly_language.rst:630
+msgid "``RETI``"
+msgstr ""
+
+#: ../../assembly_language.rst:631
+msgid "Return from Interrupt"
+msgstr ""
+
+#: ../../assembly_language.rst:632
+msgid ":math:`PC \\leftarrow STACK, I \\leftarrow 1`"
+msgstr ""
+
+#: ../../assembly_language.rst:633 ../../assembly_language.rst:817
+#: ../../assembly_language.rst:821
+msgid "I"
+msgstr ""
+
+#: ../../assembly_language.rst:634
+msgid "``CPSE Rd, Rr``"
+msgstr ""
+
+#: ../../assembly_language.rst:635
+msgid "Compare Skip if Equal"
+msgstr ""
+
+#: ../../assembly_language.rst:636
+msgid "If :math:`Rd = Rr` then skip next instruction"
+msgstr ""
+
+#: ../../assembly_language.rst:638
+msgid "``CP Rd, Rr``"
+msgstr ""
+
+#: ../../assembly_language.rst:639
+msgid "Compare"
+msgstr ""
+
+#: ../../assembly_language.rst:640
+msgid ":math:`Rd - Rr`"
+msgstr ""
+
+#: ../../assembly_language.rst:642
+msgid "``CPI Rd, K``"
+msgstr ""
+
+#: ../../assembly_language.rst:643
+msgid "Compare with Immediate"
+msgstr ""
+
+#: ../../assembly_language.rst:644
+msgid ":math:`Rd - K`"
+msgstr ""
+
+#: ../../assembly_language.rst:646
+msgid "``BREQ label``"
+msgstr ""
+
+#: ../../assembly_language.rst:647
+msgid "Branch if Equal"
+msgstr ""
+
+#: ../../assembly_language.rst:648
+msgid "If :math:`Z = 1` then :math:`PC \\leftarrow label`"
+msgstr ""
+
+#: ../../assembly_language.rst:650
+msgid "``BRNE label``"
+msgstr ""
+
+#: ../../assembly_language.rst:651
+msgid "Branch if Not Equal"
+msgstr ""
+
+#: ../../assembly_language.rst:652
+msgid "If :math:`Z = 0` then :math:`PC \\leftarrow label`"
+msgstr ""
+
+#: ../../assembly_language.rst:654
+msgid "``BRCS label``"
+msgstr ""
+
+#: ../../assembly_language.rst:655
+msgid "Branch if Carry Set"
+msgstr ""
+
+#: ../../assembly_language.rst:656
+msgid "If :math:`C = 1` then :math:`PC \\leftarrow label`"
+msgstr ""
+
+#: ../../assembly_language.rst:658
+msgid "``BRCC label``"
+msgstr ""
+
+#: ../../assembly_language.rst:659
+msgid "Branch if Carry Clear"
+msgstr ""
+
+#: ../../assembly_language.rst:660
+msgid "If :math:`C = 0` then :math:`PC \\leftarrow label`"
+msgstr ""
+
+#: ../../assembly_language.rst:662
+msgid "``BRLO label``"
+msgstr ""
+
+#: ../../assembly_language.rst:663
+msgid "Branch if Lower (Unsigned)"
+msgstr ""
+
+#: ../../assembly_language.rst:664
+msgid "If :math:`C = 1` then :math:`PC \\leftarrow label` (alias for BRCS)"
+msgstr ""
+
+#: ../../assembly_language.rst:666
+msgid "``BRSH label``"
+msgstr ""
+
+#: ../../assembly_language.rst:667
+msgid "Branch if Same or Higher"
+msgstr ""
+
+#: ../../assembly_language.rst:668
+msgid "If :math:`C = 0` then :math:`PC \\leftarrow label` (alias for BRCC)"
+msgstr ""
+
+#: ../../assembly_language.rst:670
+msgid "``BRGE label``"
+msgstr ""
+
+#: ../../assembly_language.rst:671
+msgid "Branch if Greater or Equal (Signed)"
+msgstr ""
+
+#: ../../assembly_language.rst:672
+msgid ""
+"If :math:`S = 0` (:math:`N \\oplus V = 0`) then :math:`PC \\leftarrow "
+"label`"
+msgstr ""
+
+#: ../../assembly_language.rst:674
+msgid "``BRLT label``"
+msgstr ""
+
+#: ../../assembly_language.rst:675
+msgid "Branch if Less Than (Signed)"
+msgstr ""
+
+#: ../../assembly_language.rst:676
+msgid ""
+"If :math:`S = 1` (:math:`N \\oplus V = 1`) then :math:`PC \\leftarrow "
+"label`"
+msgstr ""
+
+#: ../../assembly_language.rst:678
+msgid "``BRMI label``"
+msgstr ""
+
+#: ../../assembly_language.rst:679
+msgid "Branch if Minus"
+msgstr ""
+
+#: ../../assembly_language.rst:680
+msgid "If :math:`N = 1` then :math:`PC \\leftarrow label`"
+msgstr ""
+
+#: ../../assembly_language.rst:682
+msgid "``BRPL label``"
+msgstr ""
+
+#: ../../assembly_language.rst:683
+msgid "Branch if Plus"
+msgstr ""
+
+#: ../../assembly_language.rst:684
+msgid "If :math:`N = 0` then :math:`PC \\leftarrow label`"
+msgstr ""
+
+#: ../../assembly_language.rst:688
+msgid "Data Transfer Instructions"
+msgstr ""
+
+#: ../../assembly_language.rst:698
+msgid "``MOV Rd, Rr``"
+msgstr ""
+
+#: ../../assembly_language.rst:699
+msgid "Copy Register"
+msgstr ""
+
+#: ../../assembly_language.rst:700
+msgid ":math:`Rd \\leftarrow Rr`"
+msgstr ""
+
+#: ../../assembly_language.rst:702
+msgid "``LDI Rd, K``"
+msgstr ""
+
+#: ../../assembly_language.rst:703
+msgid "Load Immediate"
+msgstr ""
+
+#: ../../assembly_language.rst:704
+msgid ":math:`Rd \\leftarrow K` (:math:`16 \\le d \\le 31`)"
+msgstr ""
+
+#: ../../assembly_language.rst:706
+msgid "``LD Rd, addr_reg``"
+msgstr ""
+
+#: ../../assembly_language.rst:707
+msgid "Load Indirect from Data Space"
+msgstr ""
+
+#: ../../assembly_language.rst:708
+msgid ":math:`Rd \\leftarrow (addr\\_reg)`"
+msgstr ""
+
+#: ../../assembly_language.rst:710
+msgid "``ST addr_reg, Rr``"
+msgstr ""
+
+#: ../../assembly_language.rst:711
+msgid "Store Indirect to Data Space"
+msgstr ""
+
+#: ../../assembly_language.rst:712
+msgid ":math:`(addr\\_reg) \\leftarrow Rr`"
+msgstr ""
+
+#: ../../assembly_language.rst:714
+msgid "``LDS Rd, addr``"
+msgstr ""
+
+#: ../../assembly_language.rst:715
+msgid "Load Direct from Data Space"
+msgstr ""
+
+#: ../../assembly_language.rst:716
+msgid ":math:`Rd \\leftarrow (addr)`"
+msgstr ""
+
+#: ../../assembly_language.rst:718
+msgid "``STS addr, Rr``"
+msgstr ""
+
+#: ../../assembly_language.rst:719
+msgid "Store Direct to Data Space"
+msgstr ""
+
+#: ../../assembly_language.rst:720
+msgid ":math:`(addr) \\leftarrow Rr`"
+msgstr ""
+
+#: ../../assembly_language.rst:722
+msgid "``IN Rd, port``"
+msgstr ""
+
+#: ../../assembly_language.rst:723
+msgid "Load an I/O Location to Register"
+msgstr ""
+
+#: ../../assembly_language.rst:724
+msgid ":math:`Rd \\leftarrow P`"
+msgstr ""
+
+#: ../../assembly_language.rst:726
+msgid "``OUT port, Rr``"
+msgstr ""
+
+#: ../../assembly_language.rst:727
+msgid "Store Register to an I/O Location"
+msgstr ""
+
+#: ../../assembly_language.rst:728
+msgid ":math:`P \\leftarrow Rr`"
+msgstr ""
+
+#: ../../assembly_language.rst:730
+msgid "``PUSH Rr``"
+msgstr ""
+
+#: ../../assembly_language.rst:731
+msgid "Push Register on Stack"
+msgstr ""
+
+#: ../../assembly_language.rst:732
+msgid ":math:`STACK \\leftarrow Rr, SP \\leftarrow SP - 1`"
+msgstr ""
+
+#: ../../assembly_language.rst:734
+msgid "``POP Rd``"
+msgstr ""
+
+#: ../../assembly_language.rst:735
+msgid "Pop Register from Stack"
+msgstr ""
+
+#: ../../assembly_language.rst:736
+msgid ":math:`SP \\leftarrow SP + 1, Rd \\leftarrow STACK`"
+msgstr ""
+
+#: ../../assembly_language.rst:740
+msgid "Bit and Bit-Test Instructions"
+msgstr ""
+
+#: ../../assembly_language.rst:750
+msgid "``SBI port, bit``"
+msgstr ""
+
+#: ../../assembly_language.rst:751
+msgid "Set Bit in I/O Register"
+msgstr ""
+
+#: ../../assembly_language.rst:752
+msgid ":math:`I/O(P, bit) \\leftarrow 1`"
+msgstr ""
+
+#: ../../assembly_language.rst:754
+msgid "``CBI port, bit``"
+msgstr ""
+
+#: ../../assembly_language.rst:755
+msgid "Clear Bit in I/O Register"
+msgstr ""
+
+#: ../../assembly_language.rst:756
+msgid ":math:`I/O(P, bit) \\leftarrow 0`"
+msgstr ""
+
+#: ../../assembly_language.rst:758
+msgid "``LSL Rd``"
+msgstr ""
+
+#: ../../assembly_language.rst:759
+msgid "Logical Shift Left"
+msgstr ""
+
+#: ../../assembly_language.rst:760
+msgid ":math:`Rd \\leftarrow Rd \\ll 1` (alias for ADD Rd, Rd)"
+msgstr ""
+
+#: ../../assembly_language.rst:762
+msgid "``LSR Rd``"
+msgstr ""
+
+#: ../../assembly_language.rst:763
+msgid "Logical Shift Right"
+msgstr ""
+
+#: ../../assembly_language.rst:764
+msgid ":math:`0 \\rightarrow Rd7 \\dots Rd0 \\rightarrow C`"
+msgstr ""
+
+#: ../../assembly_language.rst:766
+msgid "``ASR Rd``"
+msgstr ""
+
+#: ../../assembly_language.rst:767
+msgid "Arithmetic Shift Right"
+msgstr ""
+
+#: ../../assembly_language.rst:768
+msgid ":math:`Rd7 \\rightarrow Rd7 \\dots Rd0 \\rightarrow C`"
+msgstr ""
+
+#: ../../assembly_language.rst:770
+msgid "``ROL Rd``"
+msgstr ""
+
+#: ../../assembly_language.rst:771
+msgid "Rotate Left through Carry"
+msgstr ""
+
+#: ../../assembly_language.rst:772
+msgid ":math:`C \\leftarrow Rd7 \\dots Rd0 \\leftarrow C` (alias for ADC Rd, Rd)"
+msgstr ""
+
+#: ../../assembly_language.rst:774
+msgid "``ROR Rd``"
+msgstr ""
+
+#: ../../assembly_language.rst:775
+msgid "Rotate Right through Carry"
+msgstr ""
+
+#: ../../assembly_language.rst:776
+msgid ":math:`C \\rightarrow Rd7 \\dots Rd0 \\rightarrow C`"
+msgstr ""
+
+#: ../../assembly_language.rst:778
+msgid "``SWAP Rd``"
+msgstr ""
+
+#: ../../assembly_language.rst:779
+msgid "Swap Nibbles"
+msgstr ""
+
+#: ../../assembly_language.rst:780
+msgid ":math:`Rd(7..4) \\leftrightarrow Rd(3..0)`"
+msgstr ""
+
+#: ../../assembly_language.rst:782
+msgid "``SBRS Rd, bit``"
+msgstr ""
+
+#: ../../assembly_language.rst:783
+msgid "Skip if Bit in Register is Set"
+msgstr ""
+
+#: ../../assembly_language.rst:784
+msgid "If :math:`Rd(bit) = 1` then skip next instruction"
+msgstr ""
+
+#: ../../assembly_language.rst:786
+msgid "``SBRC Rd, bit``"
+msgstr ""
+
+#: ../../assembly_language.rst:787
+msgid "Skip if Bit in Register is Cleared"
+msgstr ""
+
+#: ../../assembly_language.rst:788
+msgid "If :math:`Rd(bit) = 0` then skip next instruction"
+msgstr ""
+
+#: ../../assembly_language.rst:790
+msgid "``SBIS port, bit``"
+msgstr ""
+
+#: ../../assembly_language.rst:791
+msgid "Skip if Bit in I/O Register is Set"
+msgstr ""
+
+#: ../../assembly_language.rst:792
+msgid "If :math:`I/O(P, bit) = 1` then skip next instruction"
+msgstr ""
+
+#: ../../assembly_language.rst:794
+msgid "``SBIC port, bit``"
+msgstr ""
+
+#: ../../assembly_language.rst:795
+msgid "Skip if Bit in I/O Register is Cleared"
+msgstr ""
+
+#: ../../assembly_language.rst:796
+msgid "If :math:`I/O(P, bit) = 0` then skip next instruction"
+msgstr ""
+
+#: ../../assembly_language.rst:800
+msgid "MCU Control Instructions"
+msgstr ""
+
+#: ../../assembly_language.rst:810
+msgid "``NOP``"
+msgstr ""
+
+#: ../../assembly_language.rst:811
+msgid "No Operation"
+msgstr ""
+
+#: ../../assembly_language.rst:812
+msgid "No operation performed"
+msgstr ""
+
+#: ../../assembly_language.rst:814
+msgid "``SEI``"
+msgstr ""
+
+#: ../../assembly_language.rst:815
+msgid "Set Global Interrupt Flag"
+msgstr ""
+
+#: ../../assembly_language.rst:816
+msgid ":math:`I \\leftarrow 1`"
+msgstr ""
+
+#: ../../assembly_language.rst:818
+msgid "``CLI``"
+msgstr ""
+
+#: ../../assembly_language.rst:819
+msgid "Clear Global Interrupt Flag"
+msgstr ""
+
+#: ../../assembly_language.rst:820
+msgid ":math:`I \\leftarrow 0`"
+msgstr ""
+
+#~ msgid "``EORI Rd, K``"
+#~ msgstr ""
+
+#~ msgid "Exclusive OR with Immediate"
+#~ msgstr ""
+
+#~ msgid ":math:`Rd \\leftarrow Rd \\oplus K`"
+#~ msgstr ""
+
diff --git a/docs/locales/ja/LC_MESSAGES/examples.po b/docs/locales/ja/LC_MESSAGES/examples.po
new file mode 100644
index 0000000..e5d9a57
--- /dev/null
+++ b/docs/locales/ja/LC_MESSAGES/examples.po
@@ -0,0 +1,1331 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, 2026.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:17+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language: ja\n"
+"Language-Team: ja <LL@li.org>\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=utf-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Generated-By: Babel 2.17.0\n"
+
+#: ../../examples/array_sum.rst:2 ../../examples/index.rst:113
+msgid "Array Sum"
+msgstr ""
+
+#: ../../examples/array_sum.rst:4
+msgid "Sums elements of an array stored in memory."
+msgstr ""
+
+#: ../../examples/array_sum.rst:10
+msgid "Demonstrates memory access and array processing."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:2 ../../examples/bubblesort.rst:351
+#: ../../examples/index.rst:125
+msgid "Bubble Sort"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:4
+msgid ""
+"This advanced example demonstrates bubble sort: a classic sorting "
+"algorithm that sorts an array in memory."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:7 ../../examples/fibonacci.rst:7
+#: ../../examples/index.rst:7
+msgid "Overview"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:9
+msgid "**Difficulty**: Advanced"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:11
+msgid ""
+"**Concepts**: Nested loops, memory operations, array manipulation, "
+"pseudo-random number generation"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:13
+msgid "**Output**: Sorted array at RAM[0x60..0x7F] (32 bytes in ascending order)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:16 ../../examples/fibonacci.rst:16
+msgid "The Program"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:23
+msgid "Algorithm Overview"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:25
+msgid "The program has two main phases:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:27
+msgid "**Initialization**: Generate 32 pseudo-random values and store them in RAM"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:28
+msgid "**Bubble Sort**: Sort the array using the bubble sort algorithm"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:31
+msgid "Phase 1: Array Initialization"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:34
+msgid "Pseudo-Random Number Generator"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:36
+msgid "The program uses a simple linear congruential generator (LCG):"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:42
+msgid "This generates a sequence of pseudo-random 8-bit values."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:56
+msgid "After 32 iterations, RAM[0x60..0x7F] contains pseudo-random values."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:59
+msgid "Phase 2: Bubble Sort"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:62 ../../examples/fibonacci.rst:23
+msgid "Algorithm Explanation"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:64
+msgid ""
+"Bubble sort works by repeatedly stepping through the array, comparing "
+"adjacent elements, and swapping them if they're in the wrong order."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:74
+msgid "Outer Loop"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:87
+msgid "Runs 31 times (i = 0 to 30)."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:90
+msgid "Inner Loop"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:119
+msgid "For each j:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:121
+msgid "Load adjacent elements (j and j+1)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:122
+msgid "Compare them"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:123
+msgid "Swap if first > second (for ascending order)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:124
+msgid "Advance to next pair"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:127
+msgid "Register Usage"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:129
+msgid "Register Allocation"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:133
+msgid "Register"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:134
+msgid "Purpose"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:135
+msgid "R16"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:136
+msgid "Memory address pointer / base address"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:137
+msgid "R17"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:138
+msgid "Array index during initialization"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:139
+msgid "R18"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:140
+msgid "PRNG seed / outer loop counter (i)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:141
+msgid "R19"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:142
+msgid "Inner loop counter (j)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:143
+msgid "R20"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:144
+msgid "Address of element A"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:145
+msgid "R21"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:146
+msgid "Value of element A"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:147
+msgid "R22"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:148
+msgid "Address of element B"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:149
+msgid "R23"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:150
+msgid "Temporary comparison value"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:151
+msgid "R24"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:152
+msgid "Value of element B"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:153
+msgid "R25"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:154
+msgid "PRNG multiplier constant (75)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:157
+msgid "Memory Layout"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:174
+msgid "Execution Example"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:177
+msgid "Initial Array (pseudo-random)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:184
+msgid "After Bubble Sort"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:190
+msgid ""
+"Bubble sort compares and swaps adjacent elements until the entire array "
+"is sorted."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:193 ../../examples/fibonacci.rst:139
+msgid "Running the Example"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:196 ../../examples/fibonacci.rst:142
+msgid "Interactive Debugger"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:202
+msgid ""
+"Watch the sorting process step-by-step. Set marks at the beginning of "
+"inner_loop to track passes."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:205 ../../examples/fibonacci.rst:151
+msgid "Animation"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:212
+msgid "Creates a visualization showing:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:214
+msgid "Memory heatmap of the array being sorted"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:215
+msgid "Register changes during comparisons"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:216
+msgid "Visual pattern of values moving to their correct positions"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:219 ../../examples/fibonacci.rst:160
+msgid "Python API"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:239
+msgid "Performance Analysis"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:242 ../../examples/bubblesort.rst:348
+msgid "Time Complexity"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:244
+msgid "**Best case**: O(n²) - 31 × 31 = 961 comparisons"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:245
+msgid ""
+"**Worst case**: O(n²) - Same as best (this implementation doesn't "
+"optimize)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:246
+msgid "**Average case**: O(n²)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:248
+msgid "For 32 elements:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:250
+msgid "Outer loop: 31 iterations"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:251
+msgid "Inner loop: 31 iterations per outer"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:252
+msgid "Total comparisons: ~961"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:253
+msgid "Total swaps: Variable (depends on initial order)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:256
+msgid "Instruction Count"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:258
+msgid "Each comparison involves approximately:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:260
+msgid "10 instructions to load addresses and values"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:261
+msgid "5 instructions for comparison and potential swap"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:262
+msgid "3 instructions for loop control"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:264
+msgid "Total: ~15,000+ instructions for a complete sort."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:267 ../../examples/fibonacci.rst:173
+msgid "Key Concepts"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:270
+msgid "Nested Loops"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:272
+msgid "Two loop counters working together:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:286
+msgid "Address Calculation"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:288
+msgid "Computing memory addresses dynamically:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:297
+msgid "Conditional Swapping"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:308 ../../examples/fibonacci.rst:202
+msgid "Exercises"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:310
+msgid "**Count swaps**: Add a counter to track number of swaps"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:311
+msgid "**Optimize**: Add early exit if no swaps occurred in a pass"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:312
+msgid "**Different sizes**: Sort 16 or 64 elements instead"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:313
+msgid "**Descending order**: Modify to sort in descending order"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:314
+msgid "**Different algorithm**: Implement selection sort or insertion sort"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:317
+msgid "Solutions Hints"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:319
+msgid "**Count swaps**: Add ``inc r26`` in the swap section, initialize R26 to 0."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:321
+msgid "**Optimize**: Set a flag when swapping, check it at end of outer loop."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:323
+msgid "**Descending order**: Change ``brcs no_swap`` to ``brcc no_swap``."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:326
+msgid "Visualization Tips"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:328
+msgid "When viewing the animation:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:330
+msgid "**Memory panel**: Watch values \"bubble\" to their positions"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:331
+msgid "**Register panel**: R19 (j) cycles 0-30 repeatedly"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:332
+msgid "**Register panel**: R18 (i) increments slowly"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:334
+msgid "Look for:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:336
+msgid "Large values moving right (higher addresses)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:337
+msgid "Small values moving left (lower addresses)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:338
+msgid "Progressively fewer changes as array becomes sorted"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:341
+msgid "Comparison with Other Sorts"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:343
+msgid "Sorting Algorithm Comparison"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:347
+msgid "Algorithm"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:349
+msgid "Space"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:350
+msgid "Stability"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:352 ../../examples/bubblesort.rst:356
+#: ../../examples/bubblesort.rst:360
+msgid "O(n²)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:353 ../../examples/bubblesort.rst:357
+#: ../../examples/bubblesort.rst:361
+msgid "O(1)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:354 ../../examples/bubblesort.rst:362
+msgid "Yes"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:355
+msgid "Selection Sort"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:358 ../../examples/bubblesort.rst:366
+msgid "No"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:359
+msgid "Insertion Sort"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:363
+msgid "Quick Sort"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:364
+msgid "O(n log n)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:365
+msgid "O(log n)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:368
+msgid ""
+"Bubble sort is chosen for this example because it's conceptually simple "
+"and demonstrates memory operations clearly."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:371 ../../examples/fibonacci.rst:232
+msgid "Related Examples"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:373
+msgid ":doc:`linear_search` - Sequential array access"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:374
+msgid ":doc:`find_max` - Array comparison operations"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:375
+msgid ":doc:`reverse` - Array manipulation"
+msgstr ""
+
+#: ../../examples/count_bits.rst:2 ../../examples/index.rst:137
+msgid "Count Bits"
+msgstr ""
+
+#: ../../examples/count_bits.rst:4
+msgid "Counts the number of set bits (1s) in a value."
+msgstr ""
+
+#: ../../examples/count_bits.rst:10
+msgid "Demonstrates bit manipulation and counting operations."
+msgstr ""
+
+#: ../../examples/factorial.rst:2
+msgid "Factorial"
+msgstr ""
+
+#: ../../examples/factorial.rst:4
+msgid "Computes factorial of a number using iterative multiplication."
+msgstr ""
+
+#: ../../examples/factorial.rst:10
+msgid ""
+"Calculates 5! = 120 using repeated multiplication and demonstrates loop "
+"control."
+msgstr ""
+
+#: ../../examples/fibonacci.rst:2
+msgid "Fibonacci Sequence"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:4
+msgid ""
+"This example calculates the 10th Fibonacci number using an iterative "
+"approach."
+msgstr ""
+
+#: ../../examples/fibonacci.rst:9
+msgid "**Difficulty**: Beginner"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:11
+msgid "**Concepts**: Loops, register arithmetic, conditional branching"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:13
+msgid "**Output**: R17 contains F(10) = 55"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:25
+msgid "The Fibonacci sequence is defined as:"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:27
+msgid "F(0) = 0"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:28
+msgid "F(1) = 1"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:29
+msgid "F(n) = F(n-1) + F(n-2) for n > 1"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:31
+msgid "This program uses an iterative approach with three registers:"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:33
+msgid "**R16**: Previous Fibonacci number (F(n-1))"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:34
+msgid "**R17**: Current Fibonacci number (F(n))"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:35
+msgid "**R18**: Counter (remaining iterations)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:38
+msgid "Step-by-Step Walkthrough"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:41
+msgid "Initialization (Lines 8-10)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:49
+msgid ""
+"We start with F(0) = 0 and F(1) = 1. Since we want F(10), we need 9 more "
+"iterations (F(2) through F(10))."
+msgstr ""
+
+#: ../../examples/fibonacci.rst:52
+msgid "Main Loop (Lines 12-18)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:64
+msgid "Each iteration:"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:66
+msgid "**Add**: Compute next Fibonacci number (R16 + R17)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:67
+msgid "**Save**: Store result in temporary register R19"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:68
+msgid "**Shift**: Move R17 to R16 (previous ← current)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:69
+msgid "**Update**: Move R19 to R17 (current ← new result)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:70
+msgid "**Decrement**: Decrease counter"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:71
+msgid "**Branch**: Loop if counter ≠ 0"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:74
+msgid "Execution Trace"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:76
+msgid "Here's how the registers evolve:"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:78
+msgid "Fibonacci Calculation"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:82
+msgid "Iter"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:83
+msgid "R16 (prev)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:84
+msgid "R17 (curr)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:85
+msgid "R18 (count)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:86
+msgid "Calculation"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:87
+msgid "Init"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:88 ../../examples/fibonacci.rst:135
+msgid "0"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:89 ../../examples/fibonacci.rst:92
+#: ../../examples/fibonacci.rst:93 ../../examples/fibonacci.rst:94
+#: ../../examples/fibonacci.rst:98 ../../examples/fibonacci.rst:130
+msgid "1"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:90 ../../examples/fibonacci.rst:132
+msgid "9"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:91
+msgid "F(0), F(1)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:95 ../../examples/fibonacci.rst:114
+#: ../../examples/fibonacci.rst:118 ../../examples/fibonacci.rst:127
+msgid "8"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:96
+msgid "F(2) = 0 + 1 = 1"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:97 ../../examples/fibonacci.rst:99
+#: ../../examples/fibonacci.rst:103 ../../examples/fibonacci.rst:125
+msgid "2"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:100 ../../examples/fibonacci.rst:122
+msgid "7"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:101
+msgid "F(3) = 1 + 1 = 2"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:102 ../../examples/fibonacci.rst:104
+#: ../../examples/fibonacci.rst:108 ../../examples/fibonacci.rst:120
+msgid "3"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:105 ../../examples/fibonacci.rst:117
+msgid "6"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:106
+msgid "F(4) = 1 + 2 = 3"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:107 ../../examples/fibonacci.rst:115
+msgid "4"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:109 ../../examples/fibonacci.rst:110
+#: ../../examples/fibonacci.rst:112 ../../examples/fibonacci.rst:113
+msgid "5"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:111
+msgid "F(5) = 2 + 3 = 5"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:116
+msgid "F(6) = 3 + 5 = 8"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:119 ../../examples/fibonacci.rst:123
+msgid "13"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:121
+msgid "F(7) = 5 + 8 = 13"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:124 ../../examples/fibonacci.rst:128
+msgid "21"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:126
+msgid "F(8) = 8 + 13 = 21"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:129 ../../examples/fibonacci.rst:133
+msgid "34"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:131
+msgid "F(9) = 13 + 21 = 34"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:134
+msgid "55"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:136
+msgid "F(10) = 21 + 34 = 55"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:148
+msgid "Step through with ``j`` and watch registers R16, R17, and R18 evolve."
+msgstr ""
+
+#: ../../examples/fibonacci.rst:157
+msgid "Visualize the register changes over time."
+msgstr ""
+
+#: ../../examples/fibonacci.rst:176
+msgid "Loop Structure"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:178
+msgid "The loop pattern is common in assembly:"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:189
+msgid "Register Shifting"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:191
+msgid "Moving values between registers for state management:"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:199
+msgid ""
+"This \"register rotation\" is a fundamental technique in assembly "
+"programming."
+msgstr ""
+
+#: ../../examples/fibonacci.rst:204
+msgid "**Modify the counter**: Calculate F(15) instead of F(10)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:205
+msgid ""
+"**Different starting values**: Try F(0) = 1, F(1) = 1 (alternative "
+"definition)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:206
+msgid "**Store in memory**: Save each Fibonacci number to memory"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:207
+msgid "**Detect overflow**: Check when the result exceeds 255"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:210
+msgid "Solutions"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:212
+msgid "**F(15) modification**:"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:218
+msgid "Note: F(15) = 610, which exceeds 8-bit range (wraps to 98)."
+msgstr ""
+
+#: ../../examples/fibonacci.rst:220
+msgid "**Store in memory**:"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:234
+msgid ":doc:`factorial` - Another iterative calculation"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:235
+msgid ":doc:`sum_1_to_n` - Similar loop structure"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:236
+msgid ":doc:`power` - Repeated operation pattern"
+msgstr ""
+
+#: ../../examples/find_max.rst:2
+msgid "Find Maximum"
+msgstr ""
+
+#: ../../examples/find_max.rst:4
+msgid "Finds the maximum value in an array."
+msgstr ""
+
+#: ../../examples/find_max.rst:10
+msgid "Demonstrates comparison operations and conditional logic."
+msgstr ""
+
+#: ../../examples/gcd.rst:2
+msgid "GCD (Greatest Common Divisor)"
+msgstr ""
+
+#: ../../examples/gcd.rst:4
+msgid "Computes the GCD of two numbers using Euclidean algorithm."
+msgstr ""
+
+#: ../../examples/gcd.rst:10
+msgid ""
+"Demonstrates subtraction-based Euclidean algorithm and conditional "
+"comparison."
+msgstr ""
+
+#: ../../examples/hello_world.rst:2 ../../examples/index.rst:98
+msgid "Hello World"
+msgstr ""
+
+#: ../../examples/hello_world.rst:4
+msgid "A minimal Tiny8 program demonstrating basic structure."
+msgstr ""
+
+#: ../../examples/hello_world.rst:10
+msgid ""
+"This program demonstrates the simplest possible Tiny8 program structure "
+"with initialization and an infinite loop."
+msgstr ""
+
+#: ../../examples/index.rst:2
+msgid "Examples"
+msgstr ""
+
+#: ../../examples/index.rst:4
+msgid ""
+"This section contains detailed walkthroughs of example programs that "
+"demonstrate Tiny8's capabilities and teach assembly programming concepts."
+msgstr ""
+
+#: ../../examples/index.rst:9
+msgid "The examples are organized by complexity and concept:"
+msgstr ""
+
+#: ../../examples/index.rst:11
+msgid "**Basic Examples**"
+msgstr ""
+
+#: ../../examples/index.rst:12
+msgid "Simple programs demonstrating fundamental operations"
+msgstr ""
+
+#: ../../examples/index.rst:14
+msgid "**Intermediate Examples**"
+msgstr ""
+
+#: ../../examples/index.rst:15
+msgid "Programs using loops, conditionals, and memory operations"
+msgstr ""
+
+#: ../../examples/index.rst:17
+msgid "**Advanced Examples**"
+msgstr ""
+
+#: ../../examples/index.rst:18
+msgid "Complex algorithms including sorting and mathematical computations"
+msgstr ""
+
+#: ../../examples/index.rst:20
+msgid ""
+"All examples are available in the ``examples/`` directory of the Tiny8 "
+"repository."
+msgstr ""
+
+#: ../../examples/index.rst:23
+msgid "Running Examples"
+msgstr ""
+
+#: ../../examples/index.rst:25
+msgid "You can run any example with the interactive debugger:"
+msgstr ""
+
+#: ../../examples/index.rst:31
+msgid "Or use the Python API:"
+msgstr ""
+
+#: ../../examples/index.rst:42
+msgid "Example Programs"
+msgstr ""
+
+#: ../../examples/index.rst:45
+msgid "Basic Examples"
+msgstr ""
+
+#: ../../examples/index.rst:55
+msgid "Intermediate Examples"
+msgstr ""
+
+#: ../../examples/index.rst:67
+msgid "Advanced Examples"
+msgstr ""
+
+#: ../../examples/index.rst:81
+msgid "C Language Programs & Interactive Demos"
+msgstr ""
+
+#: ../../examples/index.rst:83
+msgid ""
+"Tiny8 includes an embedded C subset compiler capable of compiling and "
+"running C programs directly on the simulated CPU:"
+msgstr ""
+
+#: ../../examples/index.rst:85
+msgid "**factorial.c**: Recursive factorial calculation demonstration."
+msgstr ""
+
+#: ../../examples/index.rst:86
+msgid ""
+"**mnist_heatmap.c**: 28x28 MNIST real digit heatmap transfer to 32x32 "
+"VRAM."
+msgstr ""
+
+#: ../../examples/index.rst:89
+msgid "Quick Reference"
+msgstr ""
+
+#: ../../examples/index.rst:91
+msgid "Example Summary"
+msgstr ""
+
+#: ../../examples/index.rst:95
+msgid "Program"
+msgstr ""
+
+#: ../../examples/index.rst:96
+msgid "Concept"
+msgstr ""
+
+#: ../../examples/index.rst:97
+msgid "Key Instructions / Language"
+msgstr ""
+
+#: ../../examples/index.rst:99
+msgid "Basic memory writing"
+msgstr ""
+
+#: ../../examples/index.rst:100
+msgid "LDI, ST, INC, JMP"
+msgstr ""
+
+#: ../../examples/index.rst:101
+msgid "Fibonacci"
+msgstr ""
+
+#: ../../examples/index.rst:102
+msgid "Iterative sequence"
+msgstr ""
+
+#: ../../examples/index.rst:103
+msgid "ADD, MOV, DEC, BRNE"
+msgstr ""
+
+#: ../../examples/index.rst:104
+msgid "Factorial (ASM)"
+msgstr ""
+
+#: ../../examples/index.rst:105
+msgid "Iterative multiplication"
+msgstr ""
+
+#: ../../examples/index.rst:106
+msgid "MUL, DEC, CPI, BRGE"
+msgstr ""
+
+#: ../../examples/index.rst:107
+msgid "Factorial (C)"
+msgstr ""
+
+#: ../../examples/index.rst:108
+msgid "Recursive function calls"
+msgstr ""
+
+#: ../../examples/index.rst:109
+msgid "C Compiler (CALL, RET, PUSH, POP)"
+msgstr ""
+
+#: ../../examples/index.rst:110 ../../examples/sum_1_to_n.rst:2
+msgid "Sum 1 to N"
+msgstr ""
+
+#: ../../examples/index.rst:111
+msgid "Loop accumulation"
+msgstr ""
+
+#: ../../examples/index.rst:112
+msgid "ADD, INC, CP, BRLT, BREQ"
+msgstr ""
+
+#: ../../examples/index.rst:114
+msgid "Pointer iteration"
+msgstr ""
+
+#: ../../examples/index.rst:115
+msgid "LD, ST, ADD, INC, BRNE"
+msgstr ""
+
+#: ../../examples/index.rst:116
+msgid "Find Max"
+msgstr ""
+
+#: ../../examples/index.rst:117
+msgid "Array scanning & comparison"
+msgstr ""
+
+#: ../../examples/index.rst:118
+msgid "LD, ST, CP, BRGE, MOV"
+msgstr ""
+
+#: ../../examples/index.rst:119 ../../examples/linear_search.rst:2
+msgid "Linear Search"
+msgstr ""
+
+#: ../../examples/index.rst:120
+msgid "Target search & sentinel"
+msgstr ""
+
+#: ../../examples/index.rst:121
+msgid "LD, ST, CP, BREQ, INC"
+msgstr ""
+
+#: ../../examples/index.rst:122 ../../examples/memory_copy.rst:2
+msgid "Memory Copy"
+msgstr ""
+
+#: ../../examples/index.rst:123
+msgid "Block memory transfer"
+msgstr ""
+
+#: ../../examples/index.rst:124
+msgid "LD, ST, INC, DEC, BRNE"
+msgstr ""
+
+#: ../../examples/index.rst:126
+msgid "PRNG & in-place sort"
+msgstr ""
+
+#: ../../examples/index.rst:127
+msgid "MUL, LD, ST, CP, BRCS"
+msgstr ""
+
+#: ../../examples/index.rst:128
+msgid "GCD"
+msgstr ""
+
+#: ../../examples/index.rst:129
+msgid "Euclidean algorithm"
+msgstr ""
+
+#: ../../examples/index.rst:130
+msgid "DIV, MOV, CPI, BREQ"
+msgstr ""
+
+#: ../../examples/index.rst:131
+msgid "Power"
+msgstr ""
+
+#: ../../examples/index.rst:132
+msgid "Exponentiation"
+msgstr ""
+
+#: ../../examples/index.rst:133
+msgid "MUL, INC, CP, BRLT"
+msgstr ""
+
+#: ../../examples/index.rst:134 ../../examples/multiply_by_shift.rst:2
+msgid "Multiply by Shift"
+msgstr ""
+
+#: ../../examples/index.rst:135
+msgid "Binary shift multiplication"
+msgstr ""
+
+#: ../../examples/index.rst:136
+msgid "LSL, LSR, ANDI, ADD"
+msgstr ""
+
+#: ../../examples/index.rst:138
+msgid "Bit testing & division"
+msgstr ""
+
+#: ../../examples/index.rst:139
+msgid "AND, DIV, CPI, BRNE"
+msgstr ""
+
+#: ../../examples/index.rst:140 ../../examples/is_prime.rst:2
+msgid "Is Prime"
+msgstr ""
+
+#: ../../examples/index.rst:141
+msgid "Trial division"
+msgstr ""
+
+#: ../../examples/index.rst:142
+msgid "DIV, MUL, CP, BRGE, BRLT"
+msgstr ""
+
+#: ../../examples/index.rst:143 ../../examples/reverse.rst:2
+msgid "Reverse Array"
+msgstr ""
+
+#: ../../examples/index.rst:144
+msgid "Two-pointer array reverse"
+msgstr ""
+
+#: ../../examples/index.rst:145
+msgid "LD, ST, CP, BRGE, INC, DEC"
+msgstr ""
+
+#: ../../examples/index.rst:146
+msgid "MNIST Heatmap (C)"
+msgstr ""
+
+#: ../../examples/index.rst:147
+msgid "28x28 digit VRAM heatmap"
+msgstr ""
+
+#: ../../examples/index.rst:148
+msgid "C (VRAM 0x0200..0x05FF)"
+msgstr ""
+
+#: ../../examples/index.rst:149
+msgid "MNIST Diffusion (ASM)"
+msgstr ""
+
+#: ../../examples/index.rst:150
+msgid "Iterative reverse-diffusion synthesis"
+msgstr ""
+
+#: ../../examples/index.rst:151
+msgid "ASM (diffusion_mnist8.asm)"
+msgstr ""
+
+#: ../../examples/index.rst:154
+msgid "Learning Path"
+msgstr ""
+
+#: ../../examples/index.rst:156
+msgid "Recommended order for learning:"
+msgstr ""
+
+#: ../../examples/index.rst:158
+msgid "**Start with basics**: hello_world, fibonacci, factorial"
+msgstr ""
+
+#: ../../examples/index.rst:159
+msgid "**Learn memory**: array_sum, memory_copy, find_max"
+msgstr ""
+
+#: ../../examples/index.rst:160
+msgid "**Master control flow**: linear_search, gcd"
+msgstr ""
+
+#: ../../examples/index.rst:161
+msgid "**Tackle algorithms**: bubblesort, power, is_prime"
+msgstr ""
+
+#: ../../examples/index.rst:162
+msgid "**Explore bit operations**: multiply_by_shift, count_bits"
+msgstr ""
+
+#: ../../examples/is_prime.rst:4
+msgid "Tests whether a number is prime."
+msgstr ""
+
+#: ../../examples/is_prime.rst:10
+msgid "Demonstrates trial division and number theory concepts."
+msgstr ""
+
+#: ../../examples/linear_search.rst:4
+msgid "Searches for a value in an array."
+msgstr ""
+
+#: ../../examples/linear_search.rst:10
+msgid "Demonstrates sequential search and early loop exit."
+msgstr ""
+
+#: ../../examples/memory_copy.rst:4
+msgid "Copies data from one memory location to another."
+msgstr ""
+
+#: ../../examples/memory_copy.rst:10
+msgid "Demonstrates memory-to-memory data transfer."
+msgstr ""
+
+#: ../../examples/multiply_by_shift.rst:4
+msgid "Multiplies numbers using bit shifting instead of MUL instruction."
+msgstr ""
+
+#: ../../examples/multiply_by_shift.rst:10
+msgid "Demonstrates bit manipulation and efficient multiplication."
+msgstr ""
+
+#: ../../examples/power.rst:2
+msgid "Power Function"
+msgstr ""
+
+#: ../../examples/power.rst:4
+msgid "Computes x^n using repeated multiplication."
+msgstr ""
+
+#: ../../examples/power.rst:10
+msgid "Demonstrates exponentiation through iteration."
+msgstr ""
+
+#: ../../examples/reverse.rst:4
+msgid "Reverses an array in place."
+msgstr ""
+
+#: ../../examples/reverse.rst:10
+msgid "Demonstrates two-pointer technique and array manipulation."
+msgstr ""
+
+#: ../../examples/sum_1_to_n.rst:4
+msgid "Calculates the sum of integers from 1 to N."
+msgstr ""
+
+#: ../../examples/sum_1_to_n.rst:10
+msgid "Demonstrates accumulation pattern and loop control."
+msgstr ""
+
diff --git a/docs/locales/ja/LC_MESSAGES/examples/array_sum.po b/docs/locales/ja/LC_MESSAGES/examples/array_sum.po
new file mode 100644
index 0000000..a53f027
--- /dev/null
+++ b/docs/locales/ja/LC_MESSAGES/examples/array_sum.po
@@ -0,0 +1,33 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, 2026.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:30+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language: ja\n"
+"Language-Team: ja <LL@li.org>\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=utf-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Generated-By: Babel 2.17.0\n"
+
+#: ../../examples/array_sum.rst:2
+msgid "Array Sum"
+msgstr ""
+
+#: ../../examples/array_sum.rst:4
+msgid "Sums elements of an array stored in memory."
+msgstr ""
+
+#: ../../examples/array_sum.rst:10
+msgid "Demonstrates memory access and array processing."
+msgstr ""
+
diff --git a/docs/locales/ja/LC_MESSAGES/examples/bubblesort.po b/docs/locales/ja/LC_MESSAGES/examples/bubblesort.po
new file mode 100644
index 0000000..be5804e
--- /dev/null
+++ b/docs/locales/ja/LC_MESSAGES/examples/bubblesort.po
@@ -0,0 +1,537 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, 2026.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:30+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language: ja\n"
+"Language-Team: ja <LL@li.org>\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=utf-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Generated-By: Babel 2.17.0\n"
+
+#: ../../examples/bubblesort.rst:2 ../../examples/bubblesort.rst:351
+msgid "Bubble Sort"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:4
+msgid ""
+"This advanced example demonstrates bubble sort: a classic sorting "
+"algorithm that sorts an array in memory."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:7
+msgid "Overview"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:9
+msgid "**Difficulty**: Advanced"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:11
+msgid ""
+"**Concepts**: Nested loops, memory operations, array manipulation, "
+"pseudo-random number generation"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:13
+msgid "**Output**: Sorted array at RAM[0x60..0x7F] (32 bytes in ascending order)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:16
+msgid "The Program"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:23
+msgid "Algorithm Overview"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:25
+msgid "The program has two main phases:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:27
+msgid "**Initialization**: Generate 32 pseudo-random values and store them in RAM"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:28
+msgid "**Bubble Sort**: Sort the array using the bubble sort algorithm"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:31
+msgid "Phase 1: Array Initialization"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:34
+msgid "Pseudo-Random Number Generator"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:36
+msgid "The program uses a simple linear congruential generator (LCG):"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:42
+msgid "This generates a sequence of pseudo-random 8-bit values."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:56
+msgid "After 32 iterations, RAM[0x60..0x7F] contains pseudo-random values."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:59
+msgid "Phase 2: Bubble Sort"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:62
+msgid "Algorithm Explanation"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:64
+msgid ""
+"Bubble sort works by repeatedly stepping through the array, comparing "
+"adjacent elements, and swapping them if they're in the wrong order."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:74
+msgid "Outer Loop"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:87
+msgid "Runs 31 times (i = 0 to 30)."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:90
+msgid "Inner Loop"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:119
+msgid "For each j:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:121
+msgid "Load adjacent elements (j and j+1)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:122
+msgid "Compare them"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:123
+msgid "Swap if first > second (for ascending order)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:124
+msgid "Advance to next pair"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:127
+msgid "Register Usage"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:129
+msgid "Register Allocation"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:133
+msgid "Register"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:134
+msgid "Purpose"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:135
+msgid "R16"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:136
+msgid "Memory address pointer / base address"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:137
+msgid "R17"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:138
+msgid "Array index during initialization"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:139
+msgid "R18"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:140
+msgid "PRNG seed / outer loop counter (i)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:141
+msgid "R19"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:142
+msgid "Inner loop counter (j)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:143
+msgid "R20"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:144
+msgid "Address of element A"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:145
+msgid "R21"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:146
+msgid "Value of element A"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:147
+msgid "R22"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:148
+msgid "Address of element B"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:149
+msgid "R23"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:150
+msgid "Temporary comparison value"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:151
+msgid "R24"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:152
+msgid "Value of element B"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:153
+msgid "R25"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:154
+msgid "PRNG multiplier constant (75)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:157
+msgid "Memory Layout"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:174
+msgid "Execution Example"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:177
+msgid "Initial Array (pseudo-random)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:184
+msgid "After Bubble Sort"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:190
+msgid ""
+"Bubble sort compares and swaps adjacent elements until the entire array "
+"is sorted."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:193
+msgid "Running the Example"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:196
+msgid "Interactive Debugger"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:202
+msgid ""
+"Watch the sorting process step-by-step. Set marks at the beginning of "
+"inner_loop to track passes."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:205
+msgid "Animation"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:212
+msgid "Creates a visualization showing:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:214
+msgid "Memory heatmap of the array being sorted"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:215
+msgid "Register changes during comparisons"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:216
+msgid "Visual pattern of values moving to their correct positions"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:219
+msgid "Python API"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:239
+msgid "Performance Analysis"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:242 ../../examples/bubblesort.rst:348
+msgid "Time Complexity"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:244
+msgid "**Best case**: O(n²) - 31 × 31 = 961 comparisons"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:245
+msgid ""
+"**Worst case**: O(n²) - Same as best (this implementation doesn't "
+"optimize)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:246
+msgid "**Average case**: O(n²)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:248
+msgid "For 32 elements:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:250
+msgid "Outer loop: 31 iterations"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:251
+msgid "Inner loop: 31 iterations per outer"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:252
+msgid "Total comparisons: ~961"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:253
+msgid "Total swaps: Variable (depends on initial order)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:256
+msgid "Instruction Count"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:258
+msgid "Each comparison involves approximately:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:260
+msgid "10 instructions to load addresses and values"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:261
+msgid "5 instructions for comparison and potential swap"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:262
+msgid "3 instructions for loop control"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:264
+msgid "Total: ~15,000+ instructions for a complete sort."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:267
+msgid "Key Concepts"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:270
+msgid "Nested Loops"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:272
+msgid "Two loop counters working together:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:286
+msgid "Address Calculation"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:288
+msgid "Computing memory addresses dynamically:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:297
+msgid "Conditional Swapping"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:308
+msgid "Exercises"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:310
+msgid "**Count swaps**: Add a counter to track number of swaps"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:311
+msgid "**Optimize**: Add early exit if no swaps occurred in a pass"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:312
+msgid "**Different sizes**: Sort 16 or 64 elements instead"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:313
+msgid "**Descending order**: Modify to sort in descending order"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:314
+msgid "**Different algorithm**: Implement selection sort or insertion sort"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:317
+msgid "Solutions Hints"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:319
+msgid "**Count swaps**: Add ``inc r26`` in the swap section, initialize R26 to 0."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:321
+msgid "**Optimize**: Set a flag when swapping, check it at end of outer loop."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:323
+msgid "**Descending order**: Change ``brcs no_swap`` to ``brcc no_swap``."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:326
+msgid "Visualization Tips"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:328
+msgid "When viewing the animation:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:330
+msgid "**Memory panel**: Watch values \"bubble\" to their positions"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:331
+msgid "**Register panel**: R19 (j) cycles 0-30 repeatedly"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:332
+msgid "**Register panel**: R18 (i) increments slowly"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:334
+msgid "Look for:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:336
+msgid "Large values moving right (higher addresses)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:337
+msgid "Small values moving left (lower addresses)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:338
+msgid "Progressively fewer changes as array becomes sorted"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:341
+msgid "Comparison with Other Sorts"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:343
+msgid "Sorting Algorithm Comparison"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:347
+msgid "Algorithm"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:349
+msgid "Space"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:350
+msgid "Stability"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:352 ../../examples/bubblesort.rst:356
+#: ../../examples/bubblesort.rst:360
+msgid "O(n²)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:353 ../../examples/bubblesort.rst:357
+#: ../../examples/bubblesort.rst:361
+msgid "O(1)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:354 ../../examples/bubblesort.rst:362
+msgid "Yes"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:355
+msgid "Selection Sort"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:358 ../../examples/bubblesort.rst:366
+msgid "No"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:359
+msgid "Insertion Sort"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:363
+msgid "Quick Sort"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:364
+msgid "O(n log n)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:365
+msgid "O(log n)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:368
+msgid ""
+"Bubble sort is chosen for this example because it's conceptually simple "
+"and demonstrates memory operations clearly."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:371
+msgid "Related Examples"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:373
+msgid ":doc:`linear_search` - Sequential array access"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:374
+msgid ":doc:`find_max` - Array comparison operations"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:375
+msgid ":doc:`reverse` - Array manipulation"
+msgstr ""
+
diff --git a/docs/locales/ja/LC_MESSAGES/examples/count_bits.po b/docs/locales/ja/LC_MESSAGES/examples/count_bits.po
new file mode 100644
index 0000000..0f23de7
--- /dev/null
+++ b/docs/locales/ja/LC_MESSAGES/examples/count_bits.po
@@ -0,0 +1,33 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, 2026.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:30+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language: ja\n"
+"Language-Team: ja <LL@li.org>\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=utf-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Generated-By: Babel 2.17.0\n"
+
+#: ../../examples/count_bits.rst:2
+msgid "Count Bits"
+msgstr ""
+
+#: ../../examples/count_bits.rst:4
+msgid "Counts the number of set bits (1s) in a value."
+msgstr ""
+
+#: ../../examples/count_bits.rst:10
+msgid "Demonstrates bit manipulation and counting operations."
+msgstr ""
+
diff --git a/docs/locales/ja/LC_MESSAGES/examples/factorial.po b/docs/locales/ja/LC_MESSAGES/examples/factorial.po
new file mode 100644
index 0000000..922b900
--- /dev/null
+++ b/docs/locales/ja/LC_MESSAGES/examples/factorial.po
@@ -0,0 +1,35 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, 2026.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:30+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language: ja\n"
+"Language-Team: ja <LL@li.org>\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=utf-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Generated-By: Babel 2.17.0\n"
+
+#: ../../examples/factorial.rst:2
+msgid "Factorial"
+msgstr ""
+
+#: ../../examples/factorial.rst:4
+msgid "Computes factorial of a number using iterative multiplication."
+msgstr ""
+
+#: ../../examples/factorial.rst:10
+msgid ""
+"Calculates 5! = 120 using repeated multiplication and demonstrates loop "
+"control."
+msgstr ""
+
diff --git a/docs/locales/ja/LC_MESSAGES/examples/fibonacci.po b/docs/locales/ja/LC_MESSAGES/examples/fibonacci.po
new file mode 100644
index 0000000..7d43a75
--- /dev/null
+++ b/docs/locales/ja/LC_MESSAGES/examples/fibonacci.po
@@ -0,0 +1,375 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, 2026.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:30+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language: ja\n"
+"Language-Team: ja <LL@li.org>\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=utf-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Generated-By: Babel 2.17.0\n"
+
+#: ../../examples/fibonacci.rst:2
+msgid "Fibonacci Sequence"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:4
+msgid ""
+"This example calculates the 10th Fibonacci number using an iterative "
+"approach."
+msgstr ""
+
+#: ../../examples/fibonacci.rst:7
+msgid "Overview"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:9
+msgid "**Difficulty**: Beginner"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:11
+msgid "**Concepts**: Loops, register arithmetic, conditional branching"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:13
+msgid "**Output**: R17 contains F(10) = 55"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:16
+msgid "The Program"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:23
+msgid "Algorithm Explanation"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:25
+msgid "The Fibonacci sequence is defined as:"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:27
+msgid "F(0) = 0"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:28
+msgid "F(1) = 1"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:29
+msgid "F(n) = F(n-1) + F(n-2) for n > 1"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:31
+msgid "This program uses an iterative approach with three registers:"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:33
+msgid "**R16**: Previous Fibonacci number (F(n-1))"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:34
+msgid "**R17**: Current Fibonacci number (F(n))"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:35
+msgid "**R18**: Counter (remaining iterations)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:38
+msgid "Step-by-Step Walkthrough"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:41
+msgid "Initialization (Lines 8-10)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:49
+msgid ""
+"We start with F(0) = 0 and F(1) = 1. Since we want F(10), we need 9 more "
+"iterations (F(2) through F(10))."
+msgstr ""
+
+#: ../../examples/fibonacci.rst:52
+msgid "Main Loop (Lines 12-18)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:64
+msgid "Each iteration:"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:66
+msgid "**Add**: Compute next Fibonacci number (R16 + R17)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:67
+msgid "**Save**: Store result in temporary register R19"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:68
+msgid "**Shift**: Move R17 to R16 (previous ← current)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:69
+msgid "**Update**: Move R19 to R17 (current ← new result)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:70
+msgid "**Decrement**: Decrease counter"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:71
+msgid "**Branch**: Loop if counter ≠ 0"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:74
+msgid "Execution Trace"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:76
+msgid "Here's how the registers evolve:"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:78
+msgid "Fibonacci Calculation"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:82
+msgid "Iter"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:83
+msgid "R16 (prev)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:84
+msgid "R17 (curr)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:85
+msgid "R18 (count)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:86
+msgid "Calculation"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:87
+msgid "Init"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:88 ../../examples/fibonacci.rst:135
+msgid "0"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:89 ../../examples/fibonacci.rst:92
+#: ../../examples/fibonacci.rst:93 ../../examples/fibonacci.rst:94
+#: ../../examples/fibonacci.rst:98 ../../examples/fibonacci.rst:130
+msgid "1"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:90 ../../examples/fibonacci.rst:132
+msgid "9"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:91
+msgid "F(0), F(1)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:95 ../../examples/fibonacci.rst:114
+#: ../../examples/fibonacci.rst:118 ../../examples/fibonacci.rst:127
+msgid "8"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:96
+msgid "F(2) = 0 + 1 = 1"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:97 ../../examples/fibonacci.rst:99
+#: ../../examples/fibonacci.rst:103 ../../examples/fibonacci.rst:125
+msgid "2"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:100 ../../examples/fibonacci.rst:122
+msgid "7"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:101
+msgid "F(3) = 1 + 1 = 2"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:102 ../../examples/fibonacci.rst:104
+#: ../../examples/fibonacci.rst:108 ../../examples/fibonacci.rst:120
+msgid "3"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:105 ../../examples/fibonacci.rst:117
+msgid "6"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:106
+msgid "F(4) = 1 + 2 = 3"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:107 ../../examples/fibonacci.rst:115
+msgid "4"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:109 ../../examples/fibonacci.rst:110
+#: ../../examples/fibonacci.rst:112 ../../examples/fibonacci.rst:113
+msgid "5"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:111
+msgid "F(5) = 2 + 3 = 5"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:116
+msgid "F(6) = 3 + 5 = 8"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:119 ../../examples/fibonacci.rst:123
+msgid "13"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:121
+msgid "F(7) = 5 + 8 = 13"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:124 ../../examples/fibonacci.rst:128
+msgid "21"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:126
+msgid "F(8) = 8 + 13 = 21"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:129 ../../examples/fibonacci.rst:133
+msgid "34"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:131
+msgid "F(9) = 13 + 21 = 34"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:134
+msgid "55"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:136
+msgid "F(10) = 21 + 34 = 55"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:139
+msgid "Running the Example"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:142
+msgid "Interactive Debugger"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:148
+msgid "Step through with ``j`` and watch registers R16, R17, and R18 evolve."
+msgstr ""
+
+#: ../../examples/fibonacci.rst:151
+msgid "Animation"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:157
+msgid "Visualize the register changes over time."
+msgstr ""
+
+#: ../../examples/fibonacci.rst:160
+msgid "Python API"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:173
+msgid "Key Concepts"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:176
+msgid "Loop Structure"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:178
+msgid "The loop pattern is common in assembly:"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:189
+msgid "Register Shifting"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:191
+msgid "Moving values between registers for state management:"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:199
+msgid ""
+"This \"register rotation\" is a fundamental technique in assembly "
+"programming."
+msgstr ""
+
+#: ../../examples/fibonacci.rst:202
+msgid "Exercises"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:204
+msgid "**Modify the counter**: Calculate F(15) instead of F(10)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:205
+msgid ""
+"**Different starting values**: Try F(0) = 1, F(1) = 1 (alternative "
+"definition)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:206
+msgid "**Store in memory**: Save each Fibonacci number to memory"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:207
+msgid "**Detect overflow**: Check when the result exceeds 255"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:210
+msgid "Solutions"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:212
+msgid "**F(15) modification**:"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:218
+msgid "Note: F(15) = 610, which exceeds 8-bit range (wraps to 98)."
+msgstr ""
+
+#: ../../examples/fibonacci.rst:220
+msgid "**Store in memory**:"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:232
+msgid "Related Examples"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:234
+msgid ":doc:`factorial` - Another iterative calculation"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:235
+msgid ":doc:`sum_1_to_n` - Similar loop structure"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:236
+msgid ":doc:`power` - Repeated operation pattern"
+msgstr ""
+
diff --git a/docs/locales/ja/LC_MESSAGES/examples/find_max.po b/docs/locales/ja/LC_MESSAGES/examples/find_max.po
new file mode 100644
index 0000000..64bd8a7
--- /dev/null
+++ b/docs/locales/ja/LC_MESSAGES/examples/find_max.po
@@ -0,0 +1,33 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, 2026.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:30+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language: ja\n"
+"Language-Team: ja <LL@li.org>\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=utf-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Generated-By: Babel 2.17.0\n"
+
+#: ../../examples/find_max.rst:2
+msgid "Find Maximum"
+msgstr ""
+
+#: ../../examples/find_max.rst:4
+msgid "Finds the maximum value in an array."
+msgstr ""
+
+#: ../../examples/find_max.rst:10
+msgid "Demonstrates comparison operations and conditional logic."
+msgstr ""
+
diff --git a/docs/locales/ja/LC_MESSAGES/examples/gcd.po b/docs/locales/ja/LC_MESSAGES/examples/gcd.po
new file mode 100644
index 0000000..aabbd77
--- /dev/null
+++ b/docs/locales/ja/LC_MESSAGES/examples/gcd.po
@@ -0,0 +1,35 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, 2026.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:30+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language: ja\n"
+"Language-Team: ja <LL@li.org>\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=utf-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Generated-By: Babel 2.17.0\n"
+
+#: ../../examples/gcd.rst:2
+msgid "GCD (Greatest Common Divisor)"
+msgstr ""
+
+#: ../../examples/gcd.rst:4
+msgid "Computes the GCD of two numbers using Euclidean algorithm."
+msgstr ""
+
+#: ../../examples/gcd.rst:10
+msgid ""
+"Demonstrates subtraction-based Euclidean algorithm and conditional "
+"comparison."
+msgstr ""
+
diff --git a/docs/locales/ja/LC_MESSAGES/examples/hello_world.po b/docs/locales/ja/LC_MESSAGES/examples/hello_world.po
new file mode 100644
index 0000000..e00b6c0
--- /dev/null
+++ b/docs/locales/ja/LC_MESSAGES/examples/hello_world.po
@@ -0,0 +1,35 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, 2026.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:30+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language: ja\n"
+"Language-Team: ja <LL@li.org>\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=utf-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Generated-By: Babel 2.17.0\n"
+
+#: ../../examples/hello_world.rst:2
+msgid "Hello World"
+msgstr ""
+
+#: ../../examples/hello_world.rst:4
+msgid "A minimal Tiny8 program demonstrating basic structure."
+msgstr ""
+
+#: ../../examples/hello_world.rst:10
+msgid ""
+"This program demonstrates the simplest possible Tiny8 program structure "
+"with initialization and an infinite loop."
+msgstr ""
+
diff --git a/docs/locales/ja/LC_MESSAGES/examples/index.po b/docs/locales/ja/LC_MESSAGES/examples/index.po
new file mode 100644
index 0000000..8c11c4e
--- /dev/null
+++ b/docs/locales/ja/LC_MESSAGES/examples/index.po
@@ -0,0 +1,381 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, 2026.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:30+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language: ja\n"
+"Language-Team: ja <LL@li.org>\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=utf-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Generated-By: Babel 2.17.0\n"
+
+#: ../../examples/index.rst:2
+msgid "Examples"
+msgstr ""
+
+#: ../../examples/index.rst:4
+msgid ""
+"This section contains detailed walkthroughs of example programs that "
+"demonstrate Tiny8's capabilities and teach assembly programming concepts."
+msgstr ""
+
+#: ../../examples/index.rst:7
+msgid "Overview"
+msgstr ""
+
+#: ../../examples/index.rst:9
+msgid "The examples are organized by complexity and concept:"
+msgstr ""
+
+#: ../../examples/index.rst:11
+msgid "**Basic Examples**"
+msgstr ""
+
+#: ../../examples/index.rst:12
+msgid "Simple programs demonstrating fundamental operations"
+msgstr ""
+
+#: ../../examples/index.rst:14
+msgid "**Intermediate Examples**"
+msgstr ""
+
+#: ../../examples/index.rst:15
+msgid "Programs using loops, conditionals, and memory operations"
+msgstr ""
+
+#: ../../examples/index.rst:17
+msgid "**Advanced Examples**"
+msgstr ""
+
+#: ../../examples/index.rst:18
+msgid "Complex algorithms including sorting and mathematical computations"
+msgstr ""
+
+#: ../../examples/index.rst:20
+msgid ""
+"All examples are available in the ``examples/`` directory of the Tiny8 "
+"repository."
+msgstr ""
+
+#: ../../examples/index.rst:23
+msgid "Running Examples"
+msgstr ""
+
+#: ../../examples/index.rst:25
+msgid "You can run any example with the interactive debugger:"
+msgstr ""
+
+#: ../../examples/index.rst:31
+msgid "Or use the Python API:"
+msgstr ""
+
+#: ../../examples/index.rst:42
+msgid "Example Programs"
+msgstr ""
+
+#: ../../examples/index.rst:45
+msgid "Basic Examples"
+msgstr ""
+
+#: ../../examples/index.rst:55
+msgid "Intermediate Examples"
+msgstr ""
+
+#: ../../examples/index.rst:67
+msgid "Advanced Examples"
+msgstr ""
+
+#: ../../examples/index.rst:81
+msgid "C Language Programs & Interactive Demos"
+msgstr ""
+
+#: ../../examples/index.rst:83
+msgid ""
+"Tiny8 includes an embedded C subset compiler capable of compiling and "
+"running C programs directly on the simulated CPU:"
+msgstr ""
+
+#: ../../examples/index.rst:85
+msgid "**factorial.c**: Recursive factorial calculation demonstration."
+msgstr ""
+
+#: ../../examples/index.rst:86
+msgid ""
+"**mnist_heatmap.c**: 28x28 MNIST real digit heatmap transfer to 32x32 "
+"VRAM."
+msgstr ""
+
+#: ../../examples/index.rst:89
+msgid "Quick Reference"
+msgstr ""
+
+#: ../../examples/index.rst:91
+msgid "Example Summary"
+msgstr ""
+
+#: ../../examples/index.rst:95
+msgid "Program"
+msgstr ""
+
+#: ../../examples/index.rst:96
+msgid "Concept"
+msgstr ""
+
+#: ../../examples/index.rst:97
+msgid "Key Instructions / Language"
+msgstr ""
+
+#: ../../examples/index.rst:98
+msgid "Hello World"
+msgstr ""
+
+#: ../../examples/index.rst:99
+msgid "Basic memory writing"
+msgstr ""
+
+#: ../../examples/index.rst:100
+msgid "LDI, ST, INC, JMP"
+msgstr ""
+
+#: ../../examples/index.rst:101
+msgid "Fibonacci"
+msgstr ""
+
+#: ../../examples/index.rst:102
+msgid "Iterative sequence"
+msgstr ""
+
+#: ../../examples/index.rst:103
+msgid "ADD, MOV, DEC, BRNE"
+msgstr ""
+
+#: ../../examples/index.rst:104
+msgid "Factorial (ASM)"
+msgstr ""
+
+#: ../../examples/index.rst:105
+msgid "Iterative multiplication"
+msgstr ""
+
+#: ../../examples/index.rst:106
+msgid "MUL, DEC, CPI, BRGE"
+msgstr ""
+
+#: ../../examples/index.rst:107
+msgid "Factorial (C)"
+msgstr ""
+
+#: ../../examples/index.rst:108
+msgid "Recursive function calls"
+msgstr ""
+
+#: ../../examples/index.rst:109
+msgid "C Compiler (CALL, RET, PUSH, POP)"
+msgstr ""
+
+#: ../../examples/index.rst:110
+msgid "Sum 1 to N"
+msgstr ""
+
+#: ../../examples/index.rst:111
+msgid "Loop accumulation"
+msgstr ""
+
+#: ../../examples/index.rst:112
+msgid "ADD, INC, CP, BRLT, BREQ"
+msgstr ""
+
+#: ../../examples/index.rst:113
+msgid "Array Sum"
+msgstr ""
+
+#: ../../examples/index.rst:114
+msgid "Pointer iteration"
+msgstr ""
+
+#: ../../examples/index.rst:115
+msgid "LD, ST, ADD, INC, BRNE"
+msgstr ""
+
+#: ../../examples/index.rst:116
+msgid "Find Max"
+msgstr ""
+
+#: ../../examples/index.rst:117
+msgid "Array scanning & comparison"
+msgstr ""
+
+#: ../../examples/index.rst:118
+msgid "LD, ST, CP, BRGE, MOV"
+msgstr ""
+
+#: ../../examples/index.rst:119
+msgid "Linear Search"
+msgstr ""
+
+#: ../../examples/index.rst:120
+msgid "Target search & sentinel"
+msgstr ""
+
+#: ../../examples/index.rst:121
+msgid "LD, ST, CP, BREQ, INC"
+msgstr ""
+
+#: ../../examples/index.rst:122
+msgid "Memory Copy"
+msgstr ""
+
+#: ../../examples/index.rst:123
+msgid "Block memory transfer"
+msgstr ""
+
+#: ../../examples/index.rst:124
+msgid "LD, ST, INC, DEC, BRNE"
+msgstr ""
+
+#: ../../examples/index.rst:125
+msgid "Bubble Sort"
+msgstr ""
+
+#: ../../examples/index.rst:126
+msgid "PRNG & in-place sort"
+msgstr ""
+
+#: ../../examples/index.rst:127
+msgid "MUL, LD, ST, CP, BRCS"
+msgstr ""
+
+#: ../../examples/index.rst:128
+msgid "GCD"
+msgstr ""
+
+#: ../../examples/index.rst:129
+msgid "Euclidean algorithm"
+msgstr ""
+
+#: ../../examples/index.rst:130
+msgid "DIV, MOV, CPI, BREQ"
+msgstr ""
+
+#: ../../examples/index.rst:131
+msgid "Power"
+msgstr ""
+
+#: ../../examples/index.rst:132
+msgid "Exponentiation"
+msgstr ""
+
+#: ../../examples/index.rst:133
+msgid "MUL, INC, CP, BRLT"
+msgstr ""
+
+#: ../../examples/index.rst:134
+msgid "Multiply by Shift"
+msgstr ""
+
+#: ../../examples/index.rst:135
+msgid "Binary shift multiplication"
+msgstr ""
+
+#: ../../examples/index.rst:136
+msgid "LSL, LSR, ANDI, ADD"
+msgstr ""
+
+#: ../../examples/index.rst:137
+msgid "Count Bits"
+msgstr ""
+
+#: ../../examples/index.rst:138
+msgid "Bit testing & division"
+msgstr ""
+
+#: ../../examples/index.rst:139
+msgid "AND, DIV, CPI, BRNE"
+msgstr ""
+
+#: ../../examples/index.rst:140
+msgid "Is Prime"
+msgstr ""
+
+#: ../../examples/index.rst:141
+msgid "Trial division"
+msgstr ""
+
+#: ../../examples/index.rst:142
+msgid "DIV, MUL, CP, BRGE, BRLT"
+msgstr ""
+
+#: ../../examples/index.rst:143
+msgid "Reverse Array"
+msgstr ""
+
+#: ../../examples/index.rst:144
+msgid "Two-pointer array reverse"
+msgstr ""
+
+#: ../../examples/index.rst:145
+msgid "LD, ST, CP, BRGE, INC, DEC"
+msgstr ""
+
+#: ../../examples/index.rst:146
+msgid "MNIST Heatmap (C)"
+msgstr ""
+
+#: ../../examples/index.rst:147
+msgid "28x28 digit VRAM heatmap"
+msgstr ""
+
+#: ../../examples/index.rst:148
+msgid "C (VRAM 0x0200..0x05FF)"
+msgstr ""
+
+#: ../../examples/index.rst:149
+msgid "MNIST Diffusion (ASM)"
+msgstr ""
+
+#: ../../examples/index.rst:150
+msgid "Iterative reverse-diffusion synthesis"
+msgstr ""
+
+#: ../../examples/index.rst:151
+msgid "ASM (diffusion_mnist8.asm)"
+msgstr ""
+
+#: ../../examples/index.rst:154
+msgid "Learning Path"
+msgstr ""
+
+#: ../../examples/index.rst:156
+msgid "Recommended order for learning:"
+msgstr ""
+
+#: ../../examples/index.rst:158
+msgid "**Start with basics**: hello_world, fibonacci, factorial"
+msgstr ""
+
+#: ../../examples/index.rst:159
+msgid "**Learn memory**: array_sum, memory_copy, find_max"
+msgstr ""
+
+#: ../../examples/index.rst:160
+msgid "**Master control flow**: linear_search, gcd"
+msgstr ""
+
+#: ../../examples/index.rst:161
+msgid "**Tackle algorithms**: bubblesort, power, is_prime"
+msgstr ""
+
+#: ../../examples/index.rst:162
+msgid "**Explore bit operations**: multiply_by_shift, count_bits"
+msgstr ""
+
diff --git a/docs/locales/ja/LC_MESSAGES/examples/is_prime.po b/docs/locales/ja/LC_MESSAGES/examples/is_prime.po
new file mode 100644
index 0000000..3627d10
--- /dev/null
+++ b/docs/locales/ja/LC_MESSAGES/examples/is_prime.po
@@ -0,0 +1,33 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, 2026.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:30+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language: ja\n"
+"Language-Team: ja <LL@li.org>\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=utf-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Generated-By: Babel 2.17.0\n"
+
+#: ../../examples/is_prime.rst:2
+msgid "Is Prime"
+msgstr ""
+
+#: ../../examples/is_prime.rst:4
+msgid "Tests whether a number is prime."
+msgstr ""
+
+#: ../../examples/is_prime.rst:10
+msgid "Demonstrates trial division and number theory concepts."
+msgstr ""
+
diff --git a/docs/locales/ja/LC_MESSAGES/examples/linear_search.po b/docs/locales/ja/LC_MESSAGES/examples/linear_search.po
new file mode 100644
index 0000000..e7d2822
--- /dev/null
+++ b/docs/locales/ja/LC_MESSAGES/examples/linear_search.po
@@ -0,0 +1,33 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, 2026.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:30+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language: ja\n"
+"Language-Team: ja <LL@li.org>\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=utf-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Generated-By: Babel 2.17.0\n"
+
+#: ../../examples/linear_search.rst:2
+msgid "Linear Search"
+msgstr ""
+
+#: ../../examples/linear_search.rst:4
+msgid "Searches for a value in an array."
+msgstr ""
+
+#: ../../examples/linear_search.rst:10
+msgid "Demonstrates sequential search and early loop exit."
+msgstr ""
+
diff --git a/docs/locales/ja/LC_MESSAGES/examples/memory_copy.po b/docs/locales/ja/LC_MESSAGES/examples/memory_copy.po
new file mode 100644
index 0000000..cb0c751
--- /dev/null
+++ b/docs/locales/ja/LC_MESSAGES/examples/memory_copy.po
@@ -0,0 +1,33 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, 2026.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:30+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language: ja\n"
+"Language-Team: ja <LL@li.org>\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=utf-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Generated-By: Babel 2.17.0\n"
+
+#: ../../examples/memory_copy.rst:2
+msgid "Memory Copy"
+msgstr ""
+
+#: ../../examples/memory_copy.rst:4
+msgid "Copies data from one memory location to another."
+msgstr ""
+
+#: ../../examples/memory_copy.rst:10
+msgid "Demonstrates memory-to-memory data transfer."
+msgstr ""
+
diff --git a/docs/locales/ja/LC_MESSAGES/examples/multiply_by_shift.po b/docs/locales/ja/LC_MESSAGES/examples/multiply_by_shift.po
new file mode 100644
index 0000000..b6dedf4
--- /dev/null
+++ b/docs/locales/ja/LC_MESSAGES/examples/multiply_by_shift.po
@@ -0,0 +1,33 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, 2026.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:30+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language: ja\n"
+"Language-Team: ja <LL@li.org>\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=utf-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Generated-By: Babel 2.17.0\n"
+
+#: ../../examples/multiply_by_shift.rst:2
+msgid "Multiply by Shift"
+msgstr ""
+
+#: ../../examples/multiply_by_shift.rst:4
+msgid "Multiplies numbers using bit shifting instead of MUL instruction."
+msgstr ""
+
+#: ../../examples/multiply_by_shift.rst:10
+msgid "Demonstrates bit manipulation and efficient multiplication."
+msgstr ""
+
diff --git a/docs/locales/ja/LC_MESSAGES/examples/power.po b/docs/locales/ja/LC_MESSAGES/examples/power.po
new file mode 100644
index 0000000..0ddf83c
--- /dev/null
+++ b/docs/locales/ja/LC_MESSAGES/examples/power.po
@@ -0,0 +1,33 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, 2026.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:30+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language: ja\n"
+"Language-Team: ja <LL@li.org>\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=utf-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Generated-By: Babel 2.17.0\n"
+
+#: ../../examples/power.rst:2
+msgid "Power Function"
+msgstr ""
+
+#: ../../examples/power.rst:4
+msgid "Computes x^n using repeated multiplication."
+msgstr ""
+
+#: ../../examples/power.rst:10
+msgid "Demonstrates exponentiation through iteration."
+msgstr ""
+
diff --git a/docs/locales/ja/LC_MESSAGES/examples/reverse.po b/docs/locales/ja/LC_MESSAGES/examples/reverse.po
new file mode 100644
index 0000000..2c9bd73
--- /dev/null
+++ b/docs/locales/ja/LC_MESSAGES/examples/reverse.po
@@ -0,0 +1,33 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, 2026.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:30+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language: ja\n"
+"Language-Team: ja <LL@li.org>\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=utf-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Generated-By: Babel 2.17.0\n"
+
+#: ../../examples/reverse.rst:2
+msgid "Reverse Array"
+msgstr ""
+
+#: ../../examples/reverse.rst:4
+msgid "Reverses an array in place."
+msgstr ""
+
+#: ../../examples/reverse.rst:10
+msgid "Demonstrates two-pointer technique and array manipulation."
+msgstr ""
+
diff --git a/docs/locales/ja/LC_MESSAGES/examples/sum_1_to_n.po b/docs/locales/ja/LC_MESSAGES/examples/sum_1_to_n.po
new file mode 100644
index 0000000..ee58b9e
--- /dev/null
+++ b/docs/locales/ja/LC_MESSAGES/examples/sum_1_to_n.po
@@ -0,0 +1,33 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, 2026.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:30+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language: ja\n"
+"Language-Team: ja <LL@li.org>\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=utf-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Generated-By: Babel 2.17.0\n"
+
+#: ../../examples/sum_1_to_n.rst:2
+msgid "Sum 1 to N"
+msgstr ""
+
+#: ../../examples/sum_1_to_n.rst:4
+msgid "Calculates the sum of integers from 1 to N."
+msgstr ""
+
+#: ../../examples/sum_1_to_n.rst:10
+msgid "Demonstrates accumulation pattern and loop control."
+msgstr ""
+
diff --git a/docs/locales/ja/LC_MESSAGES/getting_started.po b/docs/locales/ja/LC_MESSAGES/getting_started.po
new file mode 100644
index 0000000..2e3ee2c
--- /dev/null
+++ b/docs/locales/ja/LC_MESSAGES/getting_started.po
@@ -0,0 +1,306 @@
+# Japanese translation for Tiny8 getting_started documentation.
+# Copyright (C) 2025-2026, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+#
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:30+0900\n"
+"PO-Revision-Date: 2026-10-24 22:22+0900\n"
+"Last-Translator: sql-hkr <sql.hkr@gmail.com>\n"
+"Language: ja\n"
+"Language-Team: ja <LL@li.org>\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=utf-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Generated-By: Babel 2.17.0\n"
+
+#: ../../getting_started.rst:2
+msgid "Getting Started"
+msgstr "はじめに"
+
+#: ../../getting_started.rst:4
+msgid ""
+"This guide will help you get started with Tiny8, from installation to "
+"running your first programs."
+msgstr "このガイドでは、Tiny8のインストールから最初のプログラムの実行までの手順を解説します。"
+
+#: ../../getting_started.rst:7
+msgid "Installation"
+msgstr "インストール"
+
+#: ../../getting_started.rst:10
+msgid "Requirements"
+msgstr "システム要件"
+
+#: ../../getting_started.rst:12
+msgid "Tiny8 requires Python 3.11 or later. Check your Python version:"
+msgstr "Tiny8の動作にはPython 3.11以上が必要です。Pythonのバージョンを確認してください:"
+
+#: ../../getting_started.rst:19
+msgid "Installing Tiny8"
+msgstr "Tiny8のインストール"
+
+#: ../../getting_started.rst:21
+msgid "Install Tiny8 using pip:"
+msgstr "pipを使用してTiny8をインストール:"
+
+#: ../../getting_started.rst:27
+msgid ""
+"This will install the ``tiny8`` command-line tool and make the Python API"
+" available for import."
+msgstr "これによりコマンドラインツール ``tiny8`` がインストールされ、Python APIが利用可能になります。"
+
+#: ../../getting_started.rst:30
+msgid "Verifying Installation"
+msgstr "インストールの確認"
+
+#: ../../getting_started.rst:32
+msgid "Verify that Tiny8 is installed correctly:"
+msgstr "Tiny8が正しくインストールされたか確認します:"
+
+#: ../../getting_started.rst:38
+msgid "You should see the version number printed to the terminal."
+msgstr "ターミナルにバージョン番号が表示されます。"
+
+#: ../../getting_started.rst:41
+msgid "Your First Program"
+msgstr "最初のプログラム"
+
+#: ../../getting_started.rst:43
+msgid "Let's write a simple program that adds two numbers."
+msgstr "2つの数値を加算する簡単なプログラムを作成してみましょう。"
+
+#: ../../getting_started.rst:46
+msgid "Create the Assembly File"
+msgstr "アセンブリファイルの作成"
+
+#: ../../getting_started.rst:48
+msgid "Create a new file called ``add.asm`` with the following content:"
+msgstr "以下の内容で ``add.asm`` というファイルを作成します:"
+
+#: ../../getting_started.rst:63
+msgid "Understanding the Code"
+msgstr "コードの解説"
+
+#: ../../getting_started.rst:65
+msgid "Let's break down what each line does:"
+msgstr "各行の処理内容を詳しく見ていきます:"
+
+#: ../../getting_started.rst:67
+msgid ""
+"``ldi r16, 5`` - **L** oa **d** **I** mmediate: Loads the value 5 "
+"directly into register 16"
+msgstr "``ldi r16, 5`` - 即値ロード: レジスタ16に数値5を直接格納します"
+
+#: ../../getting_started.rst:68
+msgid "``ldi r17, 3`` - Loads the value 3 into register 17"
+msgstr "``ldi r17, 3`` - レジスタ17に数値3を直接格納します"
+
+#: ../../getting_started.rst:69
+msgid ""
+"``add r16, r17`` - Adds the contents of R17 to R16, storing the result in"
+" R16"
+msgstr "``add r16, r17`` - R17の値をR16に加算し、結果をR16に格納します"
+
+#: ../../getting_started.rst:70
+msgid "``jmp done`` - Jumps to the label ``done``, creating an infinite loop"
+msgstr "``jmp done`` - ``done`` ラベルにジャンプし、無限ループを形成して停止します"
+
+#: ../../getting_started.rst:73
+msgid "Lines starting with ``;`` are comments and are ignored by the assembler."
+msgstr "``;`` で始まる行はコメントであり、アセンブラによって無視されます。"
+
+#: ../../getting_started.rst:76
+msgid "Running with the Interactive Debugger"
+msgstr "インタラクティブデバッガでの実行"
+
+#: ../../getting_started.rst:78
+msgid "Run your program using the Tiny8 interactive debugger:"
+msgstr "Tiny8のインタラクティブデバッガでプログラムを実行します:"
+
+#: ../../getting_started.rst:84
+msgid "You'll see a terminal-based interface showing:"
+msgstr "ターミナル画面上に以下の要素が表示されます:"
+
+#: ../../getting_started.rst:86
+msgid ""
+"**Source code** - Your assembly program with the current instruction "
+"highlighted"
+msgstr "**ソースコード** - 現在実行中の命令がハイライトされたアセンブリコード"
+
+#: ../../getting_started.rst:87
+msgid "**Registers** - The 32 general-purpose registers (R0-R31)"
+msgstr "**レジスタ** - 32本の汎用レジスタ (R0-R31)"
+
+#: ../../getting_started.rst:88
+msgid "**Status flags** - The SREG flags (I, T, H, S, V, N, Z, C)"
+msgstr "**ステータスフラグ** - SREGフラグ (I, T, H, S, V, N, Z, C)"
+
+#: ../../getting_started.rst:89
+msgid "**Memory** - RAM contents"
+msgstr "**メモリ** - RAMのメモリダンプ"
+
+#: ../../getting_started.rst:90
+msgid ""
+"**Control information** - Program counter (PC), stack pointer (SP), and "
+"step count"
+msgstr "**制御情報** - プログラムカウンタ (PC)、スタックポインタ (SP)、ステップ数"
+
+#: ../../getting_started.rst:93
+msgid "Debugger Controls"
+msgstr "デバッガの操作方法"
+
+#: ../../getting_started.rst:95
+msgid "Use these keyboard shortcuts to control execution:"
+msgstr "以下のキーボードショートカットで実行を制御できます:"
+
+#: ../../getting_started.rst:97
+msgid "**Execution:**"
+msgstr "**実行操作:**"
+
+#: ../../getting_started.rst:99
+msgid "``Space`` - Play / pause automatic continuous execution"
+msgstr "``Space`` - 自動連続実行の再生 / 一時停止"
+
+#: ../../getting_started.rst:100
+msgid "``Shift+Space`` - Reverse playback execution"
+msgstr "``Shift+Space`` - 逆再生実行"
+
+#: ../../getting_started.rst:101
+msgid "``n`` - Step forward 1 instruction (+1 step)"
+msgstr "``n`` - 1命令進む (+1ステップ)"
+
+#: ../../getting_started.rst:102
+msgid "``p`` - Step backward 1 instruction (-1 step, time-travel)"
+msgstr "``p`` - 1命令戻る (-1ステップ, タイムトラベル)"
+
+#: ../../getting_started.rst:103
+msgid "``c`` - Continue forward to next breakpoint"
+msgstr "``c`` - 次のブレークポイントまで前方継続実行"
+
+#: ../../getting_started.rst:104
+msgid "``C`` (``Shift+c``) - Reverse continue backward to previous breakpoint"
+msgstr "``C`` (``Shift+c``) - 前のブレークポイントまで逆方向継続実行"
+
+#: ../../getting_started.rst:105
+msgid "``b`` - Toggle breakpoint at current PC"
+msgstr "``b`` - 現在のPC位置でブレークポイントを設定/解除"
+
+#: ../../getting_started.rst:106
+msgid "``+`` / ``-`` - Increase / decrease playback speed"
+msgstr "``+`` / ``-`` - 再生速度の加速 / 減速"
+
+#: ../../getting_started.rst:107
+msgid "``r`` - Reset execution back to Step 0"
+msgstr "``r`` - ステップ0にリセット"
+
+#: ../../getting_started.rst:109
+msgid "**Display & Navigation:**"
+msgstr "**表示 & ナビゲーション:**"
+
+#: ../../getting_started.rst:111
+msgid "``j`` / ``k`` - Scroll memory view down / up by 32 bytes (1 row)"
+msgstr "``j`` / ``k`` - メモリビューを32バイト (1行) 下/上にスクロール"
+
+#: ../../getting_started.rst:112
+msgid "``J`` / ``K`` - Fast scroll memory view down / up by 128 bytes (4 rows)"
+msgstr "``J`` / ``K`` - メモリビューを128バイト (4行) 高速スクロール"
+
+#: ../../getting_started.rst:113
+msgid "``g`` - Toggle Grayscale / Viridis color palette"
+msgstr "``g`` - グレースケール / Viridisカラーパレット切替"
+
+#: ../../getting_started.rst:114
+msgid "``x`` - Toggle Hexadecimal (02X) / Graphic Pixel blocks"
+msgstr "``x`` - 16進数 (02X) / グラフィックピクセルブロック切替"
+
+#: ../../getting_started.rst:115
+msgid "``m`` - Cycle view modes"
+msgstr "``m`` - 表示モードの巡回切替"
+
+#: ../../getting_started.rst:116
+msgid "``i`` - Inspect details of currently executing instruction"
+msgstr "``i`` - 現在実行中の命令の詳細情報を表示"
+
+#: ../../getting_started.rst:117
+msgid "``h`` or ``?`` - Open full help and keyboard guide modal"
+msgstr "``h`` または ``?`` - ヘルプ＆キーボードガイドモーダルを開く"
+
+#: ../../getting_started.rst:118
+msgid "``e`` - Open built-in Vim modal editor"
+msgstr "``e`` - 内蔵Vimモーダルエディタを開く"
+
+#: ../../getting_started.rst:120
+msgid "**Command Bar Prompt:**"
+msgstr "**コマンドバープロンプト:**"
+
+#: ../../getting_started.rst:122
+msgid "``:`` - Enter command prompt (e.g. ``:goto <step>``, ``:b <pc>``, ``:q``)"
+msgstr ""
+"``:`` - コマンドプロンプトを開く (例: ``:goto <step>``, ``:b <pc>``, ``:q``)"
+
+#: ../../getting_started.rst:124
+msgid "**Exit:**"
+msgstr "**終了:**"
+
+#: ../../getting_started.rst:126
+msgid "``q`` - Quit debugger"
+msgstr "``q`` - デバッガを終了"
+
+#: ../../getting_started.rst:128
+msgid ""
+"Try stepping through your program with ``n`` and watch how the registers "
+"change!"
+msgstr "``n`` キーでプログラムを1ステップずつ進め、レジスタの値の変化を観察してみましょう。"
+
+#: ../../getting_started.rst:131
+msgid "Running from Python"
+msgstr "Pythonからの実行"
+
+#: ../../getting_started.rst:133
+msgid "You can also run Tiny8 programs from Python code."
+msgstr "Tiny8のプログラムはPythonコード内からも実行できます。"
+
+#: ../../getting_started.rst:136
+msgid "Basic Execution"
+msgstr "基本的な実行"
+
+#: ../../getting_started.rst:158
+msgid "Step-by-Step Execution"
+msgstr "ステップごとの実行"
+
+#: ../../getting_started.rst:160
+msgid "For more control, you can step through the program manually:"
+msgstr "より詳細に制御する場合は、手動で1ステップずつ進めることができます:"
+
+#: ../../getting_started.rst:188
+msgid "Inspecting CPU State"
+msgstr "CPU状態の検査"
+
+#: ../../getting_started.rst:190
+msgid "You can inspect various aspects of the CPU state:"
+msgstr "CPUの各種状態を取得・検査できます:"
+
+#: ../../getting_started.rst:209
+msgid "Common Assembly Patterns"
+msgstr "一般的なアセンブリパターン"
+
+#: ../../getting_started.rst:212
+msgid "Loading Immediate Values"
+msgstr "即値のロード"
+
+#: ../../getting_started.rst:221
+msgid "Working with Memory"
+msgstr "メモリ操作"
+
+#: ../../getting_started.rst:233
+msgid "Loops"
+msgstr "ループ処理"
+
+#: ../../getting_started.rst:247
+msgid "Conditional Branching"
+msgstr "条件分岐"
+
diff --git a/docs/locales/ja/LC_MESSAGES/index.po b/docs/locales/ja/LC_MESSAGES/index.po
new file mode 100644
index 0000000..dd5c2a0
--- /dev/null
+++ b/docs/locales/ja/LC_MESSAGES/index.po
@@ -0,0 +1,229 @@
+# Japanese translation for Tiny8 documentation.
+# Copyright (C) 2025-2026, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+#
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-25 01:27+0900\n"
+"PO-Revision-Date: 2026-10-24 22:20+0900\n"
+"Last-Translator: sql-hkr <sql.hkr@gmail.com>\n"
+"Language: ja\n"
+"Language-Team: ja <LL@li.org>\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=utf-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Generated-By: Babel 2.17.0\n"
+
+#: ../../index.rst:117
+msgid "User Guide"
+msgstr "ユーザーガイド"
+
+#: ../../index.rst:126
+msgid "Examples"
+msgstr "サンプルプログラム"
+
+#: ../../index.rst:132
+msgid "API Reference"
+msgstr "API リファレンス"
+
+#: ../../index.rst:4
+msgid "Tiny8 Documentation"
+msgstr "Tiny8 ドキュメント"
+
+#: ../../index.rst:6
+msgid ""
+"**From bare-metal computer architecture to Generative AI — an educational"
+" 8-bit AVR RISC CPU simulator with real-time interactive visualization**"
+msgstr ""
+"**低レイヤのコンピュータアーキテクチャから生成AI（拡散モデル）までを繋ぐ、教育用8ビットAVR "
+"CPUシミュレータ＆インタラクティブビジュアライザ**"
+
+#: ../../index.rst:8
+msgid ""
+"Tiny8 is a lightweight educational toolkit that bridges bare-metal "
+"computer architecture and modern Generative AI. Designed for hands-on "
+"learning and experimentation, it guides you through the full stack of "
+"computing — from 32 general-purpose registers, ALU operations, stack "
+"frames, and C compilation up to executing an iterative reverse-diffusion "
+"model synthesizing 28x28 MNIST digits directly on an AVR 8-bit RISC "
+"processor. With an interactive Vim-inspired terminal debugger, time-"
+"travel reverse execution, and a 32x32 TrueColor memory heatmap, Tiny8 "
+"lets you see, step through, and understand computation at every level."
+msgstr ""
+"Tiny8は、低レイヤのコンピュータアーキテクチャから現代の生成AIまでを一気通貫で学べる教育用ツールキットです。32個の汎用レジスタ、ALU演算、スタックフレーム、ポインタ操作、C言語コンパイルといったハードウェア基礎から、8ビットAVR"
+" RISCプロセッサ上で直接動作する反復逆拡散モデル（Diffusion Model）による28x28 "
+"MNIST数字生成までを、リアルタイムなインタラクティブTUIデバッガ、タイムトラベル逆実行、32x32 "
+"TrueColorメモリヒートマップを通じて直感的に探索・プログラミング・視覚化できます。"
+
+#: ../../index.rst:10
+msgid "Animated bubble sort visualization"
+msgstr "バブルソートの可視化アニメーション"
+
+#: ../../index.rst:16
+msgid "Real-time visualization of a bubble sort algorithm executing on Tiny8"
+msgstr "Tiny8上で実行されるバブルソートアルゴリズムのリアルタイム可視化"
+
+#: ../../index.rst:18
+msgid "Features"
+msgstr "主な特徴"
+
+#: ../../index.rst:21
+msgid "Interactive Terminal Debugger"
+msgstr "インタラクティブなターミナルデバッガ"
+
+#: ../../index.rst:23
+msgid "CLI visualizer screenshot"
+msgstr "CLIビジュアライザのスクリーンショット"
+
+#: ../../index.rst:28
+msgid ""
+"**Vim-style navigation**: Step through execution with intuitive keyboard "
+"controls"
+msgstr "**Vim風ナビゲーション**: 直感的なキーボード操作で実行を1ステップずつ追跡"
+
+#: ../../index.rst:29
+msgid ""
+"**Change highlighting**: See exactly what changed at each step "
+"(registers, flags, memory)"
+msgstr "**変更箇所の強調表示**: 各ステップで変更されたレジスタ、フラグ、メモリをリアルタイムに強調"
+
+#: ../../index.rst:30
+msgid ""
+"**Time-travel debugging**: Step forward and backward with sparse "
+"checkpoint restoration"
+msgstr "**タイムトラベルデバッグ**: スパースチェックポイント復元による前進・後退ステップ実行"
+
+#: ../../index.rst:31
+msgid ""
+"**32x32 TrueColor Heatmap**: VRAM memory matrix with Viridis/Grayscale "
+"visualization"
+msgstr "**32x32 TrueColorヒートマップ**: Viridis/グレースケールによるVRAMメモリマトリックス可視化"
+
+#: ../../index.rst:32
+msgid ""
+"**Built-in Vim Editor**: Launch full-screen modal editor anytime with "
+"``e``"
+msgstr "**内蔵Vimエディタ**: ``e`` キーでいつでも全画面モーダルエディタを起動可能"
+
+#: ../../index.rst:33
+msgid ""
+"**Internationalization**: English (en) and Japanese (ja) localization "
+"support"
+msgstr "**国際化対応 (i18n)**: 英語 (en) および日本語 (ja) のローカライゼーション対応"
+
+#: ../../index.rst:36
+msgid "Complete 8-bit Architecture"
+msgstr "完全な8ビットアーキテクチャ"
+
+#: ../../index.rst:38
+msgid "**32 general-purpose registers** (R0-R31)"
+msgstr "**32本の汎用レジスタ** (R0-R31)"
+
+#: ../../index.rst:39
+msgid "**8-bit ALU** with arithmetic, logical, and bit manipulation operations"
+msgstr "算術・論理・ビット操作をサポートする **8ビットALU**"
+
+#: ../../index.rst:40
+msgid "**Status register (SREG)** with 8 condition flags"
+msgstr "8個の条件フラグを持つ **ステータスレジスタ (SREG)**"
+
+#: ../../index.rst:41
+msgid "**64KB address space** for unified memory and I/O"
+msgstr "統合メモリおよびI/O用の **64KBアドレス空間**"
+
+#: ../../index.rst:42
+msgid "**Stack operations** with dedicated stack pointer"
+msgstr "専用スタックポインタによる **スタック操作**"
+
+#: ../../index.rst:43
+msgid ""
+"**AVR instruction set** with 67 instructions compliant with Microchip "
+"DS40002198A"
+msgstr "Microchip DS40002198Aに準拠した67命令を備えた **AVR命令セット**"
+
+#: ../../index.rst:46
+msgid "Educational Focus"
+msgstr "教育重視の設計"
+
+#: ../../index.rst:48
+msgid "Clean, readable Python implementation"
+msgstr "クリーンで読みやすいPython実装"
+
+#: ../../index.rst:49
+msgid "Comprehensive examples (Fibonacci, bubble sort, factorial, and more)"
+msgstr "充実したサンプルプログラム (フィボナッチ、バブルソート、階乗など)"
+
+#: ../../index.rst:50
+msgid "Step-by-step execution traces for debugging"
+msgstr "デバッグ用の詳細なステップ実行トレース"
+
+#: ../../index.rst:51
+msgid "Full API documentation and instruction set reference"
+msgstr "完全なAPIドキュメントおよび命令セットリファレンス"
+
+#: ../../index.rst:54
+msgid "Quick Start"
+msgstr "クイックスタート"
+
+#: ../../index.rst:57
+msgid "Installation"
+msgstr "インストール"
+
+#: ../../index.rst:59
+msgid "Install Tiny8 using pip:"
+msgstr "pipを使用してTiny8をインストール:"
+
+#: ../../index.rst:66
+msgid "Your First Program"
+msgstr "最初のプログラム"
+
+#: ../../index.rst:68
+msgid "Create a file called ``fibonacci.asm``:"
+msgstr "``fibonacci.asm`` というファイルを作成:"
+
+#: ../../index.rst:90
+msgid "Run it with the interactive debugger:"
+msgstr "インタラクティブデバッガで実行:"
+
+#: ../../index.rst:97
+msgid "Using the Python API"
+msgstr "Python APIの使用"
+
+#: ../../index.rst:115
+msgid "Documentation Contents"
+msgstr "ドキュメント目次"
+
+#: ../../index.rst:139
+msgid "Indices and Tables"
+msgstr "索引とテーブル"
+
+#: ../../index.rst:141
+msgid ":ref:`genindex`"
+msgstr ":ref:`genindex`"
+
+#: ../../index.rst:142
+msgid ":ref:`modindex`"
+msgstr ":ref:`modindex`"
+
+#: ../../index.rst:143
+msgid ":ref:`search`"
+msgstr ":ref:`search`"
+
+#~ msgid ""
+#~ "Tiny8 is a lightweight and educational"
+#~ " toolkit for exploring the fundamentals "
+#~ "of computer architecture through hands-"
+#~ "on assembly programming and real-time"
+#~ " visualization. Designed for learning and"
+#~ " experimentation, it features an AVR "
+#~ "8-bit RISC CPU architecture with 32 "
+#~ "registers, a standard-compliant instruction"
+#~ " set, and powerful debugging tools —"
+#~ " all with zero heavy dependencies."
+#~ msgstr ""
+#~ "Tiny8は、実践的なアセンブリプログラミングとリアルタイム可視化を通じてコンピュータアーキテクチャの基礎を探求するための、軽量な教育用ツールキットです。学習と実験のために設計されており、32個のレジスタを持つAVR"
+#~ " 8ビットRISC CPUアーキテクチャ、規格準拠の命令セット、強力なデバッグツールを、重い外部依存関係なしで提供します。"
+
diff --git a/docs/locales/ja/LC_MESSAGES/visualization.po b/docs/locales/ja/LC_MESSAGES/visualization.po
new file mode 100644
index 0000000..45e2f49
--- /dev/null
+++ b/docs/locales/ja/LC_MESSAGES/visualization.po
@@ -0,0 +1,403 @@
+# Japanese translation for Tiny8 visualization documentation.
+# Copyright (C) 2025-2026, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+#
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-25 00:49+0900\n"
+"PO-Revision-Date: 2026-10-24 22:24+0900\n"
+"Last-Translator: sql-hkr <sql.hkr@gmail.com>\n"
+"Language: ja\n"
+"Language-Team: ja <LL@li.org>\n"
+"Plural-Forms: nplurals=1; plural=0;\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=utf-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+"Generated-By: Babel 2.17.0\n"
+
+#: ../../visualization.rst:2
+msgid "Visualization & Debugger"
+msgstr "可視化 & デバッガ"
+
+#: ../../visualization.rst:4
+msgid ""
+"Tiny8 features a modern, real-time terminal visualizer and visual "
+"debugger powered by `Textual <https://textual.textualize.io/>`_. It "
+"provides interactive execution controls, sparse checkpoint time-travel, a"
+" 32x32 TrueColor memory heatmap, and a full-screen built-in modal editor."
+msgstr ""
+"Tiny8は、`Textual <https://textual.textualize.io/>`_ "
+"を採用したモダンなリアルタイムターミナルビジュアライザ＆デバッガを搭載しています。インタラクティブな実行制御、スパースチェックポイントによるタイムトラベルデバッグ、32x32"
+" TrueColorメモリヒートマップ、全画面の内蔵モーダルエディタを提供します。"
+
+#: ../../visualization.rst:7
+msgid "Launching the TUI"
+msgstr "TUIの起動"
+
+#: ../../visualization.rst:9
+msgid "To run any assembly or C program with the interactive debugger:"
+msgstr "インタラクティブデバッガでアセンブリまたはCプログラムを実行するには:"
+
+#: ../../visualization.rst:16
+msgid "You can also specify options such as step limits or editor launch:"
+msgstr "実行ステップ数の上限やエディタ起動などのオプションを指定することもできます:"
+
+#: ../../visualization.rst:30
+msgid "Interface Overview"
+msgstr "インターフェース概要"
+
+#: ../../visualization.rst:32
+msgid ""
+"Real-time generative reverse-diffusion synthesis (MNIST 8) at x5,000 "
+"speed in Tiny8 TUI (Viridis Palette, Forward Pixel + Reverse Hex)"
+msgstr ""
+
+#: ../../visualization.rst:37
+msgid ""
+"*Real-time generative reverse-diffusion synthesis (MNIST 8) executing at "
+"x5,000 speed in Tiny8 TUI (Viridis Palette: Forward Pixel + Reverse Hex)*"
+msgstr ""
+
+#: ../../visualization.rst:39
+msgid ""
+"Real-time generative reverse-diffusion synthesis (MNIST 8) at x5,000 "
+"speed in Tiny8 TUI (Grayscale Palette, Forward Pixel + Reverse Hex)"
+msgstr ""
+
+#: ../../visualization.rst:44
+msgid ""
+"*Real-time generative reverse-diffusion synthesis (MNIST 8) executing at "
+"x5,000 speed in Tiny8 TUI (Grayscale Palette: Forward Pixel + Reverse "
+"Hex)*"
+msgstr ""
+
+#: ../../visualization.rst:46
+msgid "The debugger interface provides real-time reactive panels:"
+msgstr "デバッガ画面はリアルタイムに反応する複数のパネルで構成されています:"
+
+#: ../../visualization.rst:66
+msgid "Interactive Controls"
+msgstr "インタラクティブ操作"
+
+#: ../../visualization.rst:69
+msgid "Execution & Time-Travel"
+msgstr "実行 & タイムトラベル"
+
+#: ../../visualization.rst:75 ../../visualization.rst:105
+msgid "Key"
+msgstr "キー"
+
+#: ../../visualization.rst:76 ../../visualization.rst:106
+msgid "Action"
+msgstr "操作内容"
+
+#: ../../visualization.rst:77
+msgid "``Space``"
+msgstr "``Space``"
+
+#: ../../visualization.rst:78
+msgid "Play / pause automatic continuous execution"
+msgstr "自動連続実行の再生 / 一時停止"
+
+#: ../../visualization.rst:79
+msgid "``Shift+Space``"
+msgstr "``Shift+Space``"
+
+#: ../../visualization.rst:80
+msgid "Reverse playback automatic continuous execution"
+msgstr "逆方向の自動連続再生"
+
+#: ../../visualization.rst:81
+msgid "``n``"
+msgstr "``n``"
+
+#: ../../visualization.rst:82
+msgid "Step forward 1 instruction (+1 step)"
+msgstr "1命令進む (+1ステップ)"
+
+#: ../../visualization.rst:83
+msgid "``p``"
+msgstr "``p``"
+
+#: ../../visualization.rst:84
+msgid "Step backward 1 instruction (-1 step, Time-Travel debug)"
+msgstr "1命令戻る (-1ステップ, タイムトラベルデバッグ)"
+
+#: ../../visualization.rst:85
+msgid "``c``"
+msgstr "``c``"
+
+#: ../../visualization.rst:86
+msgid "Continue forward until next breakpoint or program halt"
+msgstr "次のブレークポイントまたはプログラム終了まで前方継続実行"
+
+#: ../../visualization.rst:87
+msgid "``C`` (``Shift+c``)"
+msgstr "``C`` (``Shift+c``)"
+
+#: ../../visualization.rst:88
+msgid "Reverse continue backward until previous breakpoint or start"
+msgstr "前のブレークポイントまたは開始位置まで後方逆行実行"
+
+#: ../../visualization.rst:89
+msgid "``b``"
+msgstr "``b``"
+
+#: ../../visualization.rst:90
+msgid "Toggle breakpoint at current PC"
+msgstr "現在のPC位置でブレークポイントを設定/解除"
+
+#: ../../visualization.rst:91
+msgid "``+`` / ``-``"
+msgstr "``+`` / ``-``"
+
+#: ../../visualization.rst:92
+msgid "Increase / decrease automatic playback execution speed"
+msgstr "自動再生速度の加速 / 減速"
+
+#: ../../visualization.rst:93
+msgid "``r``"
+msgstr "``r``"
+
+#: ../../visualization.rst:94
+msgid "Reset execution back to Step 0"
+msgstr "ステップ0にリセット"
+
+#: ../../visualization.rst:95
+msgid "``q``"
+msgstr "``q``"
+
+#: ../../visualization.rst:96
+msgid "Quit Tiny8 application"
+msgstr "Tiny8アプリケーションを終了"
+
+#: ../../visualization.rst:99
+msgid "View & Display Controls"
+msgstr "表示 & ビュー操作"
+
+#: ../../visualization.rst:107
+msgid "``j`` / ``k``"
+msgstr "``j`` / ``k``"
+
+#: ../../visualization.rst:108
+msgid "Scroll memory viewport down / up by 32 bytes (1 row)"
+msgstr "メモリビューを32バイト (1行) 下/上にスクロール"
+
+#: ../../visualization.rst:109
+msgid "``J`` / ``K``"
+msgstr "``J`` / ``K``"
+
+#: ../../visualization.rst:110
+msgid "Fast scroll memory viewport down / up by 128 bytes (4 rows)"
+msgstr "メモリビューを128バイト (4行) 下/上に高速スクロール"
+
+#: ../../visualization.rst:111
+msgid "``g``"
+msgstr "``g``"
+
+#: ../../visualization.rst:112
+msgid "Toggle between Viridis and Grayscale color palettes"
+msgstr "Viridisとグレースケールのカラーパレットを切替"
+
+#: ../../visualization.rst:113
+msgid "``x``"
+msgstr "``x``"
+
+#: ../../visualization.rst:114
+msgid "Toggle between Hexadecimal digits (02X) and Graphic Pixel blocks"
+msgstr "16進数表記 (02X) とグラフィックピクセルブロックを切替"
+
+#: ../../visualization.rst:115
+msgid "``m``"
+msgstr "``m``"
+
+#: ../../visualization.rst:116
+msgid ""
+"Cycle view modes (Viridis+Hex -> Viridis+Pixel -> Grayscale+Pixel -> "
+"Grayscale+Hex)"
+msgstr ""
+"表示モード循環切替 (Viridis+Hex -> Viridis+Pixel -> Grayscale+Pixel -> "
+"Grayscale+Hex)"
+
+#: ../../visualization.rst:117
+msgid "``i``"
+msgstr "``i``"
+
+#: ../../visualization.rst:118
+msgid "Inspect details of the currently executing instruction"
+msgstr "現在実行中の命令の詳細情報を表示"
+
+#: ../../visualization.rst:119
+msgid "``h`` or ``?``"
+msgstr "``h`` または ``?``"
+
+#: ../../visualization.rst:120
+msgid "Open full TUI Application Usage & Keyboard Guide"
+msgstr "全TUI使用方法＆キーボードガイドモーダルを開く"
+
+#: ../../visualization.rst:121
+msgid "``e``"
+msgstr "``e``"
+
+#: ../../visualization.rst:122
+msgid "Launch the built-in full-screen Vim-style modal editor"
+msgstr "内蔵の全画面Vim風モーダルエディタを起動"
+
+#: ../../visualization.rst:125
+msgid "Command Bar Prompt (:)"
+msgstr "コマンドバープロンプト (:)"
+
+#: ../../visualization.rst:127
+msgid "Press ``:`` anytime from the debugger to enter commands:"
+msgstr "デバッガ画面で ``:`` を押すといつでもコマンドを入力できます:"
+
+#: ../../visualization.rst:133
+msgid "Command"
+msgstr "コマンド"
+
+#: ../../visualization.rst:134
+msgid "Description"
+msgstr "説明"
+
+#: ../../visualization.rst:135
+msgid "``:goto <step>``"
+msgstr "``:goto <step>``"
+
+#: ../../visualization.rst:136
+msgid "Seek directly to an execution step (e.g., ``:goto 500``)"
+msgstr "指定ステップへ直接ジャンプ (例: ``:goto 500``)"
+
+#: ../../visualization.rst:137
+msgid "``:b <pc> [if expr]``"
+msgstr "``:b <pc> [if expr]``"
+
+#: ../../visualization.rst:138
+msgid "Set conditional breakpoint (e.g., ``:b 0x0010 if R16 > 10``)"
+msgstr "条件付きブレークポイントを設定 (例: ``:b 0x0010 if R16 > 10``)"
+
+#: ../../visualization.rst:139
+msgid "``:watch <target>``"
+msgstr "``:watch <target>``"
+
+#: ../../visualization.rst:140
+msgid "Set watchpoint on register or memory address"
+msgstr "レジスタまたはメモリ番地にウォッチポイントを設定"
+
+#: ../../visualization.rst:141
+msgid "``:set <reg> <val>``"
+msgstr "``:set <reg> <val>``"
+
+#: ../../visualization.rst:142
+msgid "Modify register value dynamically (e.g., ``:set R16 42``)"
+msgstr "レジスタの値を動的に変更 (例: ``:set R16 42``)"
+
+#: ../../visualization.rst:143
+msgid "``:poke <addr> <val>``"
+msgstr "``:poke <addr> <val>``"
+
+#: ../../visualization.rst:144
+msgid "Modify RAM byte value dynamically (e.g., ``:poke 0x0200 255``)"
+msgstr "RAMバイト値を動的に変更 (例: ``:poke 0x0200 255``)"
+
+#: ../../visualization.rst:145
+msgid "``:exec <asm>``"
+msgstr "``:exec <asm>``"
+
+#: ../../visualization.rst:146
+msgid "Execute an assembly instruction immediately (e.g., ``:exec LDI R16, 5``)"
+msgstr "アセンブリ命令を即座に動的実行 (例: ``:exec LDI R16, 5``)"
+
+#: ../../visualization.rst:147
+msgid "``:speed <ms>``"
+msgstr "``:speed <ms>``"
+
+#: ../../visualization.rst:148
+msgid "Set playback speed interval in milliseconds"
+msgstr "再生インターバルをミリ秒単位で設定"
+
+#: ../../visualization.rst:149
+msgid "``:m <addr>``"
+msgstr "``:m <addr>``"
+
+#: ../../visualization.rst:150
+msgid "Jump memory viewport to specified address"
+msgstr "メモリビューポートを指定アドレスへジャンプ"
+
+#: ../../visualization.rst:151
+msgid "``:q`` / ``:quit``"
+msgstr "``:q`` / ``:quit``"
+
+#: ../../visualization.rst:152
+msgid "Exit debugger"
+msgstr "デバッガを終了"
+
+#: ../../visualization.rst:155
+msgid "Built-in Vim Modal Editor"
+msgstr "内蔵Vimモーダルエディタ"
+
+#: ../../visualization.rst:157
+msgid ""
+"Press ``e`` anytime or pass ``--edit`` on the command line to enter the "
+"full-screen Vim editor:"
+msgstr "デバッグ中に ``e`` を押すか、コマンドラインで ``--edit`` を渡すと全画面Vimエディタに入ります:"
+
+#: ../../visualization.rst:159
+msgid ""
+"**NORMAL Mode**: Full cursor navigation with ``h``/``j``/``k``/``l``, "
+"word jump ``w``/``b``, line bounds ``0``/``$``, file bounds ``gg``/``G``,"
+" delete character ``x``, delete line ``dd``, copy line ``yy``, paste "
+"``p``, undo ``u``, redo ``Ctrl+r``."
+msgstr ""
+"**ノーマルモード**: ``h``/``j``/``k``/``l`` によるカーソル移動、``w``/``b`` "
+"による単語移動、``0``/``$`` による行頭行末、``gg``/``G`` によるファイル先頭末尾、``x`` による文字削除、``dd``"
+" による行削除、``yy`` による行コピー、``p`` によるペースト、``u`` によるアンドゥ、``Ctrl+r`` によるリドゥを完備。"
+
+#: ../../visualization.rst:160
+msgid ""
+"**INSERT Mode**: Press ``i``, ``a``, or ``o`` to write code freely. Press"
+" ``Esc`` to return to NORMAL mode."
+msgstr "**インサートモード**: ``i``、``a``、``o`` を押して自由にコードを記述。``Esc`` でノーマルモードに戻ります。"
+
+#: ../../visualization.rst:161
+msgid ""
+"**COMMAND Mode**: Press ``:`` to enter commands: * ``:w`` - Save code to "
+"file * ``:wq`` or ``:x`` - Save and return to debugger * ``:run`` - "
+"Compile/assemble code and restart debugging immediately * ``:q`` or "
+"``:q!`` - Exit editor back to debugger"
+msgstr ""
+"**コマンドモード**: ``:`` を押してコマンドを実行: * ``:w`` - コードをファイルに保存 * ``:wq`` または "
+"``:x`` - 保存してデバッガに戻る * ``:run`` - 再コンパイル/アセンブルして即座にシミュレーションを再開 * ``:q`` "
+"または ``:q!`` - エディタを終了してデバッガに戻る"
+
+#: ../../visualization.rst:168
+msgid "Documentation Internationalization (i18n)"
+msgstr "ドキュメント多言語対応 (i18n)"
+
+#: ../../visualization.rst:170
+msgid ""
+"Tiny8 documentation supports English (en) and Japanese (ja) localization "
+"via Sphinx gettext:"
+msgstr "Tiny8のドキュメントはSphinx gettextを通じて英語 (en) および日本語 (ja) の多言語ローカライゼーションに対応しています:"
+
+#~ msgid "``:lang <en|ja>``"
+#~ msgstr "``:lang <en|ja>``"
+
+#~ msgid "Dynamically switch UI language between English and Japanese"
+#~ msgstr "UI表示言語を英語/日本語間で動的に切り替え"
+
+#~ msgid "**CLI flag**: ``tiny8 <file> --lang ja`` or ``tiny8 <file> -l en``"
+#~ msgstr "**CLIフラグ**: ``tiny8 <file> --lang ja`` または ``tiny8 <file> -l en``"
+
+#~ msgid ""
+#~ "**Environment variables**: ``TINY8_LANG=ja`` or "
+#~ "system locale ``LANG=ja_JP.UTF-8``"
+#~ msgstr "**環境変数**: ``TINY8_LANG=ja`` またはシステムロケール ``LANG=ja_JP.UTF-8``"
+
+#~ msgid ""
+#~ "**Runtime switching**: Enter ``:lang ja`` "
+#~ "or ``:lang en`` in the debugger "
+#~ "command prompt"
+#~ msgstr "**実行時切替**: デバッガのコマンドプロンプトで ``:lang ja`` または ``:lang en`` を入力"
+
diff --git a/docs/locales/pot/api/modules.pot b/docs/locales/pot/api/modules.pot
new file mode 100644
index 0000000..0e8cf71
--- /dev/null
+++ b/docs/locales/pot/api/modules.pot
@@ -0,0 +1,21 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-25 00:49+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../api/modules.rst:2
+msgid "tiny8"
+msgstr ""
diff --git a/docs/locales/pot/api/tiny8.pot b/docs/locales/pot/api/tiny8.pot
new file mode 100644
index 0000000..d1f7343
--- /dev/null
+++ b/docs/locales/pot/api/tiny8.pot
@@ -0,0 +1,3189 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-25 01:27+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../api/tiny8.rst:2
+msgid "tiny8 package"
+msgstr ""
+
+#: ../../api/tiny8.rst:5
+msgid "Submodules"
+msgstr ""
+
+#: ../../api/tiny8.rst:8
+msgid "tiny8.assembler module"
+msgstr ""
+
+#: ../../../src/tiny8/assembler.py:docstring of tiny8.assembler:1
+msgid "Assembler for tiny8 converting assembly text into program listings."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.assembler.AsmResult:1
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU:1
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.utils.ProgressBar:1
+#: ../../../src/tiny8/assembler.py:docstring of tiny8.assembler.AsmResult:1
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.ASTNode:1
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.CodeGenerator:1
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.Lexer:1
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.Parser:1
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.Token:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU:1
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory:1
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CheckpointManager:1
+#: ../../../src/tiny8/utils.py:docstring of tiny8.utils.ProgressBar:1
+msgid "Bases: :py:class:`object`"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.assembler.AsmResult:1
+#: ../../../src/tiny8/assembler.py:docstring of tiny8.assembler.AsmResult:1
+msgid "Result of assembling assembly source code."
+msgstr ""
+
+#: ../../api/tiny8.rst:0
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.restore_snapshot:0
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.CodeGenerator.gen_expr:0
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.optimize_assembly:0
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.restore_snapshot:0
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory.restore_ram:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CheckpointManager.detect_loop:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CheckpointManager.invalidate_after:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CheckpointManager.precompute:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CheckpointManager.record:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CheckpointManager.record_if_interval:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CheckpointManager.restore_exact_step:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.MemoryWidget.get_heatmap_bg:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_exec_instruction:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.on_input_submitted:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.watch_mem_start:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.eval_condition:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.extract_call_frames:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.get_widget_available_lines:0
+msgid "Parameters"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.assembler.AsmResult:5
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU:65
+#: ../../../src/tiny8/assembler.py:docstring of tiny8.assembler.AsmResult:5
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU:47
+msgid "List of instruction tuples in (mnemonic, operands) format."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.assembler.AsmResult:0
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU:0
+#: ../../../src/tiny8/assembler.py:docstring of tiny8.assembler.AsmResult:0
+msgid "type"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.assembler.AsmResult:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU:67
+#: ../../../src/tiny8/assembler.py:docstring of tiny8.assembler.AsmResult:7
+msgid "list[tuple[str, tuple]]"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.assembler.AsmResult:11
+#: ../../../src/tiny8/assembler.py:docstring of tiny8.assembler.AsmResult:11
+msgid "Mapping of label names to program counter addresses."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.assembler.AsmResult:13
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU:73
+#: ../../../src/tiny8/assembler.py:docstring of tiny8.assembler.AsmResult:13
+msgid "dict[str, int]"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.assembler.AsmResult:17
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU:77
+#: ../../../src/tiny8/assembler.py:docstring of tiny8.assembler.AsmResult:17
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU:55
+msgid "Mapping of program counter to source line numbers."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.assembler.AsmResult:19
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU:79
+#: ../../../src/tiny8/assembler.py:docstring of tiny8.assembler.AsmResult:19
+msgid "dict[int, int]"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.assembler.AsmResult:23
+#: ../../../src/tiny8/assembler.py:docstring of tiny8.assembler.AsmResult:23
+msgid "Original source lines for display and debugging."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.assembler.AsmResult:25
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU:85
+#: ../../../src/tiny8/assembler.py:docstring of tiny8.assembler.AsmResult:25
+msgid "list[str]"
+msgstr ""
+
+#: ../../api/tiny8.rst:0
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.clear_traces:0
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.restore_snapshot:0
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.snapshot:0
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.utils.ProgressBar.__enter__:0
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.utils.ProgressBar.__exit__:0
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.utils.ProgressBar.close:0
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.utils.ProgressBar.reset:0
+#: ../../../src/tiny8/cli.py:docstring of tiny8.tui.main:0
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.CodeGenerator.gen_expr:0
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.Lexer.tokenize:0
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.optimize_assembly:0
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.clear_traces:0
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.restore_snapshot:0
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.snapshot:0
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory.clear_changes:0
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory.restore_ram:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CacheProgressModalScreen.compose:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CheckpointManager.detect_loop:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CheckpointManager.invalidate_after:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CheckpointManager.precompute:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CheckpointManager.record:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CheckpointManager.record_if_interval:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CheckpointManager.restore_exact_step:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.InstructionDetailModalScreen.compose:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.InstructionReferenceScreen.compose:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.MemoryWidget.get_heatmap_bg:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.TUIHelpScreen.compose:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_cancel_command:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_continue_run:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_cycle_mode:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_exec_instruction:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_faster:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_open_command:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_open_editor:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_reverse_continue:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_scroll_down:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_scroll_page_down:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_scroll_page_up:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_scroll_up:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_show_help:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_show_instruction_detail:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_show_reference:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_slower:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_toggle_breakpoint:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_toggle_grayscale:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_toggle_hex:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_toggle_play:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_toggle_reverse_play:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.compose:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.on_input_submitted:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.watch_mem_start:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.VimEditorScreen.compose:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.eval_condition:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.extract_call_frames:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.get_widget_available_lines:0
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.main:0
+#: ../../../src/tiny8/utils.py:docstring of tiny8.utils.ProgressBar.__enter__:0
+#: ../../../src/tiny8/utils.py:docstring of tiny8.utils.ProgressBar.__exit__:0
+#: ../../../src/tiny8/utils.py:docstring of tiny8.utils.ProgressBar.close:0
+#: ../../../src/tiny8/utils.py:docstring of tiny8.utils.ProgressBar.reset:0
+msgid "Return type"
+msgstr ""
+
+#: ../../../src/tiny8/assembler.py:docstring of tiny8.assembler.parse_asm:1
+msgid "Parse assembly source text into an AsmResult structure."
+msgstr ""
+
+#: ../../../src/tiny8/assembler.py:docstring of tiny8.assembler.parse_asm:3
+msgid "Assembly source text."
+msgstr ""
+
+#: ../../api/tiny8.rst:0
+msgid "Returns"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.assembler.assemble:5
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.assembler.assemble_file:5
+#: ../../../src/tiny8/assembler.py:docstring of tiny8.assembler.assemble:5
+#: ../../../src/tiny8/assembler.py:docstring of tiny8.assembler.assemble_file:5
+#: ../../../src/tiny8/assembler.py:docstring of tiny8.assembler.parse_asm:5
+msgid "AsmResult containing parsed program, labels, and line mappings."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.assembler.assemble:1
+#: ../../../src/tiny8/assembler.py:docstring of tiny8.assembler.assemble:1
+msgid "Assemble source text into program instructions and label mappings."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.assembler.assemble:3
+#: ../../../src/tiny8/assembler.py:docstring of tiny8.assembler.assemble:3
+msgid "Assembly source code string."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.assembler.assemble_file:1
+#: ../../../src/tiny8/assembler.py:docstring of tiny8.assembler.assemble_file:1
+msgid "Assemble source file into program instructions and label mappings."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.assembler.assemble_file:3
+#: ../../../src/tiny8/assembler.py:docstring of tiny8.assembler.assemble_file:3
+msgid "Path to the assembly source file."
+msgstr ""
+
+#: ../../api/tiny8.rst:0
+msgid "Raises"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.assembler.assemble_file:7
+#: ../../../src/tiny8/assembler.py:docstring of tiny8.assembler.assemble_file:7
+msgid "If the source file does not exist."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.assembler.assemble_file:8
+#: ../../../src/tiny8/assembler.py:docstring of tiny8.assembler.assemble_file:8
+msgid "If reading the file fails."
+msgstr ""
+
+#: ../../api/tiny8.rst:16
+msgid "tiny8.cli module"
+msgstr ""
+
+#: ../../../src/tiny8/cli.py:docstring of tiny8.cli:1
+msgid "Backward-compatibility wrapper forwarding to tiny8.tui."
+msgstr ""
+
+#: ../../../src/tiny8/cli.py:docstring of tiny8.tui.main:1
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.main:1
+msgid "Entry point for tiny8 CLI supporting Assembly and C sources."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.tui.run_cli:1
+#: ../../../src/tiny8/cli.py:docstring of tiny8.tui.run_cli:1
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.run_cli:1
+msgid "Launch modern Textual TUI debugger with OLED black theme and gradient heatmaps."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.tui.run_cli:3
+#: ../../../src/tiny8/cli.py:docstring of tiny8.tui.run_cli:3
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.run_cli:3
+msgid "CPU emulator with execution history."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.tui.run_cli:4
+#: ../../../src/tiny8/cli.py:docstring of tiny8.tui.run_cli:4
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.run_cli:4
+msgid "Start address for memory viewer."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.tui.run_cli:5
+#: ../../../src/tiny8/cli.py:docstring of tiny8.tui.run_cli:5
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.run_cli:5
+msgid "End address for memory viewer."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.tui.run_cli:6
+#: ../../../src/tiny8/cli.py:docstring of tiny8.tui.run_cli:6
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.run_cli:6
+msgid "Playback interval in seconds."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.tui.run_cli:7
+#: ../../../src/tiny8/cli.py:docstring of tiny8.tui.run_cli:7
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.run_cli:7
+msgid "Source assembly or C lines."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.tui.run_cli:8
+#: ../../../src/tiny8/cli.py:docstring of tiny8.tui.run_cli:8
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.run_cli:8
+msgid "C variable metadata symbols."
+msgstr ""
+
+#: ../../api/tiny8.rst:24
+msgid "tiny8.compiler module"
+msgstr ""
+
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler:1
+msgid "Simple C compiler for Tiny8 converting a subset of C into Tiny8 assembly."
+msgstr ""
+
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler:3
+msgid "Features: - Variable declarations and assignments (int/char) - Arithmetic (+, -, *, /, %), bitwise (&, |, ^, ~), logical (!), and relational (<, <=, >, >=, ==, !=) - Control structures: if / else, while, return - Functions with register-based parameter passing (R16..R19) and return value in R16 - Hardware builtins: peek(addr), poke(addr, val), in(port), out(port, val)"
+msgstr ""
+
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.Token:1
+msgid "Lexical token."
+msgstr ""
+
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.Lexer:1
+msgid "Tokenize C source code."
+msgstr ""
+
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.Lexer.tokenize:1
+msgid "Convert input source into tokens, ignoring whitespace and comments."
+msgstr ""
+
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.ASTNode:1
+msgid "Base AST node."
+msgstr ""
+
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.ArrayAccess:1
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.ArrayAssign:1
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.ArrayDecl:1
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.Assign:1
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.BinaryOp:1
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.Block:1
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.BreakStmt:1
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.Call:1
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.ExprStmt:1
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.ForStmt:1
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.FunctionDef:1
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.IfStmt:1
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.Literal:1
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.Program:1
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.ReturnStmt:1
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.StringLiteral:1
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.UnaryOp:1
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.Var:1
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.VarDecl:1
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.WhileStmt:1
+msgid "Bases: :py:class:`~tiny8.compiler.ASTNode`"
+msgstr ""
+
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.Program:1
+msgid "Program root containing functions and global declarations."
+msgstr ""
+
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.VarDecl:1
+msgid "Variable declaration."
+msgstr ""
+
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.ArrayDecl:1
+msgid "Array variable declaration."
+msgstr ""
+
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.ArrayAccess:1
+msgid "Array indexing expression: name[index]."
+msgstr ""
+
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.ArrayAssign:1
+msgid "Array element assignment: name[index] = expr."
+msgstr ""
+
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.FunctionDef:1
+msgid "Function definition."
+msgstr ""
+
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.Block:1
+msgid "Block of statements."
+msgstr ""
+
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.Assign:1
+msgid "Assignment statement."
+msgstr ""
+
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.IfStmt:1
+msgid "If-else statement."
+msgstr ""
+
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.WhileStmt:1
+msgid "While loop."
+msgstr ""
+
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.ForStmt:1
+msgid "For loop."
+msgstr ""
+
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.BreakStmt:1
+msgid "Break statement."
+msgstr ""
+
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.ReturnStmt:1
+msgid "Return statement."
+msgstr ""
+
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.ExprStmt:1
+msgid "Expression statement."
+msgstr ""
+
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.BinaryOp:1
+msgid "Binary expression."
+msgstr ""
+
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.UnaryOp:1
+msgid "Unary expression."
+msgstr ""
+
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.Literal:1
+msgid "Literal integer value."
+msgstr ""
+
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.StringLiteral:1
+msgid "String literal value."
+msgstr ""
+
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.Var:1
+msgid "Variable reference."
+msgstr ""
+
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.Call:1
+msgid "Function call expression."
+msgstr ""
+
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.Parser:1
+msgid "Recursive descent parser."
+msgstr ""
+
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.optimize_assembly:1
+msgid "Perform peephole optimizations on generated assembly lines."
+msgstr ""
+
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.optimize_assembly:3
+msgid "Optimizations include: - Removing redundant self register moves (MOV Rx, Rx) - Simplifying PUSH Rx followed immediately by POP Ry into MOV Ry, Rx (or eliminating if Rx == Ry) - Removing redundant LD R16, R30 immediately after ST R30, R16 - Removing JMP <label> when the next line is <label>:"
+msgstr ""
+
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.CodeGenerator:1
+msgid "Generate Tiny8 assembly from AST using register & stack model."
+msgstr ""
+
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.CodeGenerator.gen_expr:1
+msgid "Evaluate expression, leaving the 8-bit result in R16."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.compiler.compile_c:1
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.compile_c:1
+msgid "Compile C source code string into Tiny8 assembly."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.compiler.compile_c:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.compiler.compile_c_with_symbols:3
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.compile_c:3
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.compile_c_with_symbols:3
+msgid "C language source code text."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.compiler.compile_c:4
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.compiler.compile_c_file:4
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.compiler.compile_c_file_with_symbols:4
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.compiler.compile_c_with_symbols:4
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.compile_c:4
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.compile_c_file:4
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.compile_c_file_with_symbols:4
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.compile_c_with_symbols:4
+msgid "Whether to apply peephole optimization. Defaults to True."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.compiler.compile_c:6
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.compiler.compile_c_file:6
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.compile_c:6
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.compile_c_file:6
+msgid "Generated Tiny8 assembly source string."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.compiler.compile_c_file:1
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.compile_c_file:1
+msgid "Read and compile C source file into Tiny8 assembly."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.compiler.compile_c_file:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.compiler.compile_c_file_with_symbols:3
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.compile_c_file:3
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.compile_c_file_with_symbols:3
+msgid "Path to C source file."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.compiler.compile_c_with_symbols:1
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.compile_c_with_symbols:1
+msgid "Compile C source into Tiny8 assembly alongside variable symbol table."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.compiler.compile_c_file_with_symbols:6
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.compiler.compile_c_with_symbols:6
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.compile_c_file_with_symbols:6
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.compile_c_with_symbols:6
+msgid "Tuple of (assembly_source_string, symbols_dict)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.compiler.compile_c_file_with_symbols:1
+#: ../../../src/tiny8/compiler.py:docstring of tiny8.compiler.compile_c_file_with_symbols:1
+msgid "Read and compile C source file into Tiny8 assembly with symbol table."
+msgstr ""
+
+#: ../../api/tiny8.rst:32
+msgid "tiny8.cpu module"
+msgstr ""
+
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu:1
+msgid "Simplified AVR-like 8-bit CPU simulator."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU:1
+msgid "Lightweight 8-bit AVR CPU emulator compliant with Microchip DS40002198A."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU:3
+msgid "Optional Memory instance. Defaults to a new Memory instance."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU:7
+msgid "Attached Memory instance."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU:11
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU:11
+msgid "List of 32 8-bit general purpose registers (R0..R31)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU:17
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU:15
+msgid "Current program counter address."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU:23
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU:19
+msgid "Stack pointer pointing to current top of stack in RAM."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU:29
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU:23
+msgid "Status register integer containing I, T, H, S, V, N, Z, C flags."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU:35
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU:27
+msgid "Number of instructions executed so far."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU:41
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU:31
+msgid "Mapping of interrupt vector addresses to enabled flags."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU:47
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU:35
+msgid "Change history of registers as (step, reg_idx, new_val) tuples."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU:53
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU:39
+msgid "Change history of RAM as (step, addr, new_val) tuples."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU:59
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU:43
+msgid "Full per-step snapshots for tracing and visualization."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU:71
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU:51
+msgid "Mapping of symbolic labels to program counter addresses."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU:83
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU:59
+msgid "Original assembly source text lines."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU:89
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU:63
+msgid "Flag indicating whether execution loop is active."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.clear_traces:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.clear_traces:1
+msgid "Clear execution traces and history to free memory."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.snapshot:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.snapshot:1
+msgid "Capture complete CPU and memory execution state snapshot."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.restore_snapshot:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.restore_snapshot:1
+msgid "Restore CPU and memory execution state from a snapshot."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.set_flag:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.set_flag:1
+msgid "Set or clear a status register flag bit."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.get_flag:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.set_flag:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.get_flag:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.set_flag:3
+msgid "SREG bit index (0..7)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.set_flag:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.set_flag:4
+msgid "True to set flag, False to clear."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.get_flag:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.get_flag:1
+msgid "Return boolean status of a specific SREG bit."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.get_flag:5
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.get_flag:5
+msgid "True if bit is set, False otherwise."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.read_reg:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.read_reg:1
+msgid "Return 8-bit value from register r."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.read_reg:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.write_reg:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.read_reg:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.write_reg:3
+msgid "Register index (0..31)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.read_reg:5
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.read_reg:5
+msgid "8-bit unsigned integer value."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.write_reg:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.write_reg:1
+msgid "Write 8-bit value to register r and trace changes."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.write_reg:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.write_reg:4
+msgid "Integer value to store (masked to 8-bit)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.read_ram:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.read_ram:1
+msgid "Read byte from RAM address."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_cbi:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbi:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.read_ram:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_cbi:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbi:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.read_ram:3
+msgid "Memory address."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.read_ram:5
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.read_ram:5
+msgid "Byte value stored at address."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.write_ram:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.write_ram:1
+msgid "Write byte to RAM address and record memory trace."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.write_ram:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.write_ram:3
+msgid "Target RAM address."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.write_ram:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.write_ram:4
+msgid "Byte value to write."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.load_program:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.load_program:1
+msgid "Load assembled program instructions into CPU."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.load_program:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.load_program:3
+msgid "AsmResult object or list of (mnemonic, operands) tuples."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.load_program:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.load_program:4
+msgid "Label mapping if program is a raw list."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.load_program:5
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.load_program:5
+msgid "PC to line mapping if program is a raw list."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.load_program:6
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.load_program:6
+msgid "Source text lines if program is a raw list."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.step:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.step:1
+msgid "Execute next single instruction at current program counter."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.step:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.step:3
+msgid "Optional override to enable or disable trace recording for this step."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.step:5
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.step:5
+msgid "True if instruction executed successfully, False if PC is out of range."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.step:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.step:7
+msgid "If instruction mnemonic has no handler."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.run:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.run:1
+msgid "Run instructions until completion or max_steps limit is reached."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.run:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.run:3
+msgid "Maximum instruction step executions allowed."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.run:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.run:4
+msgid "Whether to show progress bar in terminal."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_nop:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_nop:1
+msgid "No Operation (NOP)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_adc:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_add:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_adiw:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_and:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_andi:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brcc:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brcs:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_breq:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brge:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brlo:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brlt:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brmi:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brne:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brpl:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brsh:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_call:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_cbi:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_cli:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_cp:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_cpi:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_cpse:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_dec:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_eor:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_in:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_inc:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_jmp:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_ld:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_ldi:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_lds:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_mov:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_nop:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_or:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_ori:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_out:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_pop:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_push:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_rcall:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_ret:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_reti:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_rjmp:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbc:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbci:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbi:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbic:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbis:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbiw:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbrc:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbrs:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sei:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_st:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sts:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sub:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_subi:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_adc:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_add:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_adiw:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_and:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_andi:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brcc:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brcs:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_breq:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brge:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brlo:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brlt:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brmi:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brne:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brpl:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brsh:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_call:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_cbi:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_cli:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_cp:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_cpi:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_cpse:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_dec:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_eor:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_in:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_inc:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_jmp:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_ld:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_ldi:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_lds:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_mov:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_nop:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_or:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_ori:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_out:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_pop:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_push:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_rcall:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_ret:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_reti:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_rjmp:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbc:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbci:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbi:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbic:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbis:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbiw:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbrc:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbrs:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sei:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_st:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sts:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sub:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_subi:3
+msgid "Per AVR Instruction Set Manual DS40002198A:"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_nop:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_nop:4
+msgid "Operation: No operation. Status Register (SREG): None."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_ldi:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_ldi:1
+msgid "Load Immediate (LDI)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_ldi:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_ldi:4
+msgid "Operation: Rd <- K (16 <= d <= 31, 0 <= K <= 255) Status Register (SREG): None."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_andi:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_ldi:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_ori:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbci:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_subi:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_andi:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_ldi:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_ori:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbci:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_subi:7
+msgid "Destination register index (16..31)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_cpi:8
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_ldi:8
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_cpi:8
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_ldi:8
+msgid "Immediate byte value."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_mov:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_mov:1
+msgid "Copy Register (MOV)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_mov:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_mov:4
+msgid "Operation: Rd <- Rr (0 <= d, r <= 31) Status Register (SREG): None."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_adc:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_add:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_and:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_asr:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_clr:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_com:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_dec:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_eor:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_in:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_inc:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_ld:9
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_lds:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_lsl:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_lsr:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_mov:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_neg:6
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_or:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_pop:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_rol:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_ror:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbc:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_ser:6
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sub:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_swap:6
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_adc:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_add:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_and:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_asr:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_clr:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_com:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_dec:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_eor:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_in:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_inc:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_ld:9
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_lds:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_lsl:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_lsr:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_mov:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_neg:6
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_or:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_pop:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_rol:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_ror:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbc:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_ser:6
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sub:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_swap:6
+msgid "Destination register index."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_adc:8
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_add:8
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_and:8
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_eor:8
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_mov:8
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_or:8
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_out:8
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_push:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbc:8
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_st:10
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sts:8
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sub:8
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_adc:8
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_add:8
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_and:8
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_eor:8
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_mov:8
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_or:8
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_out:8
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_push:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbc:8
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_st:10
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sts:8
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sub:8
+msgid "Source register index."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_add:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_add:1
+msgid "Add without Carry (ADD)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_add:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_add:4
+msgid "Operation: Rd <- Rd + Rr Status Register (SREG): H, S, V, N, Z, C"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_and:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_and:1
+msgid "Logical AND (AND)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_and:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_and:4
+msgid "Operation: Rd <- Rd • Rr Status Register (SREG): S, V=0, N, Z (H, C unaffected)"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_or:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_or:1
+msgid "Logical OR (OR)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_or:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_or:4
+msgid "Operation: Rd <- Rd v Rr Status Register (SREG): S, V=0, N, Z (H, C unaffected)"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_eor:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_eor:1
+msgid "Exclusive OR (EOR)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_eor:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_eor:4
+msgid "Operation: Rd <- Rd ⊕ Rr Status Register (SREG): S, V=0, N, Z (H, C unaffected)"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sub:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sub:1
+msgid "Subtract without Carry (SUB)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sub:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sub:4
+msgid "Operation: Rd <- Rd - Rr Status Register (SREG): H, S, V, N, Z, C"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_inc:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_inc:1
+msgid "Increment (INC)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_inc:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_inc:4
+msgid "Operation: Rd <- Rd + 1 Status Register (SREG): S, V, N, Z (C unaffected)"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_dec:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_dec:1
+msgid "Decrement (DEC)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_dec:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_dec:4
+msgid "Operation: Rd <- Rd - 1 Status Register (SREG): S, V, N, Z (C unaffected)"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_mul:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_mul:1
+msgid "Multiply Unsigned (MUL)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_mul:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_mul:3
+msgid "AVR Instruction Set Manual DS40002198A: R1:R0 <- Rd * Rr (unsigned). SREG C: Set if bit 15 of result is set; cleared otherwise. SREG Z: Set if result is $0000; cleared otherwise."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_mul:8
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_mul:8
+msgid "Multiplicand register index (0..31)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_mul:9
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_mul:9
+msgid "Multiplier register index (0..31)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_muls:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_muls:1
+msgid "Multiply Signed (MULS)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_muls:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_muls:3
+msgid "AVR Instruction Set Manual DS40002198A: R1:R0 <- Rd * Rr (signed). SREG C: Set if bit 15 of result is set; cleared otherwise. SREG Z: Set if result is $0000; cleared otherwise."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_muls:8
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_mulsu:8
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_muls:8
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_mulsu:8
+msgid "Multiplicand signed register index (0..31)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_muls:9
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_muls:9
+msgid "Multiplier signed register index (0..31)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_mulsu:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_mulsu:1
+msgid "Multiply Signed with Unsigned (MULSU)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_mulsu:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_mulsu:3
+msgid "AVR Instruction Set Manual DS40002198A: R1:R0 <- Rd * Rr (Rd signed, Rr unsigned). SREG C: Set if bit 15 of result is set; cleared otherwise. SREG Z: Set if result is $0000; cleared otherwise."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_mulsu:9
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_mulsu:9
+msgid "Multiplier unsigned register index (0..31)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_adc:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_adc:1
+msgid "Add with Carry (ADC)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_adc:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_adc:4
+msgid "Operation: Rd <- Rd + Rr + C Status Register (SREG): H, S, V, N, Z, C"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_clr:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_clr:1
+msgid "Clear Register: Rd <- Rd ⊕ Rd = $00 (EOR Rd, Rd)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_asr:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_clr:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_com:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_lsl:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_lsr:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_neg:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_rol:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_ror:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_ser:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_swap:3
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_tst:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_asr:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_clr:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_com:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_lsl:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_lsr:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_neg:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_rol:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_ror:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_ser:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_swap:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_tst:3
+msgid "Status Register (SREG) per AVR Manual DS40002198A:"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_clr:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_clr:4
+msgid "S: 0, V: 0, N: 0, Z: 1; H, C, T, I unaffected. Alternative name to the EOR Rd, Rd instruction."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_ser:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_ser:1
+msgid "Set Register: Rd <- $FF (LDI Rd, $FF)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_ser:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_ser:4
+msgid "None affected. Alternative name to the LDI Rd, $FF instruction."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_in:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_in:1
+msgid "Load an I/O Location to Register (IN)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_in:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_in:4
+msgid "Operation: Rd <- P Status Register (SREG): None."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_in:8
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_in:8
+msgid "Port/memory address to read from."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_out:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_out:1
+msgid "Store Register to an I/O Location (OUT)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_out:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_out:4
+msgid "Operation: P <- Rr Status Register (SREG): None."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_out:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_out:7
+msgid "Port/memory address to write to."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_jmp:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_jmp:1
+msgid "Jump (JMP)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_jmp:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_jmp:4
+msgid "Operation: PC <- k Status Register (SREG): None."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_jmp:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_jmp:7
+msgid "Target label name or instruction address."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_jmp:9
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_jmp:9
+msgid "If target label string is not found."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_cpi:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_cpi:1
+msgid "Compare with Immediate (CPI)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_cpi:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_cpi:4
+msgid "Operation: Rd - K (16 <= d <= 31, 0 <= K <= 255) Status Register (SREG): H, S, V, N, Z, C"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_cpi:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_cpi:7
+msgid "Register index to compare (16..31)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_cp:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_cp:1
+msgid "Compare (CP)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_cp:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_cp:4
+msgid "Operation: Rd - Rr Status Register (SREG): H, S, V, N, Z, C"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_cp:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_cpse:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_cp:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_cpse:7
+msgid "First register index."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_cp:8
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_cpse:8
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_cp:8
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_cpse:8
+msgid "Second register index."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_lsl:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_lsl:1
+msgid "Logical Shift Left: C <- Rd7, Rd(n+1) <- Rd(n), Rd0 <- 0."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_lsl:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_lsl:4
+msgid "H: Rd3, S: N ⊕ V, V: N ⊕ C, N: R7, Z: Set if result is $00, C: Rd7 Alternative name to the ADD Rd, Rd instruction."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_lsr:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_lsr:1
+msgid "Logical Shift Right: 0 -> Rd7 -> ... -> Rd0 -> C."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_lsr:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_lsr:4
+msgid "S: N ⊕ V, V: C, N: 0, Z: Set if result is $00, C: Rd0 H, T, I unaffected (-)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_asr:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_asr:1
+msgid "Arithmetic Shift Right: Rd7 -> Rd7 -> ... -> Rd0 -> C."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_asr:4
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_ror:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_asr:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_ror:4
+msgid "S: N ⊕ V, V: N ⊕ C, N: R7, Z: Set if result is $00, C: Rd0 H, T, I unaffected (-)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_rol:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_rol:1
+msgid "Rotate Left Through Carry: C <- Rd7, Rd(n+1) <- Rd(n), Rd0 <- C."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_rol:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_rol:4
+msgid "H: Rd3, S: N ⊕ V, V: N ⊕ C, N: R7, Z: Set if result is $00, C: Rd7 Alternative name to the ADC Rd, Rd instruction."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_ror:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_ror:1
+msgid "Rotate Right Through Carry: Rd7 <- C, Rd(n) <- Rd(n+1), C <- Rd0."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_com:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_com:1
+msgid "One's Complement: Rd <- $FF - Rd."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_com:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_com:4
+msgid "S: N ⊕ V, V: 0, N: R7, Z: Set if result is $00, C: 1 H, T, I unaffected (-)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_neg:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_neg:1
+msgid "Two's Complement: Rd <- $00 - Rd."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_neg:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_neg:4
+msgid "H: R3 + ~Rd3, S: N ⊕ V, V: Rd == $80, N: R7, Z: Set if result is $00, C: Rd != $00"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_swap:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_swap:1
+msgid "Swap Nibbles: Rd(7..4) <-> Rd(3..0)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_swap:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_swap:4
+msgid "None affected."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_tst:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_tst:1
+msgid "Test for Zero or Minus: Rd & Rd."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_tst:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_tst:4
+msgid "S: N ⊕ V, V: 0, N: R7, Z: Set if Rd is $00 Alternative name to the AND Rd, Rd instruction."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_tst:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_tst:7
+msgid "Register index to test."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_andi:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_andi:1
+msgid "Logical AND with Immediate (ANDI)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_andi:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_andi:4
+msgid "Operation: Rd <- Rd • K (16 <= d <= 31, 0 <= K <= 255) Status Register (SREG): S, V=0, N, Z (H, C unaffected)"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_andi:8
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_ori:8
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbci:8
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_subi:8
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_andi:8
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_ori:8
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbci:8
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_subi:8
+msgid "Immediate value."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_ori:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_ori:1
+msgid "Logical OR with Immediate (ORI)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_ori:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_ori:4
+msgid "Operation: Rd <- Rd v K (16 <= d <= 31, 0 <= K <= 255) Status Register (SREG): S, V=0, N, Z (H, C unaffected)"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_subi:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_subi:1
+msgid "Subtract Immediate (SUBI)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_subi:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_subi:4
+msgid "Operation: Rd <- Rd - K (16 <= d <= 31, 0 <= K <= 255) Status Register (SREG): H, S, V, N, Z, C"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbc:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbc:1
+msgid "Subtract with Carry (SBC)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbc:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbc:4
+msgid "Operation: Rd <- Rd - Rr - C Status Register (SREG): H, S, V, N, Z, C"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbci:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbci:1
+msgid "Subtract Immediate with Carry (SBCI)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbci:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbci:4
+msgid "Operation: Rd <- Rd - K - C (16 <= d <= 31, 0 <= K <= 255) Status Register (SREG): H, S, V, N, Z, C"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sei:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sei:1
+msgid "Set Global Interrupt Flag (SEI)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sei:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sei:4
+msgid "Operation: I <- 1 Status Register (SREG): I"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_cli:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_cli:1
+msgid "Clear Global Interrupt Flag (CLI)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_cli:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_cli:4
+msgid "Operation: I <- 0 Status Register (SREG): I"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_cpse:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_cpse:1
+msgid "Compare Skip if Equal (CPSE)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_cpse:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_cpse:4
+msgid "Operation: If Rd = Rr then PC <- PC + 2 (or 3) Status Register (SREG): None (all flags unaffected)"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbrs:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbrs:1
+msgid "Skip if Bit in Register is Set (SBRS)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbrs:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbrs:4
+msgid "Operation: If Rd(b) = 1 then PC <- PC + 2 (or 3) Status Register (SREG): None."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbrc:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbrs:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbrc:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbrs:7
+msgid "Register index."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_cbi:8
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbi:8
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbic:8
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbis:8
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbrc:8
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbrs:8
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_cbi:8
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbi:8
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbic:8
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbis:8
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbrc:8
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbrs:8
+msgid "Bit index (0..7)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbrc:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbrc:1
+msgid "Skip if Bit in Register is Cleared (SBRC)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbrc:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbrc:4
+msgid "Operation: If Rd(b) = 0 then PC <- PC + 2 (or 3) Status Register (SREG): None."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbis:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbis:1
+msgid "Skip if Bit in I/O Register is Set (SBIS)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbis:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbis:4
+msgid "Operation: If P(b) = 1 then PC <- PC + 2 (or 3) Status Register (SREG): None."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbic:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbis:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbic:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbis:7
+msgid "I/O or RAM address."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbic:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbic:1
+msgid "Skip if Bit in I/O Register is Cleared (SBIC)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbic:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbic:4
+msgid "Operation: If P(b) = 0 then PC <- PC + 2 (or 3) Status Register (SREG): None."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbiw:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbiw:1
+msgid "Subtract Immediate from Word (SBIW)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbiw:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbiw:4
+msgid "Operation: Rd+1:Rd <- Rd+1:Rd - K (d in {24, 26, 28, 30}, 0 <= K <= 63) Status Register (SREG): S, V, N, Z, C"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_adiw:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbiw:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_adiw:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbiw:7
+msgid "Low register index of register pair (e.g. 24, 26, 28, 30)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbiw:8
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbiw:8
+msgid "Immediate value to subtract."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_adiw:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_adiw:1
+msgid "Add Immediate to Word (ADIW)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_adiw:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_adiw:4
+msgid "Operation: Rd+1:Rd <- Rd+1:Rd + K (d in {24, 26, 28, 30}, 0 <= K <= 63) Status Register (SREG): S, V, N, Z, C"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_adiw:8
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_adiw:8
+msgid "Immediate value to add."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_rjmp:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_rjmp:1
+msgid "Relative Jump (RJMP)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_rjmp:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_rjmp:4
+msgid "Operation: PC <- PC + k + 1 Status Register (SREG): None."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_rjmp:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_rjmp:7
+msgid "Jump target offset or symbolic label."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_rcall:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_rcall:1
+msgid "Relative Call to Subroutine (RCALL)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_rcall:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_rcall:4
+msgid "Operation: PC <- PC + k + 1, STACK <- PC + 1 Status Register (SREG): None."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_rcall:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_rcall:7
+msgid "Call target offset or symbolic label."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbi:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbi:1
+msgid "Set Bit in I/O Register (SBI)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sbi:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sbi:4
+msgid "Operation: I/O(P, b) <- 1 Status Register (SREG): None."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_cbi:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_cbi:1
+msgid "Clear Bit in I/O Register (CBI)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_cbi:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_cbi:4
+msgid "Operation: I/O(P, b) <- 0 Status Register (SREG): None."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_ld:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_ld:1
+msgid "Load Indirect from Data Space to Register (LD)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_ld:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_ld:4
+msgid "Operation: Rd <- (X / Y / Z) Status Register (SREG): None."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_ld:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_st:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_ld:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_st:7
+msgid "Supports 16-bit pointer pairs (X=R27:R26, Y=R29:R28, Z=R31:R30) when high byte is set."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_ld:10
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_st:9
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_ld:10
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_st:9
+msgid "Pointer register index."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_st:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_st:1
+msgid "Store Indirect from Register to Data Space (ST)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_st:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_st:4
+msgid "Operation: (X / Y / Z) <- Rr Status Register (SREG): None."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_lds:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_lds:1
+msgid "Load Direct from Data Space (LDS)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_lds:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_lds:4
+msgid "Operation: Rd <- (k) Status Register (SREG): None."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_lds:8
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sts:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_lds:8
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sts:7
+msgid "Memory address (0..ram_size-1)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sts:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sts:1
+msgid "Store Direct to Data Space (STS)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_sts:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_sts:4
+msgid "Operation: (k) <- Rr Status Register (SREG): None."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brne:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brne:1
+msgid "Branch if Not Equal (BRNE)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brne:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brne:4
+msgid "Operation: If Z = 0 then PC <- PC + k + 1 Status Register (SREG): None."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brcc:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brcs:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_breq:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brge:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brlo:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brlt:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brmi:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brne:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brpl:7
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brsh:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brcc:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brcs:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_breq:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brge:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brlo:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brlt:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brmi:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brne:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brpl:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brsh:7
+msgid "Jump target label or numeric address."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_breq:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_breq:1
+msgid "Branch if Equal (BREQ)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_breq:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_breq:4
+msgid "Operation: If Z = 1 then PC <- PC + k + 1 Status Register (SREG): None."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brcs:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brcs:1
+msgid "Branch if Carry Set (BRCS)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brcs:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brcs:4
+msgid "Operation: If C = 1 then PC <- PC + k + 1 Status Register (SREG): None."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brcc:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brcc:1
+msgid "Branch if Carry Cleared (BRCC)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brcc:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brcc:4
+msgid "Operation: If C = 0 then PC <- PC + k + 1 Status Register (SREG): None."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brlo:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brlo:1
+msgid "Branch if Lower Unsigned (BRLO)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brlo:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brlo:4
+msgid "Operation: If C = 1 then PC <- PC + k + 1 (alias for BRCS) Status Register (SREG): None."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brsh:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brsh:1
+msgid "Branch if Same or Higher Unsigned (BRSH)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brsh:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brsh:4
+msgid "Operation: If C = 0 then PC <- PC + k + 1 (alias for BRCC) Status Register (SREG): None."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brge:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brge:1
+msgid "Branch if Greater or Equal Signed (BRGE)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brge:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brge:4
+msgid "Operation: If S = 0 (N ⊕ V = 0) then PC <- PC + k + 1 Status Register (SREG): None."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brlt:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brlt:1
+msgid "Branch if Less Than Signed (BRLT)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brlt:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brlt:4
+msgid "Operation: If S = 1 (N ⊕ V = 1) then PC <- PC + k + 1 Status Register (SREG): None."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brmi:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brmi:1
+msgid "Branch if Minus (BRMI)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brmi:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brmi:4
+msgid "Operation: If N = 1 then PC <- PC + k + 1 Status Register (SREG): None."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brpl:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brpl:1
+msgid "Branch if Plus (BRPL)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_brpl:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_brpl:4
+msgid "Operation: If N = 0 then PC <- PC + k + 1 Status Register (SREG): None."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_push:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_push:1
+msgid "Push Register on Stack (PUSH)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_push:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_push:4
+msgid "Operation: STACK <- Rr, SP <- SP - 1 Status Register (SREG): None."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_pop:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_pop:1
+msgid "Pop Register from Stack (POP)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_pop:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_pop:4
+msgid "Operation: SP <- SP + 1, Rd <- STACK Status Register (SREG): None."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_call:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_call:1
+msgid "Long Call to Subroutine (CALL)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_call:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_call:4
+msgid "Operation: STACK <- PC + 1, PC <- k Status Register (SREG): None."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_call:7
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_call:7
+msgid "Subroutine target label or address."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_ret:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_ret:1
+msgid "Return from Subroutine (RET)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_ret:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_ret:4
+msgid "Operation: PC <- STACK Status Register (SREG): None."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_reti:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_reti:1
+msgid "Return from Interrupt (RETI)."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.op_reti:4
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.op_reti:4
+msgid "Operation: PC <- STACK, I <- 1 Status Register (SREG): I"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.trigger_interrupt:1
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.trigger_interrupt:1
+msgid "Trigger an interrupt if enabled in vector configuration."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU.trigger_interrupt:3
+#: ../../../src/tiny8/cpu.py:docstring of tiny8.cpu.CPU.trigger_interrupt:3
+msgid "Vector entry address in RAM."
+msgstr ""
+
+#: ../../api/tiny8.rst:40
+msgid "tiny8.memory module"
+msgstr ""
+
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory:1
+msgid "Memory model for tiny8 providing RAM and ROM with change tracking."
+msgstr ""
+
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory:1
+msgid "Byte-addressable RAM/ROM memory subsystem."
+msgstr ""
+
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory:3
+msgid "Maintains separate RAM and ROM buffers as 8-bit unsigned bytes (0-255) and logs modifications for tracing and visualization."
+msgstr ""
+
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory:6
+msgid "Number of bytes in RAM. Defaults to 65536."
+msgstr ""
+
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory:7
+msgid "Number of bytes in ROM. Defaults to 2048."
+msgstr ""
+
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory:11
+msgid "Size of RAM in bytes."
+msgstr ""
+
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory:15
+msgid "Size of ROM in bytes."
+msgstr ""
+
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory:19
+msgid "Bytearray representing RAM contents."
+msgstr ""
+
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory:23
+msgid "Bytearray representing ROM contents."
+msgstr ""
+
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory:27
+msgid "Log of RAM writes as (addr, old_val, new_val, step) tuples."
+msgstr ""
+
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory:31
+msgid "Log of ROM writes as (addr, old_val, new_val, step) tuples."
+msgstr ""
+
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory.read_ram:1
+msgid "Read a byte from RAM."
+msgstr ""
+
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory.read_ram:3
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory.write_ram:3
+msgid "Memory address in the range [0, ram_size)."
+msgstr ""
+
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory.read_ram:5
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory.read_rom:5
+msgid "The byte value stored at the address."
+msgstr ""
+
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory.read_ram:7
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory.write_ram:7
+msgid "If addr is outside valid RAM boundaries."
+msgstr ""
+
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory.write_ram:1
+msgid "Write a byte to RAM and log change if value changed."
+msgstr ""
+
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory.write_ram:4
+msgid "Byte value to store (masked to 8-bit)."
+msgstr ""
+
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory.write_ram:5
+msgid "Step index associated with this write. Defaults to 0."
+msgstr ""
+
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory.clear_changes:1
+msgid "Clear memory modification history to free memory."
+msgstr ""
+
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory.restore_ram:1
+msgid "Restore RAM contents from a dictionary of non-zero entries."
+msgstr ""
+
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory.load_rom:1
+msgid "Load byte sequence into ROM and record changes."
+msgstr ""
+
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory.load_rom:3
+msgid "Sequence of byte values to load into ROM."
+msgstr ""
+
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory.load_rom:5
+msgid "If data length exceeds configured rom_size."
+msgstr ""
+
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory.read_rom:1
+msgid "Read a byte from ROM."
+msgstr ""
+
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory.read_rom:3
+msgid "ROM address in the range [0, rom_size)."
+msgstr ""
+
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory.read_rom:7
+msgid "If addr is outside valid ROM boundaries."
+msgstr ""
+
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory.snapshot_ram:1
+msgid "Return a shallow copy of RAM contents."
+msgstr ""
+
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory.snapshot_ram:3
+msgid "List of integers representing current RAM."
+msgstr ""
+
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory.snapshot_rom:1
+msgid "Return a shallow copy of ROM contents."
+msgstr ""
+
+#: ../../../src/tiny8/memory.py:docstring of tiny8.memory.Memory.snapshot_rom:3
+msgid "List of integers representing current ROM."
+msgstr ""
+
+#: ../../api/tiny8.rst:48
+msgid "tiny8.tui module"
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui:1
+msgid "Modern Textual-based interactive debugger and dashboard for Tiny8."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui:3
+msgid "Provides an OLED black themed TUI with real-time registers, memory, SREG flags, gradient heatmap bars, stack explorer, breakpoints, and telemetry."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CheckpointManager:1
+msgid "Manages sparse snapshots and loop detection for time-travel."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CheckpointManager:3
+msgid "Stores complete CPU state snapshots every `interval` steps (default 100), enabling instant seeking and reverse playback without heavy RAM overhead."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CheckpointManager.record:1
+msgid "Store a CPU snapshot at the given step."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CheckpointManager.record_if_interval:1
+msgid "Record snapshot if step is a multiple of interval."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CheckpointManager.restore_exact_step:1
+msgid "Restore CPU to exact target_step using the closest preceding snapshot."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CheckpointManager.invalidate_after:1
+msgid "Invalidate checkpoints after modified step on memory/register edit."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CheckpointManager.detect_loop:1
+msgid "Detect infinite loop (e.g. self-jump HALT or cycling registers/PC)."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CheckpointManager.precompute:1
+msgid "Precompute execution checkpoints until an infinite loop or halt is detected."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.interpolate_color:1
+msgid "Interpolate RGB color matching authentic Viridis style."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.interpolate_color:3
+msgid "Float value from 0.0 to 1.0."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.interpolate_color:5
+msgid "Hex RGB color string (e.g. '#FDE725')."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.get_widget_available_lines:1
+msgid "Calculate visible content lines available for widget based on terminal/screen height."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.render_btop_bar:1
+msgid "Render horizontal gradient heatmap bar with trailing dot fill."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.render_btop_bar:3
+msgid "Current numerical value."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.render_btop_bar:4
+msgid "Upper scale limit."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.render_btop_bar:5
+msgid "Character width of bar."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.render_btop_bar:7
+msgid "Rich Text object containing gradient blocks and shade dots."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.BtopRegistersWidget:1
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CVariablesWidget:1
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CallStackWidget:1
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CodeViewWidget:1
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.InstructionDetailWidget:1
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.LazyStatusWidget:1
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.MemoryMatrixWidget:1
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.MemoryWidget:1
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.RegistersWidget:1
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.SregWidget:1
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.StackWidget:1
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.TelemetryWidget:1
+msgid "Bases: :py:class:`~textual.widgets._static.Static`"
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.SregWidget:1
+msgid "Badge-style display for SREG condition flags."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.prev_regs:1
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.regs:1
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.start_r:1
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.visible_count:1
+#: ../../../docstring of tiny8.tui.CVariablesWidget.mem:1
+#: ../../../docstring of tiny8.tui.CVariablesWidget.prev_mem:1
+#: ../../../docstring of tiny8.tui.CVariablesWidget.var_symbols:1
+#: ../../../docstring of tiny8.tui.CallStackWidget.current_pc:1
+#: ../../../docstring of tiny8.tui.CallStackWidget.frames:1
+#: ../../../docstring of tiny8.tui.CodeViewWidget.breakpoints:1
+#: ../../../docstring of tiny8.tui.CodeViewWidget.current_pc:1
+#: ../../../docstring of tiny8.tui.CodeViewWidget.pc_to_line:1
+#: ../../../docstring of tiny8.tui.CodeViewWidget.program:1
+#: ../../../docstring of tiny8.tui.CodeViewWidget.source_lines:1
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.current_instr:1
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.pc:1
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.source_line:1
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.source_text:1
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.sp:1
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_instr:1
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_pc:1
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_sp:1
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_step:1
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.filename:1
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.hint:1
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.mode:1
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.sub_info:1
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.total_steps:1
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.base_addr:1
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.mem:1
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.read_counts:1
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.write_counts:1
+#: ../../../docstring of tiny8.tui.MemoryWidget.color_mode:1
+#: ../../../docstring of tiny8.tui.MemoryWidget.mem:1
+#: ../../../docstring of tiny8.tui.MemoryWidget.prev_mem:1
+#: ../../../docstring of tiny8.tui.MemoryWidget.show_hex:1
+#: ../../../docstring of tiny8.tui.MemoryWidget.start_addr:1
+#: ../../../docstring of tiny8.tui.RegistersWidget.prev_regs:1
+#: ../../../docstring of tiny8.tui.RegistersWidget.regs:1
+#: ../../../docstring of tiny8.tui.SregWidget.sreg:1
+#: ../../../docstring of tiny8.tui.StackWidget.mem:1
+#: ../../../docstring of tiny8.tui.StackWidget.ram_size:1
+#: ../../../docstring of tiny8.tui.StackWidget.sp:1
+#: ../../../docstring of tiny8.tui.TelemetryWidget.current_step:1
+#: ../../../docstring of tiny8.tui.TelemetryWidget.instr_counts:1
+#: ../../../docstring of tiny8.tui.TelemetryWidget.total_steps:1
+#: ../../../docstring of tiny8.tui.Tiny8App.batch_size:1
+#: ../../../docstring of tiny8.tui.Tiny8App.breakpoints:1
+#: ../../../docstring of tiny8.tui.Tiny8App.color_mode:1
+#: ../../../docstring of tiny8.tui.Tiny8App.current_idx:1
+#: ../../../docstring of tiny8.tui.Tiny8App.execution_mode:1
+#: ../../../docstring of tiny8.tui.Tiny8App.mem_start:1
+#: ../../../docstring of tiny8.tui.Tiny8App.play_direction:1
+#: ../../../docstring of tiny8.tui.Tiny8App.playback_rate_idx:1
+#: ../../../docstring of tiny8.tui.Tiny8App.playing:1
+#: ../../../docstring of tiny8.tui.Tiny8App.reg_start:1
+#: ../../../docstring of tiny8.tui.Tiny8App.show_hex:1
+#: ../../../docstring of tiny8.tui.Tiny8App.speed_ms:1
+#: ../../../docstring of tiny8.tui.VimTextArea.is_modified:1
+#: ../../../docstring of tiny8.tui.VimTextArea.mode:1
+msgid "Create a reactive attribute."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.prev_regs:3
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.regs:3
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.start_r:3
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.visible_count:3
+#: ../../../docstring of tiny8.tui.CVariablesWidget.mem:3
+#: ../../../docstring of tiny8.tui.CVariablesWidget.prev_mem:3
+#: ../../../docstring of tiny8.tui.CVariablesWidget.var_symbols:3
+#: ../../../docstring of tiny8.tui.CallStackWidget.current_pc:3
+#: ../../../docstring of tiny8.tui.CallStackWidget.frames:3
+#: ../../../docstring of tiny8.tui.CodeViewWidget.breakpoints:3
+#: ../../../docstring of tiny8.tui.CodeViewWidget.current_pc:3
+#: ../../../docstring of tiny8.tui.CodeViewWidget.pc_to_line:3
+#: ../../../docstring of tiny8.tui.CodeViewWidget.program:3
+#: ../../../docstring of tiny8.tui.CodeViewWidget.source_lines:3
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.current_instr:3
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.pc:3
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.source_line:3
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.source_text:3
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.sp:3
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_instr:3
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_pc:3
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_sp:3
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_step:3
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.filename:3
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.hint:3
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.mode:3
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.sub_info:3
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.total_steps:3
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.base_addr:3
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.mem:3
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.read_counts:3
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.write_counts:3
+#: ../../../docstring of tiny8.tui.MemoryWidget.color_mode:3
+#: ../../../docstring of tiny8.tui.MemoryWidget.mem:3
+#: ../../../docstring of tiny8.tui.MemoryWidget.prev_mem:3
+#: ../../../docstring of tiny8.tui.MemoryWidget.show_hex:3
+#: ../../../docstring of tiny8.tui.MemoryWidget.start_addr:3
+#: ../../../docstring of tiny8.tui.RegistersWidget.prev_regs:3
+#: ../../../docstring of tiny8.tui.RegistersWidget.regs:3
+#: ../../../docstring of tiny8.tui.SregWidget.sreg:3
+#: ../../../docstring of tiny8.tui.StackWidget.mem:3
+#: ../../../docstring of tiny8.tui.StackWidget.ram_size:3
+#: ../../../docstring of tiny8.tui.StackWidget.sp:3
+#: ../../../docstring of tiny8.tui.TelemetryWidget.current_step:3
+#: ../../../docstring of tiny8.tui.TelemetryWidget.instr_counts:3
+#: ../../../docstring of tiny8.tui.TelemetryWidget.total_steps:3
+#: ../../../docstring of tiny8.tui.Tiny8App.batch_size:3
+#: ../../../docstring of tiny8.tui.Tiny8App.breakpoints:3
+#: ../../../docstring of tiny8.tui.Tiny8App.color_mode:3
+#: ../../../docstring of tiny8.tui.Tiny8App.current_idx:3
+#: ../../../docstring of tiny8.tui.Tiny8App.execution_mode:3
+#: ../../../docstring of tiny8.tui.Tiny8App.mem_start:3
+#: ../../../docstring of tiny8.tui.Tiny8App.play_direction:3
+#: ../../../docstring of tiny8.tui.Tiny8App.playback_rate_idx:3
+#: ../../../docstring of tiny8.tui.Tiny8App.playing:3
+#: ../../../docstring of tiny8.tui.Tiny8App.reg_start:3
+#: ../../../docstring of tiny8.tui.Tiny8App.show_hex:3
+#: ../../../docstring of tiny8.tui.Tiny8App.speed_ms:3
+#: ../../../docstring of tiny8.tui.VimTextArea.is_modified:3
+#: ../../../docstring of tiny8.tui.VimTextArea.mode:3
+msgid "A default value or callable that returns a default."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.prev_regs:4
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.regs:4
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.start_r:4
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.visible_count:4
+#: ../../../docstring of tiny8.tui.CVariablesWidget.mem:4
+#: ../../../docstring of tiny8.tui.CVariablesWidget.prev_mem:4
+#: ../../../docstring of tiny8.tui.CVariablesWidget.var_symbols:4
+#: ../../../docstring of tiny8.tui.CallStackWidget.current_pc:4
+#: ../../../docstring of tiny8.tui.CallStackWidget.frames:4
+#: ../../../docstring of tiny8.tui.CodeViewWidget.breakpoints:4
+#: ../../../docstring of tiny8.tui.CodeViewWidget.current_pc:4
+#: ../../../docstring of tiny8.tui.CodeViewWidget.pc_to_line:4
+#: ../../../docstring of tiny8.tui.CodeViewWidget.program:4
+#: ../../../docstring of tiny8.tui.CodeViewWidget.source_lines:4
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.current_instr:4
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.pc:4
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.source_line:4
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.source_text:4
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.sp:4
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_instr:4
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_pc:4
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_sp:4
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_step:4
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.filename:4
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.hint:4
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.mode:4
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.sub_info:4
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.total_steps:4
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.base_addr:4
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.mem:4
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.read_counts:4
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.write_counts:4
+#: ../../../docstring of tiny8.tui.MemoryWidget.color_mode:4
+#: ../../../docstring of tiny8.tui.MemoryWidget.mem:4
+#: ../../../docstring of tiny8.tui.MemoryWidget.prev_mem:4
+#: ../../../docstring of tiny8.tui.MemoryWidget.show_hex:4
+#: ../../../docstring of tiny8.tui.MemoryWidget.start_addr:4
+#: ../../../docstring of tiny8.tui.RegistersWidget.prev_regs:4
+#: ../../../docstring of tiny8.tui.RegistersWidget.regs:4
+#: ../../../docstring of tiny8.tui.SregWidget.sreg:4
+#: ../../../docstring of tiny8.tui.StackWidget.mem:4
+#: ../../../docstring of tiny8.tui.StackWidget.ram_size:4
+#: ../../../docstring of tiny8.tui.StackWidget.sp:4
+#: ../../../docstring of tiny8.tui.TelemetryWidget.current_step:4
+#: ../../../docstring of tiny8.tui.TelemetryWidget.instr_counts:4
+#: ../../../docstring of tiny8.tui.TelemetryWidget.total_steps:4
+#: ../../../docstring of tiny8.tui.Tiny8App.batch_size:4
+#: ../../../docstring of tiny8.tui.Tiny8App.breakpoints:4
+#: ../../../docstring of tiny8.tui.Tiny8App.color_mode:4
+#: ../../../docstring of tiny8.tui.Tiny8App.current_idx:4
+#: ../../../docstring of tiny8.tui.Tiny8App.execution_mode:4
+#: ../../../docstring of tiny8.tui.Tiny8App.mem_start:4
+#: ../../../docstring of tiny8.tui.Tiny8App.play_direction:4
+#: ../../../docstring of tiny8.tui.Tiny8App.playback_rate_idx:4
+#: ../../../docstring of tiny8.tui.Tiny8App.playing:4
+#: ../../../docstring of tiny8.tui.Tiny8App.reg_start:4
+#: ../../../docstring of tiny8.tui.Tiny8App.show_hex:4
+#: ../../../docstring of tiny8.tui.Tiny8App.speed_ms:4
+#: ../../../docstring of tiny8.tui.VimTextArea.is_modified:4
+#: ../../../docstring of tiny8.tui.VimTextArea.mode:4
+msgid "Perform a layout on change."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.prev_regs:5
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.regs:5
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.start_r:5
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.visible_count:5
+#: ../../../docstring of tiny8.tui.CVariablesWidget.mem:5
+#: ../../../docstring of tiny8.tui.CVariablesWidget.prev_mem:5
+#: ../../../docstring of tiny8.tui.CVariablesWidget.var_symbols:5
+#: ../../../docstring of tiny8.tui.CallStackWidget.current_pc:5
+#: ../../../docstring of tiny8.tui.CallStackWidget.frames:5
+#: ../../../docstring of tiny8.tui.CodeViewWidget.breakpoints:5
+#: ../../../docstring of tiny8.tui.CodeViewWidget.current_pc:5
+#: ../../../docstring of tiny8.tui.CodeViewWidget.pc_to_line:5
+#: ../../../docstring of tiny8.tui.CodeViewWidget.program:5
+#: ../../../docstring of tiny8.tui.CodeViewWidget.source_lines:5
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.current_instr:5
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.pc:5
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.source_line:5
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.source_text:5
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.sp:5
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_instr:5
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_pc:5
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_sp:5
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_step:5
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.filename:5
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.hint:5
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.mode:5
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.sub_info:5
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.total_steps:5
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.base_addr:5
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.mem:5
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.read_counts:5
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.write_counts:5
+#: ../../../docstring of tiny8.tui.MemoryWidget.color_mode:5
+#: ../../../docstring of tiny8.tui.MemoryWidget.mem:5
+#: ../../../docstring of tiny8.tui.MemoryWidget.prev_mem:5
+#: ../../../docstring of tiny8.tui.MemoryWidget.show_hex:5
+#: ../../../docstring of tiny8.tui.MemoryWidget.start_addr:5
+#: ../../../docstring of tiny8.tui.RegistersWidget.prev_regs:5
+#: ../../../docstring of tiny8.tui.RegistersWidget.regs:5
+#: ../../../docstring of tiny8.tui.SregWidget.sreg:5
+#: ../../../docstring of tiny8.tui.StackWidget.mem:5
+#: ../../../docstring of tiny8.tui.StackWidget.ram_size:5
+#: ../../../docstring of tiny8.tui.StackWidget.sp:5
+#: ../../../docstring of tiny8.tui.TelemetryWidget.current_step:5
+#: ../../../docstring of tiny8.tui.TelemetryWidget.instr_counts:5
+#: ../../../docstring of tiny8.tui.TelemetryWidget.total_steps:5
+#: ../../../docstring of tiny8.tui.Tiny8App.batch_size:5
+#: ../../../docstring of tiny8.tui.Tiny8App.breakpoints:5
+#: ../../../docstring of tiny8.tui.Tiny8App.color_mode:5
+#: ../../../docstring of tiny8.tui.Tiny8App.current_idx:5
+#: ../../../docstring of tiny8.tui.Tiny8App.execution_mode:5
+#: ../../../docstring of tiny8.tui.Tiny8App.mem_start:5
+#: ../../../docstring of tiny8.tui.Tiny8App.play_direction:5
+#: ../../../docstring of tiny8.tui.Tiny8App.playback_rate_idx:5
+#: ../../../docstring of tiny8.tui.Tiny8App.playing:5
+#: ../../../docstring of tiny8.tui.Tiny8App.reg_start:5
+#: ../../../docstring of tiny8.tui.Tiny8App.show_hex:5
+#: ../../../docstring of tiny8.tui.Tiny8App.speed_ms:5
+#: ../../../docstring of tiny8.tui.VimTextArea.is_modified:5
+#: ../../../docstring of tiny8.tui.VimTextArea.mode:5
+msgid "Perform a repaint on change."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.prev_regs:6
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.regs:6
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.start_r:6
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.visible_count:6
+#: ../../../docstring of tiny8.tui.CVariablesWidget.mem:6
+#: ../../../docstring of tiny8.tui.CVariablesWidget.prev_mem:6
+#: ../../../docstring of tiny8.tui.CVariablesWidget.var_symbols:6
+#: ../../../docstring of tiny8.tui.CallStackWidget.current_pc:6
+#: ../../../docstring of tiny8.tui.CallStackWidget.frames:6
+#: ../../../docstring of tiny8.tui.CodeViewWidget.breakpoints:6
+#: ../../../docstring of tiny8.tui.CodeViewWidget.current_pc:6
+#: ../../../docstring of tiny8.tui.CodeViewWidget.pc_to_line:6
+#: ../../../docstring of tiny8.tui.CodeViewWidget.program:6
+#: ../../../docstring of tiny8.tui.CodeViewWidget.source_lines:6
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.current_instr:6
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.pc:6
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.source_line:6
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.source_text:6
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.sp:6
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_instr:6
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_pc:6
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_sp:6
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_step:6
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.filename:6
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.hint:6
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.mode:6
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.sub_info:6
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.total_steps:6
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.base_addr:6
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.mem:6
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.read_counts:6
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.write_counts:6
+#: ../../../docstring of tiny8.tui.MemoryWidget.color_mode:6
+#: ../../../docstring of tiny8.tui.MemoryWidget.mem:6
+#: ../../../docstring of tiny8.tui.MemoryWidget.prev_mem:6
+#: ../../../docstring of tiny8.tui.MemoryWidget.show_hex:6
+#: ../../../docstring of tiny8.tui.MemoryWidget.start_addr:6
+#: ../../../docstring of tiny8.tui.RegistersWidget.prev_regs:6
+#: ../../../docstring of tiny8.tui.RegistersWidget.regs:6
+#: ../../../docstring of tiny8.tui.SregWidget.sreg:6
+#: ../../../docstring of tiny8.tui.StackWidget.mem:6
+#: ../../../docstring of tiny8.tui.StackWidget.ram_size:6
+#: ../../../docstring of tiny8.tui.StackWidget.sp:6
+#: ../../../docstring of tiny8.tui.TelemetryWidget.current_step:6
+#: ../../../docstring of tiny8.tui.TelemetryWidget.instr_counts:6
+#: ../../../docstring of tiny8.tui.TelemetryWidget.total_steps:6
+#: ../../../docstring of tiny8.tui.Tiny8App.batch_size:6
+#: ../../../docstring of tiny8.tui.Tiny8App.breakpoints:6
+#: ../../../docstring of tiny8.tui.Tiny8App.color_mode:6
+#: ../../../docstring of tiny8.tui.Tiny8App.current_idx:6
+#: ../../../docstring of tiny8.tui.Tiny8App.execution_mode:6
+#: ../../../docstring of tiny8.tui.Tiny8App.mem_start:6
+#: ../../../docstring of tiny8.tui.Tiny8App.play_direction:6
+#: ../../../docstring of tiny8.tui.Tiny8App.playback_rate_idx:6
+#: ../../../docstring of tiny8.tui.Tiny8App.playing:6
+#: ../../../docstring of tiny8.tui.Tiny8App.reg_start:6
+#: ../../../docstring of tiny8.tui.Tiny8App.show_hex:6
+#: ../../../docstring of tiny8.tui.Tiny8App.speed_ms:6
+#: ../../../docstring of tiny8.tui.VimTextArea.is_modified:6
+#: ../../../docstring of tiny8.tui.VimTextArea.mode:6
+msgid "Call watchers on initialize (post mount)."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.prev_regs:7
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.regs:7
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.start_r:7
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.visible_count:7
+#: ../../../docstring of tiny8.tui.CVariablesWidget.mem:7
+#: ../../../docstring of tiny8.tui.CVariablesWidget.prev_mem:7
+#: ../../../docstring of tiny8.tui.CVariablesWidget.var_symbols:7
+#: ../../../docstring of tiny8.tui.CallStackWidget.current_pc:7
+#: ../../../docstring of tiny8.tui.CallStackWidget.frames:7
+#: ../../../docstring of tiny8.tui.CodeViewWidget.breakpoints:7
+#: ../../../docstring of tiny8.tui.CodeViewWidget.current_pc:7
+#: ../../../docstring of tiny8.tui.CodeViewWidget.pc_to_line:7
+#: ../../../docstring of tiny8.tui.CodeViewWidget.program:7
+#: ../../../docstring of tiny8.tui.CodeViewWidget.source_lines:7
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.current_instr:7
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.pc:7
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.source_line:7
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.source_text:7
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.sp:7
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_instr:7
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_pc:7
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_sp:7
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_step:7
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.filename:7
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.hint:7
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.mode:7
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.sub_info:7
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.total_steps:7
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.base_addr:7
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.mem:7
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.read_counts:7
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.write_counts:7
+#: ../../../docstring of tiny8.tui.MemoryWidget.color_mode:7
+#: ../../../docstring of tiny8.tui.MemoryWidget.mem:7
+#: ../../../docstring of tiny8.tui.MemoryWidget.prev_mem:7
+#: ../../../docstring of tiny8.tui.MemoryWidget.show_hex:7
+#: ../../../docstring of tiny8.tui.MemoryWidget.start_addr:7
+#: ../../../docstring of tiny8.tui.RegistersWidget.prev_regs:7
+#: ../../../docstring of tiny8.tui.RegistersWidget.regs:7
+#: ../../../docstring of tiny8.tui.SregWidget.sreg:7
+#: ../../../docstring of tiny8.tui.StackWidget.mem:7
+#: ../../../docstring of tiny8.tui.StackWidget.ram_size:7
+#: ../../../docstring of tiny8.tui.StackWidget.sp:7
+#: ../../../docstring of tiny8.tui.TelemetryWidget.current_step:7
+#: ../../../docstring of tiny8.tui.TelemetryWidget.instr_counts:7
+#: ../../../docstring of tiny8.tui.TelemetryWidget.total_steps:7
+#: ../../../docstring of tiny8.tui.Tiny8App.batch_size:7
+#: ../../../docstring of tiny8.tui.Tiny8App.breakpoints:7
+#: ../../../docstring of tiny8.tui.Tiny8App.color_mode:7
+#: ../../../docstring of tiny8.tui.Tiny8App.current_idx:7
+#: ../../../docstring of tiny8.tui.Tiny8App.execution_mode:7
+#: ../../../docstring of tiny8.tui.Tiny8App.mem_start:7
+#: ../../../docstring of tiny8.tui.Tiny8App.play_direction:7
+#: ../../../docstring of tiny8.tui.Tiny8App.playback_rate_idx:7
+#: ../../../docstring of tiny8.tui.Tiny8App.playing:7
+#: ../../../docstring of tiny8.tui.Tiny8App.reg_start:7
+#: ../../../docstring of tiny8.tui.Tiny8App.show_hex:7
+#: ../../../docstring of tiny8.tui.Tiny8App.speed_ms:7
+#: ../../../docstring of tiny8.tui.VimTextArea.is_modified:7
+#: ../../../docstring of tiny8.tui.VimTextArea.mode:7
+msgid "Call watchers even when the new value equals the old value."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.prev_regs:8
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.regs:8
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.start_r:8
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.visible_count:8
+#: ../../../docstring of tiny8.tui.CVariablesWidget.mem:8
+#: ../../../docstring of tiny8.tui.CVariablesWidget.prev_mem:8
+#: ../../../docstring of tiny8.tui.CVariablesWidget.var_symbols:8
+#: ../../../docstring of tiny8.tui.CallStackWidget.current_pc:8
+#: ../../../docstring of tiny8.tui.CallStackWidget.frames:8
+#: ../../../docstring of tiny8.tui.CodeViewWidget.breakpoints:8
+#: ../../../docstring of tiny8.tui.CodeViewWidget.current_pc:8
+#: ../../../docstring of tiny8.tui.CodeViewWidget.pc_to_line:8
+#: ../../../docstring of tiny8.tui.CodeViewWidget.program:8
+#: ../../../docstring of tiny8.tui.CodeViewWidget.source_lines:8
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.current_instr:8
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.pc:8
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.source_line:8
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.source_text:8
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.sp:8
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_instr:8
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_pc:8
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_sp:8
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_step:8
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.filename:8
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.hint:8
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.mode:8
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.sub_info:8
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.total_steps:8
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.base_addr:8
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.mem:8
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.read_counts:8
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.write_counts:8
+#: ../../../docstring of tiny8.tui.MemoryWidget.color_mode:8
+#: ../../../docstring of tiny8.tui.MemoryWidget.mem:8
+#: ../../../docstring of tiny8.tui.MemoryWidget.prev_mem:8
+#: ../../../docstring of tiny8.tui.MemoryWidget.show_hex:8
+#: ../../../docstring of tiny8.tui.MemoryWidget.start_addr:8
+#: ../../../docstring of tiny8.tui.RegistersWidget.prev_regs:8
+#: ../../../docstring of tiny8.tui.RegistersWidget.regs:8
+#: ../../../docstring of tiny8.tui.SregWidget.sreg:8
+#: ../../../docstring of tiny8.tui.StackWidget.mem:8
+#: ../../../docstring of tiny8.tui.StackWidget.ram_size:8
+#: ../../../docstring of tiny8.tui.StackWidget.sp:8
+#: ../../../docstring of tiny8.tui.TelemetryWidget.current_step:8
+#: ../../../docstring of tiny8.tui.TelemetryWidget.instr_counts:8
+#: ../../../docstring of tiny8.tui.TelemetryWidget.total_steps:8
+#: ../../../docstring of tiny8.tui.Tiny8App.batch_size:8
+#: ../../../docstring of tiny8.tui.Tiny8App.breakpoints:8
+#: ../../../docstring of tiny8.tui.Tiny8App.color_mode:8
+#: ../../../docstring of tiny8.tui.Tiny8App.current_idx:8
+#: ../../../docstring of tiny8.tui.Tiny8App.execution_mode:8
+#: ../../../docstring of tiny8.tui.Tiny8App.mem_start:8
+#: ../../../docstring of tiny8.tui.Tiny8App.play_direction:8
+#: ../../../docstring of tiny8.tui.Tiny8App.playback_rate_idx:8
+#: ../../../docstring of tiny8.tui.Tiny8App.playing:8
+#: ../../../docstring of tiny8.tui.Tiny8App.reg_start:8
+#: ../../../docstring of tiny8.tui.Tiny8App.show_hex:8
+#: ../../../docstring of tiny8.tui.Tiny8App.speed_ms:8
+#: ../../../docstring of tiny8.tui.VimTextArea.is_modified:8
+#: ../../../docstring of tiny8.tui.VimTextArea.mode:8
+msgid "Compose the widget again when the attribute changes."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.prev_regs:9
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.regs:9
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.start_r:9
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.visible_count:9
+#: ../../../docstring of tiny8.tui.CVariablesWidget.mem:9
+#: ../../../docstring of tiny8.tui.CVariablesWidget.prev_mem:9
+#: ../../../docstring of tiny8.tui.CVariablesWidget.var_symbols:9
+#: ../../../docstring of tiny8.tui.CallStackWidget.current_pc:9
+#: ../../../docstring of tiny8.tui.CallStackWidget.frames:9
+#: ../../../docstring of tiny8.tui.CodeViewWidget.breakpoints:9
+#: ../../../docstring of tiny8.tui.CodeViewWidget.current_pc:9
+#: ../../../docstring of tiny8.tui.CodeViewWidget.pc_to_line:9
+#: ../../../docstring of tiny8.tui.CodeViewWidget.program:9
+#: ../../../docstring of tiny8.tui.CodeViewWidget.source_lines:9
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.current_instr:9
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.pc:9
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.source_line:9
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.source_text:9
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.sp:9
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_instr:9
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_pc:9
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_sp:9
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_step:9
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.filename:9
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.hint:9
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.mode:9
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.sub_info:9
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.total_steps:9
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.base_addr:9
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.mem:9
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.read_counts:9
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.write_counts:9
+#: ../../../docstring of tiny8.tui.MemoryWidget.color_mode:9
+#: ../../../docstring of tiny8.tui.MemoryWidget.mem:9
+#: ../../../docstring of tiny8.tui.MemoryWidget.prev_mem:9
+#: ../../../docstring of tiny8.tui.MemoryWidget.show_hex:9
+#: ../../../docstring of tiny8.tui.MemoryWidget.start_addr:9
+#: ../../../docstring of tiny8.tui.RegistersWidget.prev_regs:9
+#: ../../../docstring of tiny8.tui.RegistersWidget.regs:9
+#: ../../../docstring of tiny8.tui.SregWidget.sreg:9
+#: ../../../docstring of tiny8.tui.StackWidget.mem:9
+#: ../../../docstring of tiny8.tui.StackWidget.ram_size:9
+#: ../../../docstring of tiny8.tui.StackWidget.sp:9
+#: ../../../docstring of tiny8.tui.TelemetryWidget.current_step:9
+#: ../../../docstring of tiny8.tui.TelemetryWidget.instr_counts:9
+#: ../../../docstring of tiny8.tui.TelemetryWidget.total_steps:9
+#: ../../../docstring of tiny8.tui.Tiny8App.batch_size:9
+#: ../../../docstring of tiny8.tui.Tiny8App.breakpoints:9
+#: ../../../docstring of tiny8.tui.Tiny8App.color_mode:9
+#: ../../../docstring of tiny8.tui.Tiny8App.current_idx:9
+#: ../../../docstring of tiny8.tui.Tiny8App.execution_mode:9
+#: ../../../docstring of tiny8.tui.Tiny8App.mem_start:9
+#: ../../../docstring of tiny8.tui.Tiny8App.play_direction:9
+#: ../../../docstring of tiny8.tui.Tiny8App.playback_rate_idx:9
+#: ../../../docstring of tiny8.tui.Tiny8App.playing:9
+#: ../../../docstring of tiny8.tui.Tiny8App.reg_start:9
+#: ../../../docstring of tiny8.tui.Tiny8App.show_hex:9
+#: ../../../docstring of tiny8.tui.Tiny8App.speed_ms:9
+#: ../../../docstring of tiny8.tui.VimTextArea.is_modified:9
+#: ../../../docstring of tiny8.tui.VimTextArea.mode:9
+msgid "Refresh bindings when the reactive changes."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.prev_regs:10
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.regs:10
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.start_r:10
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.visible_count:10
+#: ../../../docstring of tiny8.tui.CVariablesWidget.mem:10
+#: ../../../docstring of tiny8.tui.CVariablesWidget.prev_mem:10
+#: ../../../docstring of tiny8.tui.CVariablesWidget.var_symbols:10
+#: ../../../docstring of tiny8.tui.CallStackWidget.current_pc:10
+#: ../../../docstring of tiny8.tui.CallStackWidget.frames:10
+#: ../../../docstring of tiny8.tui.CodeViewWidget.breakpoints:10
+#: ../../../docstring of tiny8.tui.CodeViewWidget.current_pc:10
+#: ../../../docstring of tiny8.tui.CodeViewWidget.pc_to_line:10
+#: ../../../docstring of tiny8.tui.CodeViewWidget.program:10
+#: ../../../docstring of tiny8.tui.CodeViewWidget.source_lines:10
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.current_instr:10
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.pc:10
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.source_line:10
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.source_text:10
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.sp:10
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_instr:10
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_pc:10
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_sp:10
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.current_step:10
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.filename:10
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.hint:10
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.mode:10
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.sub_info:10
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.total_steps:10
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.base_addr:10
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.mem:10
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.read_counts:10
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.write_counts:10
+#: ../../../docstring of tiny8.tui.MemoryWidget.color_mode:10
+#: ../../../docstring of tiny8.tui.MemoryWidget.mem:10
+#: ../../../docstring of tiny8.tui.MemoryWidget.prev_mem:10
+#: ../../../docstring of tiny8.tui.MemoryWidget.show_hex:10
+#: ../../../docstring of tiny8.tui.MemoryWidget.start_addr:10
+#: ../../../docstring of tiny8.tui.RegistersWidget.prev_regs:10
+#: ../../../docstring of tiny8.tui.RegistersWidget.regs:10
+#: ../../../docstring of tiny8.tui.SregWidget.sreg:10
+#: ../../../docstring of tiny8.tui.StackWidget.mem:10
+#: ../../../docstring of tiny8.tui.StackWidget.ram_size:10
+#: ../../../docstring of tiny8.tui.StackWidget.sp:10
+#: ../../../docstring of tiny8.tui.TelemetryWidget.current_step:10
+#: ../../../docstring of tiny8.tui.TelemetryWidget.instr_counts:10
+#: ../../../docstring of tiny8.tui.TelemetryWidget.total_steps:10
+#: ../../../docstring of tiny8.tui.Tiny8App.batch_size:10
+#: ../../../docstring of tiny8.tui.Tiny8App.breakpoints:10
+#: ../../../docstring of tiny8.tui.Tiny8App.color_mode:10
+#: ../../../docstring of tiny8.tui.Tiny8App.current_idx:10
+#: ../../../docstring of tiny8.tui.Tiny8App.execution_mode:10
+#: ../../../docstring of tiny8.tui.Tiny8App.mem_start:10
+#: ../../../docstring of tiny8.tui.Tiny8App.play_direction:10
+#: ../../../docstring of tiny8.tui.Tiny8App.playback_rate_idx:10
+#: ../../../docstring of tiny8.tui.Tiny8App.playing:10
+#: ../../../docstring of tiny8.tui.Tiny8App.reg_start:10
+#: ../../../docstring of tiny8.tui.Tiny8App.show_hex:10
+#: ../../../docstring of tiny8.tui.Tiny8App.speed_ms:10
+#: ../../../docstring of tiny8.tui.VimTextArea.is_modified:10
+#: ../../../docstring of tiny8.tui.VimTextArea.mode:10
+msgid "An optional TCSS classname(s) to toggle based on the truthiness of the value."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.BtopRegistersWidget.render:1
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CVariablesWidget.render:1
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CallStackWidget.render:1
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CodeViewWidget.render:1
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.InstructionDetailWidget.render:1
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.LazyStatusWidget.render:1
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.MemoryMatrixWidget.render:1
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.MemoryWidget.render:1
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.RegistersWidget.render:1
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.SregWidget.render:1
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.StackWidget.render:1
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.TelemetryWidget.render:1
+msgid "Get a rich renderable for the widget's content."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.BtopRegistersWidget.render:3
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CVariablesWidget.render:3
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CallStackWidget.render:3
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CodeViewWidget.render:3
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.InstructionDetailWidget.render:3
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.LazyStatusWidget.render:3
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.MemoryMatrixWidget.render:3
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.MemoryWidget.render:3
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.RegistersWidget.render:3
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.SregWidget.render:3
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.StackWidget.render:3
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.TelemetryWidget.render:3
+msgid "A rich renderable."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.can_focus:1
+#: ../../../docstring of tiny8.tui.CVariablesWidget.can_focus:1
+#: ../../../docstring of tiny8.tui.CacheProgressModalScreen.can_focus:1
+#: ../../../docstring of tiny8.tui.CallStackWidget.can_focus:1
+#: ../../../docstring of tiny8.tui.CodeViewWidget.can_focus:1
+#: ../../../docstring of tiny8.tui.InstructionDetailModalScreen.can_focus:1
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.can_focus:1
+#: ../../../docstring of tiny8.tui.InstructionReferenceScreen.can_focus:1
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.can_focus:1
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.can_focus:1
+#: ../../../docstring of tiny8.tui.MemoryWidget.can_focus:1
+#: ../../../docstring of tiny8.tui.RegistersWidget.can_focus:1
+#: ../../../docstring of tiny8.tui.SregWidget.can_focus:1
+#: ../../../docstring of tiny8.tui.StackWidget.can_focus:1
+#: ../../../docstring of tiny8.tui.TUIHelpScreen.can_focus:1
+#: ../../../docstring of tiny8.tui.TelemetryWidget.can_focus:1
+#: ../../../docstring of tiny8.tui.VimEditorScreen.can_focus:1
+#: ../../../docstring of tiny8.tui.VimTextArea.can_focus:1
+msgid "Widget may receive focus."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.BtopRegistersWidget.can_focus_children:1
+#: ../../../docstring of tiny8.tui.CVariablesWidget.can_focus_children:1
+#: ../../../docstring of tiny8.tui.CacheProgressModalScreen.can_focus_children:1
+#: ../../../docstring of tiny8.tui.CallStackWidget.can_focus_children:1
+#: ../../../docstring of tiny8.tui.CodeViewWidget.can_focus_children:1
+#: ../../../docstring of tiny8.tui.InstructionDetailModalScreen.can_focus_children:1
+#: ../../../docstring of tiny8.tui.InstructionDetailWidget.can_focus_children:1
+#: ../../../docstring of tiny8.tui.InstructionReferenceScreen.can_focus_children:1
+#: ../../../docstring of tiny8.tui.LazyStatusWidget.can_focus_children:1
+#: ../../../docstring of tiny8.tui.MemoryMatrixWidget.can_focus_children:1
+#: ../../../docstring of tiny8.tui.MemoryWidget.can_focus_children:1
+#: ../../../docstring of tiny8.tui.RegistersWidget.can_focus_children:1
+#: ../../../docstring of tiny8.tui.SregWidget.can_focus_children:1
+#: ../../../docstring of tiny8.tui.StackWidget.can_focus_children:1
+#: ../../../docstring of tiny8.tui.TUIHelpScreen.can_focus_children:1
+#: ../../../docstring of tiny8.tui.TelemetryWidget.can_focus_children:1
+#: ../../../docstring of tiny8.tui.VimEditorScreen.can_focus_children:1
+#: ../../../docstring of tiny8.tui.VimTextArea.can_focus_children:1
+msgid "Widget's children may receive focus."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.BtopRegistersWidget:1
+msgid "Register bars with graphical gradient heatmaps in a 2-column layout."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.RegistersWidget:1
+msgid "Grid displaying 32 8-bit general purpose registers."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.MemoryWidget:1
+msgid "32x32 Memory Dump with rich heatmap background coloring for direct visual rendering."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.MemoryWidget.get_heatmap_bg:1
+msgid "Calculate rich heat color background for byte value 0..255."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.StackWidget:1
+msgid "Call stack and stack pointer inspector."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.InstructionDetailWidget:1
+msgid "Deep-dive inspector displaying current instruction details, syntax, and effects."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.TelemetryWidget:1
+msgid "Real-time execution metrics and instruction distribution dashboard."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CodeViewWidget:1
+msgid "Assembly and source line inspection with execution pointer and breakpoints."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.eval_condition:1
+msgid "Safely evaluate debugger watch and conditional breakpoint expressions."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.extract_call_frames:1
+msgid "Reconstruct active function call frames up to current trace index."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CVariablesWidget:1
+msgid "Live C variable table showing symbol names, addresses, and runtime values."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CallStackWidget:1
+msgid "Dynamic function backtrace reconstructed from execution calls and returns."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.MemoryMatrixWidget:1
+msgid "2D RAM access heatmap showing read and write activity across addresses."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CacheProgressModalScreen:1
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.InstructionDetailModalScreen:1
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.InstructionReferenceScreen:1
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.TUIHelpScreen:1
+msgid "Bases: :py:class:`~textual.screen.ModalScreen`"
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CacheProgressModalScreen:1
+msgid "Sleek modal dialog displaying a progress bar while precomputing cache checkpoints."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.CacheProgressModalScreen.CSS:1
+#: ../../../docstring of tiny8.tui.InstructionDetailModalScreen.CSS:1
+#: ../../../docstring of tiny8.tui.InstructionReferenceScreen.CSS:1
+#: ../../../docstring of tiny8.tui.TUIHelpScreen.CSS:1
+#: ../../../docstring of tiny8.tui.VimEditorScreen.CSS:1
+msgid "Inline CSS, useful for quick scripts. Rules here take priority over CSS_PATH."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.CacheProgressModalScreen.CSS:3
+#: ../../../docstring of tiny8.tui.InstructionDetailModalScreen.CSS:3
+#: ../../../docstring of tiny8.tui.InstructionReferenceScreen.CSS:3
+#: ../../../docstring of tiny8.tui.TUIHelpScreen.CSS:3
+#: ../../../docstring of tiny8.tui.VimEditorScreen.CSS:3
+msgid "This CSS applies to the whole app."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CacheProgressModalScreen.__init__:1
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.InstructionDetailModalScreen.__init__:1
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.VimEditorScreen.__init__:1
+msgid "Initialize the screen."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CacheProgressModalScreen.__init__:3
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.InstructionDetailModalScreen.__init__:3
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.VimEditorScreen.__init__:3
+msgid "The name of the screen."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CacheProgressModalScreen.__init__:4
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.InstructionDetailModalScreen.__init__:4
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.VimEditorScreen.__init__:4
+msgid "The ID of the screen in the DOM."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CacheProgressModalScreen.__init__:5
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.InstructionDetailModalScreen.__init__:5
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.VimEditorScreen.__init__:5
+msgid "The CSS classes for the screen."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.CacheProgressModalScreen.compose:1
+msgid "Compose modal progress bar widgets."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.TUIHelpScreen:1
+msgid "Full-screen modal displaying TUI application usage, keyboard shortcuts, and guides."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.TUIHelpScreen.compose:1
+msgid "Compose help screen dialog widgets."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.InstructionDetailModalScreen:1
+msgid "Full-screen modal displaying in-depth specifications for the currently selected instruction."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.InstructionDetailModalScreen.compose:1
+msgid "Compose instruction detail modal widgets."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.InstructionReferenceScreen:1
+msgid "Full-screen reference modal showing all instruction details."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.InstructionReferenceScreen.compose:1
+msgid "Compose instruction reference modal widgets."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.LazyStatusWidget:1
+msgid "Bottom statusline with mode badge, file stats, and help hint."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.VimTextArea:1
+msgid "Bases: :py:class:`~textual.widgets._text_area.TextArea`"
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.VimTextArea:1
+msgid "TextArea enhanced with Vim modal navigation and editing."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.VimEditorScreen:1
+msgid "Bases: :py:class:`~textual.screen.Screen`"
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.VimEditorScreen:1
+msgid "Full-screen modal Vim editor for creating and modifying C and ASM files."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.VimEditorScreen.BINDINGS:1
+msgid "A list of key bindings."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.VimEditorScreen.compose:1
+msgid "Compose widgets for the Vim editor screen."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App:1
+msgid "Bases: :py:class:`~textual.app.App`"
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App:1
+msgid "Textual application with OLED black background and advanced debugger features."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.Tiny8App.TITLE:1
+msgid "A class variable to set the *default* title for the application."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.Tiny8App.TITLE:3
+msgid "To update the title while the app is running, you can set the [title][textual.app.App.title] attribute. See also [the `Screen.TITLE` attribute][textual.screen.Screen.TITLE]."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.Tiny8App.CSS:1
+msgid "Inline CSS, useful for quick scripts. This is loaded after CSS_PATH, and therefore takes priority in the event of a specificity clash."
+msgstr ""
+
+#: ../../../docstring of tiny8.tui.Tiny8App.BINDINGS:1
+msgid "The default key bindings."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.__init__:1
+msgid "Create an instance of an app."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.__init__:3
+msgid "Driver class or `None` to auto-detect. This will be used by some Textual tools."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.__init__:5
+msgid "Path to CSS or `None` to use the `CSS_PATH` class variable. To load multiple CSS files, pass a list of strings or paths which will be loaded in order."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.__init__:8
+msgid "Reload CSS if the files changed. This is set automatically if you are using `textual run` with the `dev` switch."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.__init__:10
+msgid "Allow ANSI colors if `True`, or convert ANSI colors to RGB if `False`, `None` to use \"ansi\" parameter from themes."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.__init__:12
+msgid "When the supplied CSS path(s) are an unexpected type."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.compose:1
+msgid "Compose the root application layout and widgets."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_open_editor:1
+msgid "Open full-screen Vim editor for source code."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_toggle_breakpoint:1
+msgid "Toggle breakpoint on current PC."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_continue_run:1
+msgid "Run forward until next breakpoint, watchpoint, or program completion."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_reverse_continue:1
+msgid "Run backward until previous breakpoint, watchpoint, or program start."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_exec_instruction:1
+msgid "Execute an assembly instruction dynamically in REPL mode."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.watch_mem_start:1
+msgid "Update only the memory widget when mem_start changes."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_scroll_down:1
+msgid "Scroll memory down (1 row = 32 bytes)."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_scroll_up:1
+msgid "Scroll memory up (1 row = 32 bytes)."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_scroll_page_down:1
+msgid "Fast scroll memory down (4 rows = 128 bytes)."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_scroll_page_up:1
+msgid "Fast scroll memory up (4 rows = 128 bytes)."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_open_command:1
+msgid "Open command bar input."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_cancel_command:1
+msgid "Cancel and close command input or dismiss modal dialog."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.on_input_submitted:1
+msgid "Process entered command."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_toggle_grayscale:1
+msgid "Toggle between Viridis and Grayscale color palette."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_toggle_hex:1
+msgid "Toggle between Hexadecimal digits (02X) and Graphic Pixel blocks."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_cycle_mode:1
+msgid "Cycle view modes (Viridis+Hex -> Viridis+Pixel -> Grayscale+Pixel -> Grayscale+Hex)."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_show_help:1
+msgid "Show full TUI application usage and keyboard guide."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_show_instruction_detail:1
+msgid "Show in-depth specification and effects for the currently selected instruction."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_show_reference:1
+msgid "Show full instruction set reference modal."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_toggle_play:1
+msgid "Toggle forward automatic playback."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_toggle_reverse_play:1
+msgid "Toggle reverse automatic playback (time-travel replay)."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_faster:1
+msgid "Increase playback execution speed."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_faster:3
+msgid "Decreases timer interval down to visual limit (30ms / ~33 fps), then automatically transitions to adaptive batch processing scaling up to 50,000 steps per tick."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_slower:1
+msgid "Decrease playback execution speed."
+msgstr ""
+
+#: ../../../src/tiny8/tui.py:docstring of tiny8.tui.Tiny8App.action_slower:3
+msgid "Scales down batch processing first, then transitions back to observable visual delay."
+msgstr ""
+
+#: ../../api/tiny8.rst:56
+msgid "tiny8.utils module"
+msgstr ""
+
+#: ../../../src/tiny8/utils.py:docstring of tiny8.utils:1
+msgid "Utility helpers for tiny8 including terminal progress bar."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.utils.ProgressBar:1
+#: ../../../src/tiny8/utils.py:docstring of tiny8.utils.ProgressBar:1
+msgid "Terminal progress bar indicator adapting to terminal width."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.utils.ProgressBar:3
+#: ../../../src/tiny8/utils.py:docstring of tiny8.utils.ProgressBar:3
+msgid "Total number of iterations, or None for indeterminate progress."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.utils.ProgressBar:4
+#: ../../../src/tiny8/utils.py:docstring of tiny8.utils.ProgressBar:4
+msgid "Prefix description string. Defaults to \"\"."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.utils.ProgressBar:5
+#: ../../../src/tiny8/utils.py:docstring of tiny8.utils.ProgressBar:5
+msgid "True to disable output completely. Defaults to False."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.utils.ProgressBar:6
+#: ../../../src/tiny8/utils.py:docstring of tiny8.utils.ProgressBar:6
+msgid "Explicit width in characters, or None for auto-detection."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.utils.ProgressBar:7
+#: ../../../src/tiny8/utils.py:docstring of tiny8.utils.ProgressBar:7
+msgid "Minimum interval in seconds between screen refreshes."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.utils.ProgressBar:11
+#: ../../../src/tiny8/utils.py:docstring of tiny8.utils.ProgressBar:11
+msgid "Total iterations expected."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.utils.ProgressBar:15
+#: ../../../src/tiny8/utils.py:docstring of tiny8.utils.ProgressBar:15
+msgid "Description prefix text."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.utils.ProgressBar:19
+#: ../../../src/tiny8/utils.py:docstring of tiny8.utils.ProgressBar:19
+msgid "Flag controlling output suppression."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.utils.ProgressBar:23
+#: ../../../src/tiny8/utils.py:docstring of tiny8.utils.ProgressBar:23
+msgid "Target bar character width."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.utils.ProgressBar:27
+#: ../../../src/tiny8/utils.py:docstring of tiny8.utils.ProgressBar:27
+msgid "Refresh rate throttle in seconds."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.utils.ProgressBar:31
+#: ../../../src/tiny8/utils.py:docstring of tiny8.utils.ProgressBar:31
+msgid "Current iteration step count."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.utils.ProgressBar:35
+#: ../../../src/tiny8/utils.py:docstring of tiny8.utils.ProgressBar:35
+msgid "Monotonic start timestamp."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.utils.ProgressBar:39
+#: ../../../src/tiny8/utils.py:docstring of tiny8.utils.ProgressBar:39
+msgid "Timestamp of last bar render."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.utils.ProgressBar.__enter__:1
+#: ../../../src/tiny8/utils.py:docstring of tiny8.utils.ProgressBar.__enter__:1
+msgid "Enter context manager."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.utils.ProgressBar.__exit__:1
+#: ../../../src/tiny8/utils.py:docstring of tiny8.utils.ProgressBar.__exit__:1
+msgid "Exit context manager and flush output."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.utils.ProgressBar.update:1
+#: ../../../src/tiny8/utils.py:docstring of tiny8.utils.ProgressBar.update:1
+msgid "Increment progress by n steps."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.utils.ProgressBar.update:3
+#: ../../../src/tiny8/utils.py:docstring of tiny8.utils.ProgressBar.update:3
+msgid "Number of iterations to increment. Defaults to 1."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.utils.ProgressBar.set_description:1
+#: ../../../src/tiny8/utils.py:docstring of tiny8.utils.ProgressBar.set_description:1
+msgid "Update description prefix and re-render bar."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.utils.ProgressBar.set_description:3
+#: ../../../src/tiny8/utils.py:docstring of tiny8.utils.ProgressBar.set_description:3
+msgid "New description text."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.utils.ProgressBar.close:1
+#: ../../../src/tiny8/utils.py:docstring of tiny8.utils.ProgressBar.close:1
+msgid "Finalize progress bar and print trailing newline."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.utils.ProgressBar.reset:1
+#: ../../../src/tiny8/utils.py:docstring of tiny8.utils.ProgressBar.reset:1
+msgid "Reset progress counter and timers to initial state."
+msgstr ""
+
+#: ../../api/tiny8.rst:64
+msgid "Module contents"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8:1
+msgid "A tiny AVR-like 8-bit CPU simulator package."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8:3
+msgid "Provides a compact CPU implementation, assembler, C compiler, and interactive Textual CLI for experimentation and teaching."
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU:13
+msgid "list[int]"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU:19
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU:25
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU:31
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU:37
+msgid "int"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU:43
+msgid "dict[int, bool]"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU:49
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU:55
+msgid "collections.deque[tuple[int, int, int]]"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU:61
+msgid "collections.deque[dict]"
+msgstr ""
+
+#: ../../../src/tiny8/__init__.py:docstring of tiny8.cpu.CPU:91
+msgid "bool"
+msgstr ""
diff --git a/docs/locales/pot/architecture.pot b/docs/locales/pot/architecture.pot
new file mode 100644
index 0000000..f4a1338
--- /dev/null
+++ b/docs/locales/pot/architecture.pot
@@ -0,0 +1,751 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-25 01:27+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../architecture.rst:2
+msgid "Architecture"
+msgstr ""
+
+#: ../../architecture.rst:4
+msgid "This guide provides a detailed overview of the Tiny8 CPU architecture, including its registers, memory model, instruction execution, and status flags."
+msgstr ""
+
+#: ../../architecture.rst:7
+msgid "CPU Overview"
+msgstr ""
+
+#: ../../architecture.rst:9
+msgid "Tiny8 implements an 8-bit RISC CPU architecture modeled directly after the Atmel / Microchip AVR instruction set architecture. Instruction semantics, flag behaviors, and operations strictly adhere to the official specification:"
+msgstr ""
+
+#: ../../architecture.rst:11
+msgid "**Official Specification**: `Microchip AVR® Instruction Set Manual (DS40002198A) <https://ww1.microchip.com/downloads/en/DeviceDoc/AVR-Instruction-Set-Manual-DS40002198A.pdf>`_"
+msgstr ""
+
+#: ../../architecture.rst:13
+msgid "The design balances hardware realism with educational clarity, providing full visibility and interactive step debugging."
+msgstr ""
+
+#: ../../architecture.rst:16
+msgid "Key Specifications"
+msgstr ""
+
+#: ../../architecture.rst:18
+msgid "**Word size**: 8 bits"
+msgstr ""
+
+#: ../../architecture.rst:19
+msgid "**Registers**: 32 general-purpose 8-bit registers (R0-R31)"
+msgstr ""
+
+#: ../../architecture.rst:20
+msgid "**Memory**: 64KB RAM (configurable)"
+msgstr ""
+
+#: ../../architecture.rst:21
+msgid "**Stack**: Grows downward from high memory (SP decrements on push)"
+msgstr ""
+
+#: ../../architecture.rst:22
+msgid "**Instruction set**: 67 instructions compliant with AVR DS40002198A"
+msgstr ""
+
+#: ../../architecture.rst:23
+msgid "**Status register**: 8 flags (SREG: I, T, H, S, V, N, Z, C)"
+msgstr ""
+
+#: ../../architecture.rst:26
+msgid "Register Architecture"
+msgstr ""
+
+#: ../../architecture.rst:28
+msgid "In strict alignment with the **Microchip AVR® Instruction Set Manual (DS40002198A, Section 4)**, the CPU register file consists of 32 8-bit general-purpose working registers, labeled **R0** through **R31**. All 32 registers have direct, single-cycle access to the Arithmetic Logic Unit (ALU)."
+msgstr ""
+
+#: ../../architecture.rst:45
+msgid "Register Organization & Special Functions"
+msgstr ""
+
+#: ../../architecture.rst:47
+msgid "**General Working Registers (R0–R15)**: Operate with all two-register arithmetic, logical, and bit operations (e.g., ``ADD``, ``SUB``, ``AND``, ``OR``, ``EOR``, ``MOV``, ``CP``)."
+msgstr ""
+
+#: ../../architecture.rst:49
+msgid "**Upper Registers (R16–R31)**: Support direct immediate instructions (``LDI``, ``SUBI``, ``SBCI``, ``ANDI``, ``ORI``, ``CPI``) where an 8-bit constant :math:`K` is supplied in the instruction."
+msgstr ""
+
+#: ../../architecture.rst:51
+msgid "**16-bit Word Operand Pairs (R25:R24, X, Y, Z)**: The word operations ``ADIW`` (Add Immediate to Word) and ``SBIW`` (Subtract Immediate from Word) operate exclusively on the upper register pairs: * ``R25:R24`` * ``R27:R26`` (X-register) * ``R29:R28`` (Y-register) * ``R31:R30`` (Z-register)"
+msgstr ""
+
+#: ../../architecture.rst:57
+msgid "**16-bit Pointer Registers (X, Y, Z)**: Six registers (R26–R31) serve as three 16-bit indirect address pointers for Data Space memory addressing: * **X-register**: ``XL = R26`` (low byte), ``XH = R27`` (high byte) * **Y-register**: ``YL = R28`` (low byte), ``YH = R29`` (high byte) * **Z-register**: ``ZL = R30`` (low byte), ``ZH = R31`` (high byte)"
+msgstr ""
+
+#: ../../architecture.rst:64
+msgid "Special Registers"
+msgstr ""
+
+#: ../../architecture.rst:67
+msgid "Program Counter (PC)"
+msgstr ""
+
+#: ../../architecture.rst:69
+msgid "16-bit program address pointer referencing instructions in program memory."
+msgstr ""
+
+#: ../../architecture.rst:70
+msgid "Automatically increments during sequential execution."
+msgstr ""
+
+#: ../../architecture.rst:71
+msgid "Modified by jump (``JMP``, ``RJMP``), subroutine call/return (``CALL``, ``RCALL``, ``RET``, ``RETI``), skip instructions (``CPSE``, ``SBRS``, ``SBRC``, ``SBIS``, ``SBIC``), and conditional branches (``BRxx``)."
+msgstr ""
+
+#: ../../architecture.rst:74
+msgid "Stack Pointer (SP)"
+msgstr ""
+
+#: ../../architecture.rst:76
+msgid "16-bit stack pointer pointing to the current top of the stack in Data SRAM."
+msgstr ""
+
+#: ../../architecture.rst:77
+msgid "Initialized to the end of RAM (default: ``0xFFFF`` with 64KB RAM)."
+msgstr ""
+
+#: ../../architecture.rst:78
+msgid "Decrements during ``PUSH``, ``CALL``, and ``RCALL`` (post-decrement)."
+msgstr ""
+
+#: ../../architecture.rst:79
+msgid "Increments during ``POP``, ``RET``, and ``RETI`` (pre-increment)."
+msgstr ""
+
+#: ../../architecture.rst:82
+msgid "Status Register (SREG)"
+msgstr ""
+
+#: ../../architecture.rst:84
+msgid "8-bit condition flag register containing flags: ``I``, ``T``, ``H``, ``S``, ``V``, ``N``, ``Z``, ``C``."
+msgstr ""
+
+#: ../../architecture.rst:85
+msgid "Updated by arithmetic, logical, and shift operations according to exact Boolean algebra defined in DS40002198A."
+msgstr ""
+
+#: ../../architecture.rst:93
+msgid "Memory Model & Addressing Modes"
+msgstr ""
+
+#: ../../architecture.rst:96
+msgid "Data Memory Space"
+msgstr ""
+
+#: ../../architecture.rst:98
+msgid "Tiny8 provides a flat, byte-addressable memory space modeled after AVR SRAM with configurable capacity (default: 65536 bytes / 64KB, addressable range ``0x0000`` to ``0xFFFF``)."
+msgstr ""
+
+#: ../../architecture.rst:117
+msgid "AVR Addressing Modes"
+msgstr ""
+
+#: ../../architecture.rst:119
+msgid "Tiny8 strictly adheres to the standard AVR addressing modes specified in DS40002198A:"
+msgstr ""
+
+#: ../../architecture.rst:121
+msgid "**Direct Single Register**: Operates on a single working register :math:`Rd` (e.g. ``INC Rd``, ``DEC Rd``, ``NEG Rd``, ``COM Rd``, ``CLR Rd``, ``SER Rd``, ``SWAP Rd``, ``LSL Rd``, ``LSR Rd``)."
+msgstr ""
+
+#: ../../architecture.rst:122
+msgid "**Direct Two-Register**: Operates on two working registers :math:`Rd` and :math:`Rr` (e.g. ``ADD Rd, Rr``, ``ADC Rd, Rr``, ``SUB Rd, Rr``, ``SBC Rd, Rr``, ``AND Rd, Rr``, ``OR Rd, Rr``, ``EOR Rd, Rr``, ``CP Rd, Rr``, ``MOV Rd, Rr``)."
+msgstr ""
+
+#: ../../architecture.rst:123
+msgid "**Immediate Addressing**: An 8-bit constant :math:`K` operates on an upper register :math:`R16 \\le Rd \\le R31` (e.g. ``LDI Rd, K``, ``SUBI Rd, K``, ``SBCI Rd, K``, ``ANDI Rd, K``, ``ORI Rd, K``, ``CPI Rd, K``)."
+msgstr ""
+
+#: ../../architecture.rst:124
+msgid "**Word Immediate Addressing**: A 6-bit constant :math:`0 \\le K \\le 63` operates on register pairs :math:`R25:R24`, :math:`X`, :math:`Y`, or :math:`Z` (e.g. ``ADIW Rd, K``, ``SBIW Rd, K``)."
+msgstr ""
+
+#: ../../architecture.rst:125
+msgid "**Direct Data Addressing**: 16-bit absolute memory address :math:`k` loads or stores directly to Data Space (e.g. ``LDS Rd, k``, ``STS k, Rr``)."
+msgstr ""
+
+#: ../../architecture.rst:126
+msgid "**Data Indirect Addressing with Pointer Registers (X, Y, Z)**: Accesses Data Space through 16-bit register pointers :math:`X` (R27:R26), :math:`Y` (R29:R28), or :math:`Z` (R31:R30) (e.g. ``LD Rd, X``, ``ST X, Rr``)."
+msgstr ""
+
+#: ../../architecture.rst:127
+msgid "**I/O Direct Addressing**: Reads or writes to 6-bit I/O addresses :math:`0 \\le P \\le 63` (e.g. ``IN Rd, P``, ``OUT P, Rr``, ``SBI P, b``, ``CBI P, b``, ``SBIS P, b``, ``SBIC P, b``)."
+msgstr ""
+
+#: ../../architecture.rst:128
+msgid "**Relative Program Addressing**: Jumps or branches relative to the current Program Counter within range :math:`PC + k + 1` (e.g. ``RJMP k``, ``RCALL k``, ``BREQ k``, ``BRNE k``, ``BRCS k``, ``BRCC k``, ``BRLO k``, ``BRSH k``, ``BRGE k``, ``BRLT k``, ``BRMI k``, ``BRPL k``)."
+msgstr ""
+
+#: ../../architecture.rst:129
+msgid "**Direct Program Addressing**: Unconditional jump or long subroutine call directly to 16-bit program address :math:`k` (e.g. ``JMP k``, ``CALL k``)."
+msgstr ""
+
+#: ../../architecture.rst:130
+msgid "**Indirect Program Addressing**: Return from subroutine or interrupt through return address popped from the stack (e.g. ``RET``, ``RETI``)."
+msgstr ""
+
+#: ../../architecture.rst:133
+msgid "Memory Access Examples"
+msgstr ""
+
+#: ../../architecture.rst:155
+msgid "All memory is initialized to 0 on CPU creation"
+msgstr ""
+
+#: ../../architecture.rst:156
+msgid "The assembler loads program instructions starting at address 0"
+msgstr ""
+
+#: ../../architecture.rst:157
+msgid "Stack pointer is initialized to the top of memory"
+msgstr ""
+
+#: ../../architecture.rst:160
+msgid "Status Flags"
+msgstr ""
+
+#: ../../architecture.rst:162
+msgid "The Status Register (SREG) contains 8 condition flags that reflect the result of operations and control program flow. In accordance with the **Microchip AVR® Instruction Set Manual (DS40002198A)**, each flag is defined and updated according to exact Boolean algebraic formulas."
+msgstr ""
+
+#: ../../architecture.rst:165
+msgid "Flag Descriptions & Boolean Formulas"
+msgstr ""
+
+#: ../../architecture.rst:171
+msgid "Bit"
+msgstr ""
+
+#: ../../architecture.rst:172
+msgid "Flag"
+msgstr ""
+
+#: ../../architecture.rst:173
+msgid "Name"
+msgstr ""
+
+#: ../../architecture.rst:174
+msgid "DS40002198A Definition & Formula"
+msgstr ""
+
+#: ../../architecture.rst:175
+msgid "7"
+msgstr ""
+
+#: ../../architecture.rst:176
+msgid "**I**"
+msgstr ""
+
+#: ../../architecture.rst:177
+msgid "Global Interrupt"
+msgstr ""
+
+#: ../../architecture.rst:178
+msgid "Set by ``SEI``, cleared by ``CLI`` or hardware interrupt entry."
+msgstr ""
+
+#: ../../architecture.rst:179
+msgid "6"
+msgstr ""
+
+#: ../../architecture.rst:180
+msgid "**T**"
+msgstr ""
+
+#: ../../architecture.rst:181
+msgid "Bit Copy Storage"
+msgstr ""
+
+#: ../../architecture.rst:182
+msgid "Transferred between SREG and register bit locations by ``BST`` / ``BLD``."
+msgstr ""
+
+#: ../../architecture.rst:183
+msgid "5"
+msgstr ""
+
+#: ../../architecture.rst:184
+msgid "**H**"
+msgstr ""
+
+#: ../../architecture.rst:185
+msgid "Half Carry"
+msgstr ""
+
+#: ../../architecture.rst:186
+msgid "Indicates carry/borrow across nibble boundary (bit 3 to bit 4). ADD: :math:`Rd3 \\cdot Rr3 + Rr3 \\cdot \\overline{R3} + \\overline{R3} \\cdot Rd3`. SUB: :math:`\\overline{Rd3} \\cdot Rr3 + Rr3 \\cdot R3 + R3 \\cdot \\overline{Rd3}`."
+msgstr ""
+
+#: ../../architecture.rst:187
+msgid "4"
+msgstr ""
+
+#: ../../architecture.rst:188
+msgid "**S**"
+msgstr ""
+
+#: ../../architecture.rst:189
+msgid "Sign Bit"
+msgstr ""
+
+#: ../../architecture.rst:190
+msgid "True algebraic sign test considering two's complement overflow: :math:`S = N \\oplus V`."
+msgstr ""
+
+#: ../../architecture.rst:191
+msgid "3"
+msgstr ""
+
+#: ../../architecture.rst:192
+msgid "**V**"
+msgstr ""
+
+#: ../../architecture.rst:193
+msgid "Overflow"
+msgstr ""
+
+#: ../../architecture.rst:194
+msgid "Two's complement signed overflow flag. ADD: :math:`Rd7 \\cdot Rr7 \\cdot \\overline{R7} + \\overline{Rd7} \\cdot \\overline{Rr7} \\cdot R7`. SUB: :math:`Rd7 \\cdot \\overline{Rr7} \\cdot \\overline{R7} + \\overline{Rd7} \\cdot Rr7 \\cdot R7`."
+msgstr ""
+
+#: ../../architecture.rst:195
+msgid "2"
+msgstr ""
+
+#: ../../architecture.rst:196
+msgid "**N**"
+msgstr ""
+
+#: ../../architecture.rst:197
+msgid "Negative"
+msgstr ""
+
+#: ../../architecture.rst:198
+msgid "Set if the most significant bit (MSB, bit 7) of the result is 1: :math:`N = R7`."
+msgstr ""
+
+#: ../../architecture.rst:199
+msgid "1"
+msgstr ""
+
+#: ../../architecture.rst:200
+msgid "**Z**"
+msgstr ""
+
+#: ../../architecture.rst:201
+msgid "Zero"
+msgstr ""
+
+#: ../../architecture.rst:202
+msgid "Set if the result equals zero: :math:`Z = \\overline{R7} \\cdot \\overline{R6} \\cdot \\overline{R5} \\cdot \\overline{R4} \\cdot \\overline{R3} \\cdot \\overline{R2} \\cdot \\overline{R1} \\cdot \\overline{R0}`."
+msgstr ""
+
+#: ../../architecture.rst:203
+msgid "0"
+msgstr ""
+
+#: ../../architecture.rst:204
+msgid "**C**"
+msgstr ""
+
+#: ../../architecture.rst:205
+msgid "Carry / Borrow"
+msgstr ""
+
+#: ../../architecture.rst:206
+msgid "Unsigned carry out of bit 7 or borrow. ADD: :math:`Rd7 \\cdot Rr7 + Rr7 \\cdot \\overline{R7} + \\overline{R7} \\cdot Rd7`. SUB: :math:`\\overline{Rd7} \\cdot Rr7 + Rr7 \\cdot R7 + R7 \\cdot \\overline{Rd7}`."
+msgstr ""
+
+#: ../../architecture.rst:209
+msgid "Flag Updates by Instruction Category"
+msgstr ""
+
+#: ../../architecture.rst:211
+msgid "According to AVR Instruction Set Manual DS40002198A:"
+msgstr ""
+
+#: ../../architecture.rst:213
+msgid "**Arithmetic (ADD, ADC, SUB, SUBI, SBC, SBCI)**"
+msgstr ""
+
+#: ../../architecture.rst:214
+msgid "Updates all condition flags: ``H``, ``S``, ``V``, ``N``, ``Z``, ``C``."
+msgstr ""
+
+#: ../../architecture.rst:216
+msgid "**Comparisons (CP, CPI)**"
+msgstr ""
+
+#: ../../architecture.rst:217
+msgid "Identical flag updates to subtraction (``SUB`` / ``SUBI``), but the register value is discarded."
+msgstr ""
+
+#: ../../architecture.rst:219
+msgid "**Bitwise Logical (AND, ANDI, OR, ORI, EOR, TST)**"
+msgstr ""
+
+#: ../../architecture.rst:220
+msgid "Updates ``S``, ``V=0`` (cleared), ``N``, ``Z``. Carry ``C`` and Half-Carry ``H`` are **unaffected** (``-``). ``TST Rd`` is an alias for ``AND Rd, Rd``."
+msgstr ""
+
+#: ../../architecture.rst:222
+msgid "**Register Clearing & Setting (CLR, SER)**"
+msgstr ""
+
+#: ../../architecture.rst:223
+msgid "``CLR Rd`` is an alias for ``EOR Rd, Rd``: sets ``Z=1``, ``S=0``, ``V=0``, ``N=0``; leaves ``C`` and ``H`` unaffected."
+msgstr ""
+
+#: ../../architecture.rst:224
+msgid "``SER Rd`` is an alias for ``LDI Rd, $FF``: **no flags affected**."
+msgstr ""
+
+#: ../../architecture.rst:226
+msgid "**Single-Operand Arithmetic (INC, DEC, NEG, COM)**"
+msgstr ""
+
+#: ../../architecture.rst:227
+msgid "``INC`` / ``DEC``: Update ``S``, ``V``, ``N``, ``Z``. Carry ``C`` is **unaffected** (allows loop counters without clobbering carry)."
+msgstr ""
+
+#: ../../architecture.rst:228
+msgid "``NEG``: Two's complement negation (:math:`R = 0 - Rd`). Updates ``H``, ``S``, ``V``, ``N``, ``Z``, ``C``. (:math:`C = (R \\neq 0)`, :math:`V = (Rd = \\$80)`)."
+msgstr ""
+
+#: ../../architecture.rst:229
+msgid "``COM``: One's complement inversion (:math:`R = \\$FF - Rd`). Updates ``S``, ``V=0``, ``N``, ``Z``, and forces ``C=1``."
+msgstr ""
+
+#: ../../architecture.rst:231
+msgid "**Shifts & Rotates (LSL, LSR, ROL, ROR, SWAP)**"
+msgstr ""
+
+#: ../../architecture.rst:232
+msgid "``LSL Rd``: Alias for ``ADD Rd, Rd``."
+msgstr ""
+
+#: ../../architecture.rst:233
+msgid "``ROL Rd``: Alias for ``ADC Rd, Rd``."
+msgstr ""
+
+#: ../../architecture.rst:234
+msgid "``LSR Rd``: Logical shift right. Sets :math:`C = Rd0`, :math:`N = 0`, :math:`Z = (R = 0)`, :math:`V = N \\oplus C = C`, :math:`S = N \\oplus V = C`."
+msgstr ""
+
+#: ../../architecture.rst:235
+msgid "``ROR Rd``: Rotate right through carry. Sets :math:`C = Rd0`, :math:`N = R7`, :math:`Z = (R = 0)`, :math:`V = N \\oplus C`, :math:`S = N \\oplus V`."
+msgstr ""
+
+#: ../../architecture.rst:236
+msgid "``SWAP Rd``: Swaps nibbles. **No flags affected**."
+msgstr ""
+
+#: ../../architecture.rst:238
+msgid "**Word Operations (ADIW, SBIW)**"
+msgstr ""
+
+#: ../../architecture.rst:239
+msgid "16-bit word addition / subtraction on pointer register pairs (R25:R24, R27:R26, R29:R28, R31:R30). Updates ``S``, ``V``, ``N``, ``Z``, ``C``."
+msgstr ""
+
+#: ../../architecture.rst:241
+msgid "**Data Transfer & Branches (LDI, MOV, LD, ST, LDS, STS, PUSH, POP, IN, OUT, JMP, RJMP, CALL, RCALL, RET, BRxx)**"
+msgstr ""
+
+#: ../../architecture.rst:242
+msgid "Do not affect status flags, except ``RETI`` which sets the Global Interrupt Flag ``I = 1``."
+msgstr ""
+
+#: ../../architecture.rst:245
+msgid "Using Flags for Branches"
+msgstr ""
+
+#: ../../architecture.rst:247
+msgid "Conditional branch instructions inspect specific SREG condition flags (all branches take target label or relative offset without altering flags):"
+msgstr ""
+
+#: ../../architecture.rst:253
+msgid "Mnemonic"
+msgstr ""
+
+#: ../../architecture.rst:254
+msgid "Condition"
+msgstr ""
+
+#: ../../architecture.rst:255
+msgid "Description (per DS40002198A)"
+msgstr ""
+
+#: ../../architecture.rst:256
+msgid "``BREQ label``"
+msgstr ""
+
+#: ../../architecture.rst:257
+msgid ":math:`Z = 1`"
+msgstr ""
+
+#: ../../architecture.rst:258
+msgid "Branch if Equal"
+msgstr ""
+
+#: ../../architecture.rst:259
+msgid "``BRNE label``"
+msgstr ""
+
+#: ../../architecture.rst:260
+msgid ":math:`Z = 0`"
+msgstr ""
+
+#: ../../architecture.rst:261
+msgid "Branch if Not Equal"
+msgstr ""
+
+#: ../../architecture.rst:262
+msgid "``BRCS label``"
+msgstr ""
+
+#: ../../architecture.rst:263
+#: ../../architecture.rst:269
+msgid ":math:`C = 1`"
+msgstr ""
+
+#: ../../architecture.rst:264
+msgid "Branch if Carry Set"
+msgstr ""
+
+#: ../../architecture.rst:265
+msgid "``BRCC label``"
+msgstr ""
+
+#: ../../architecture.rst:266
+#: ../../architecture.rst:272
+msgid ":math:`C = 0`"
+msgstr ""
+
+#: ../../architecture.rst:267
+msgid "Branch if Carry Clear"
+msgstr ""
+
+#: ../../architecture.rst:268
+msgid "``BRLO label``"
+msgstr ""
+
+#: ../../architecture.rst:270
+msgid "Branch if Lower (Unsigned, alias for ``BRCS``)"
+msgstr ""
+
+#: ../../architecture.rst:271
+msgid "``BRSH label``"
+msgstr ""
+
+#: ../../architecture.rst:273
+msgid "Branch if Same or Higher (Unsigned, alias for ``BRCC``)"
+msgstr ""
+
+#: ../../architecture.rst:274
+msgid "``BRGE label``"
+msgstr ""
+
+#: ../../architecture.rst:275
+msgid ":math:`S = 0` (:math:`N \\oplus V = 0`)"
+msgstr ""
+
+#: ../../architecture.rst:276
+msgid "Branch if Greater or Equal (Signed)"
+msgstr ""
+
+#: ../../architecture.rst:277
+msgid "``BRLT label``"
+msgstr ""
+
+#: ../../architecture.rst:278
+msgid ":math:`S = 1` (:math:`N \\oplus V = 1`)"
+msgstr ""
+
+#: ../../architecture.rst:279
+msgid "Branch if Less Than (Signed)"
+msgstr ""
+
+#: ../../architecture.rst:280
+msgid "``BRMI label``"
+msgstr ""
+
+#: ../../architecture.rst:281
+msgid ":math:`N = 1`"
+msgstr ""
+
+#: ../../architecture.rst:282
+msgid "Branch if Minus"
+msgstr ""
+
+#: ../../architecture.rst:283
+msgid "``BRPL label``"
+msgstr ""
+
+#: ../../architecture.rst:284
+msgid ":math:`N = 0`"
+msgstr ""
+
+#: ../../architecture.rst:285
+msgid "Branch if Plus"
+msgstr ""
+
+#: ../../architecture.rst:288
+msgid "Instruction Execution & ALU"
+msgstr ""
+
+#: ../../architecture.rst:291
+msgid "ALU Operation & Register Access"
+msgstr ""
+
+#: ../../architecture.rst:293
+msgid "In strict compliance with the **AVR® Instruction Set Manual (DS40002198A, Section 4)**, the high-performance AVR Arithmetic Logic Unit (ALU) operates in direct connection with all 32 general-purpose registers:"
+msgstr ""
+
+#: ../../architecture.rst:295
+msgid "**Single-Cycle Operation**: Arithmetic and logical register-to-register operations execute within a single instruction transition. In this cycle: 1. Two operand registers are read from the Register File. 2. The operation (Arithmetic, Logical, or Bit manipulation) is evaluated. 3. The result is written back to the destination register :math:`Rd`. 4. The Status Register (SREG) condition flags are updated according to exact Boolean algebraic formulas."
+msgstr ""
+
+#: ../../architecture.rst:300
+msgid "**ALU Functional Blocks**: * **Arithmetic**: Addition (``ADD``, ``ADC``, ``ADIW``), Subtraction (``SUB``, ``SUBI``, ``SBC``, ``SBCI``, ``SBIW``), Comparison (``CP``, ``CPI``), Negation (``NEG``), Increment (``INC``), Decrement (``DEC``), and Multiplication (``MUL``, ``MULS``, ``MULSU``). * **Logical**: Bitwise AND (``AND``, ``ANDI``, ``TST``), OR (``OR``, ``ORI``), Exclusive-OR (``EOR``, ``CLR``), and One's Complement (``COM``). * **Bit & Shift Functions**: Bit set/clear (``SBI``, ``CBI``), Shifts (``LSL``, ``LSR``, ``ASR``), Rotates through carry (``ROL``, ``ROR``), and Nibble swap (``SWAP``)."
+msgstr ""
+
+#: ../../architecture.rst:306
+msgid "Fetch-Decode-Execute Cycle"
+msgstr ""
+
+#: ../../architecture.rst:308
+msgid "Tiny8 executes programs through the classical CPU cycle:"
+msgstr ""
+
+#: ../../architecture.rst:321
+msgid "Instruction Format & Encoding"
+msgstr ""
+
+#: ../../architecture.rst:323
+msgid "In physical AVR microcontrollers: * Most instructions are **16-bit (1-word)** opcodes. * Direct memory instructions (``LDS``, ``STS``) and long jumps/calls (``JMP``, ``CALL``) are **32-bit (2-word)** opcodes."
+msgstr ""
+
+#: ../../architecture.rst:327
+msgid "In Tiny8, the assembler validates operands according to AVR DS40002198A constraints (e.g., verifying that ``LDI``, ``SUBI``, ``CPI`` only target upper registers R16–R31, and that ``ADIW`` / ``SBIW`` target valid pointer register pairs), then stores them as pre-decoded execution tuples:"
+msgstr ""
+
+#: ../../architecture.rst:340
+msgid "Step Tracing & State Inspection"
+msgstr ""
+
+#: ../../architecture.rst:342
+msgid "During each execution step, Tiny8 records changes to facilitate visual debugging:"
+msgstr ""
+
+#: ../../architecture.rst:344
+msgid "**Register Trace**: Tracks register writes as ``(step, register_index, new_value)``."
+msgstr ""
+
+#: ../../architecture.rst:345
+msgid "**Memory Trace**: Tracks SRAM writes as ``(step, address, new_value)``."
+msgstr ""
+
+#: ../../architecture.rst:346
+msgid "**Step Telemetry**: Records PC, SREG flags, cycle counts, and call stack backtraces."
+msgstr ""
+
+#: ../../architecture.rst:349
+msgid "Hardware Realism & AVR Compliance"
+msgstr ""
+
+#: ../../architecture.rst:351
+msgid "Tiny8 is strictly grounded in the **Microchip AVR® Instruction Set Manual (DS40002198A)**:"
+msgstr ""
+
+#: ../../architecture.rst:353
+msgid "**Instruction Set Fidelity**: All 61 supported instructions strictly follow official Microchip AVR definitions, operands, and SREG Boolean formulas without non-standard instruction extensions."
+msgstr ""
+
+#: ../../architecture.rst:354
+msgid "**Hardware MUL Compliance**: In accordance with AVR DS40002198A, ``MUL Rd, Rr`` writes the 16-bit unsigned product strictly into the dedicated register pair ``R1:R0`` (R0 = low byte, R1 = high byte)."
+msgstr ""
+
+#: ../../architecture.rst:355
+msgid "**Software Division**: Conforming to physical AVR silicon, integer division is performed via standard software routines (e.g., subtraction loops or shift-and-subtract) rather than non-standard hardware instructions."
+msgstr ""
+
+#: ../../architecture.rst:356
+msgid "**Execution & Memory Model**: Instructions execute in discrete single-step transitions across a unified flat address space with memory-mapped I/O (ports 0x00..0x3F including CRT matrix and keyboard buffer) for full visibility and educational inspectability."
+msgstr ""
+
+#: ../../architecture.rst:359
+msgid "Design Philosophy"
+msgstr ""
+
+#: ../../architecture.rst:361
+msgid "Tiny8's architecture is designed with these principles:"
+msgstr ""
+
+#: ../../architecture.rst:363
+msgid "**Simplicity**: Easy to understand and implement"
+msgstr ""
+
+#: ../../architecture.rst:364
+msgid "**Educational value**: Teaches fundamental concepts"
+msgstr ""
+
+#: ../../architecture.rst:365
+msgid "**Inspectability**: Full visibility into CPU state"
+msgstr ""
+
+#: ../../architecture.rst:366
+msgid "**Extensibility**: Easy to add new instructions"
+msgstr ""
+
+#: ../../architecture.rst:367
+msgid "**Practicality**: Can run real algorithms and demonstrate CS concepts"
+msgstr ""
+
+#: ../../architecture.rst:369
+msgid "The architecture strikes a balance between realism (standard AVR architecture) and pedagogy (simplified execution model), making it suitable for:"
+msgstr ""
+
+#: ../../architecture.rst:371
+msgid "Computer architecture courses"
+msgstr ""
+
+#: ../../architecture.rst:372
+msgid "Assembly language learning"
+msgstr ""
+
+#: ../../architecture.rst:373
+msgid "Algorithm visualization"
+msgstr ""
+
+#: ../../architecture.rst:374
+msgid "Embedded systems concepts"
+msgstr ""
+
+#: ../../architecture.rst:375
+msgid "Compiler/assembler development"
+msgstr ""
diff --git a/docs/locales/pot/assembly_language.pot b/docs/locales/pot/assembly_language.pot
new file mode 100644
index 0000000..115763a
--- /dev/null
+++ b/docs/locales/pot/assembly_language.pot
@@ -0,0 +1,1445 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-25 01:27+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../assembly_language.rst:2
+msgid "Assembly Language"
+msgstr ""
+
+#: ../../assembly_language.rst:4
+msgid "This guide covers the Tiny8 assembly language syntax, including instruction format, operand types, labels, and assembler directives."
+msgstr ""
+
+#: ../../assembly_language.rst:7
+msgid "Syntax Overview"
+msgstr ""
+
+#: ../../assembly_language.rst:10
+msgid "Basic Structure"
+msgstr ""
+
+#: ../../assembly_language.rst:12
+msgid "A Tiny8 assembly program consists of:"
+msgstr ""
+
+#: ../../assembly_language.rst:14
+msgid "**Instructions**: CPU operations (e.g., ``add``, ``mov``, ``ldi``)"
+msgstr ""
+
+#: ../../assembly_language.rst:15
+msgid "**Labels**: Named locations in the program"
+msgstr ""
+
+#: ../../assembly_language.rst:16
+msgid "**Comments**: Documentation prefixed with ``;``"
+msgstr ""
+
+#: ../../assembly_language.rst:17
+msgid "**Blank lines**: For readability (ignored by assembler)"
+msgstr ""
+
+#: ../../assembly_language.rst:20
+msgid "Example Program"
+msgstr ""
+
+#: ../../assembly_language.rst:42
+msgid "Comments"
+msgstr ""
+
+#: ../../assembly_language.rst:45
+msgid "Single-Line Comments"
+msgstr ""
+
+#: ../../assembly_language.rst:47
+msgid "Comments start with a semicolon (``;``) and extend to the end of the line:"
+msgstr ""
+
+#: ../../assembly_language.rst:55
+msgid "Comments are stripped during assembly and don't affect the generated program."
+msgstr ""
+
+#: ../../assembly_language.rst:58
+msgid "Whitespace"
+msgstr ""
+
+#: ../../assembly_language.rst:60
+msgid "Leading and trailing whitespace is ignored"
+msgstr ""
+
+#: ../../assembly_language.rst:61
+msgid "Multiple spaces between tokens are treated as single space"
+msgstr ""
+
+#: ../../assembly_language.rst:62
+msgid "Blank lines are allowed and ignored"
+msgstr ""
+
+#: ../../assembly_language.rst:65
+msgid "Labels"
+msgstr ""
+
+#: ../../assembly_language.rst:68
+msgid "Defining Labels"
+msgstr ""
+
+#: ../../assembly_language.rst:70
+msgid "Labels mark locations in your program and can be used as jump/branch targets:"
+msgstr ""
+
+#: ../../assembly_language.rst:81
+msgid "Label Rules"
+msgstr ""
+
+#: ../../assembly_language.rst:83
+msgid "Labels must end with a colon (``:``)"
+msgstr ""
+
+#: ../../assembly_language.rst:84
+msgid "Label names are case-sensitive"
+msgstr ""
+
+#: ../../assembly_language.rst:85
+msgid "Valid characters: letters, digits, underscore"
+msgstr ""
+
+#: ../../assembly_language.rst:86
+msgid "Cannot start with a digit"
+msgstr ""
+
+#: ../../assembly_language.rst:87
+msgid "Cannot be a reserved instruction mnemonic"
+msgstr ""
+
+#: ../../assembly_language.rst:89
+msgid "**Valid labels:**"
+msgstr ""
+
+#: ../../assembly_language.rst:98
+msgid "**Invalid labels:**"
+msgstr ""
+
+#: ../../assembly_language.rst:107
+msgid "Using Labels"
+msgstr ""
+
+#: ../../assembly_language.rst:109
+msgid "Labels are most commonly used with control flow instructions:"
+msgstr ""
+
+#: ../../assembly_language.rst:129
+msgid "Operand Types"
+msgstr ""
+
+#: ../../assembly_language.rst:132
+msgid "Registers"
+msgstr ""
+
+#: ../../assembly_language.rst:134
+msgid "Register operands are specified as ``r`` followed by the register number (0-31):"
+msgstr ""
+
+#: ../../assembly_language.rst:143
+msgid "Some instructions (like ``ldi``) only work with registers R16-R31."
+msgstr ""
+
+#: ../../assembly_language.rst:146
+msgid "Immediate Values"
+msgstr ""
+
+#: ../../assembly_language.rst:148
+msgid "Immediate values are constants embedded in the instruction:"
+msgstr ""
+
+#: ../../assembly_language.rst:150
+msgid "**Decimal** (default)"
+msgstr ""
+
+#: ../../assembly_language.rst:158
+msgid "**Hexadecimal** (prefix with ``0x`` or ``$``)"
+msgstr ""
+
+#: ../../assembly_language.rst:166
+msgid "**Binary** (prefix with ``0b``)"
+msgstr ""
+
+#: ../../assembly_language.rst:174
+msgid "**With Immediate Marker** (optional ``#`` prefix)"
+msgstr ""
+
+#: ../../assembly_language.rst:182
+msgid "Memory Addresses"
+msgstr ""
+
+#: ../../assembly_language.rst:184
+msgid "Memory addresses are used with load and store instructions:"
+msgstr ""
+
+#: ../../assembly_language.rst:193
+msgid "Label References"
+msgstr ""
+
+#: ../../assembly_language.rst:195
+msgid "Labels can be used as operands for jumps, branches, and calls:"
+msgstr ""
+
+#: ../../assembly_language.rst:214
+msgid "Instruction Format"
+msgstr ""
+
+#: ../../assembly_language.rst:217
+msgid "General Pattern"
+msgstr ""
+
+#: ../../assembly_language.rst:219
+msgid "Instructions follow this pattern:"
+msgstr ""
+
+#: ../../assembly_language.rst:225
+msgid "**label**: Optional label ending with ``:``"
+msgstr ""
+
+#: ../../assembly_language.rst:226
+msgid "**mnemonic**: Instruction name (e.g., ``add``, ``mov``, ``ldi``)"
+msgstr ""
+
+#: ../../assembly_language.rst:227
+msgid "**operands**: Zero or more operands separated by commas"
+msgstr ""
+
+#: ../../assembly_language.rst:230
+msgid "Operand Count"
+msgstr ""
+
+#: ../../assembly_language.rst:232
+msgid "Different instructions take different numbers of operands:"
+msgstr ""
+
+#: ../../assembly_language.rst:253
+msgid "Case Sensitivity"
+msgstr ""
+
+#: ../../assembly_language.rst:255
+msgid "**Instructions**: Case-insensitive (``ADD``, ``add``, ``Add`` are all valid)"
+msgstr ""
+
+#: ../../assembly_language.rst:256
+msgid "**Registers**: Case-insensitive (``r16``, ``R16`` are both valid)"
+msgstr ""
+
+#: ../../assembly_language.rst:257
+msgid "**Labels**: Case-sensitive (``Loop`` and ``loop`` are different)"
+msgstr ""
+
+#: ../../assembly_language.rst:272
+msgid "Program Structure"
+msgstr ""
+
+#: ../../assembly_language.rst:275
+msgid "Typical Program Layout"
+msgstr ""
+
+#: ../../assembly_language.rst:277
+msgid "Most Tiny8 programs follow this structure:"
+msgstr ""
+
+#: ../../assembly_language.rst:310
+msgid "Initialization"
+msgstr ""
+
+#: ../../assembly_language.rst:312
+msgid "Initialize registers and memory at the start of your program:"
+msgstr ""
+
+#: ../../assembly_language.rst:326
+msgid "Main Loop"
+msgstr ""
+
+#: ../../assembly_language.rst:328
+msgid "Most programs have a main execution loop:"
+msgstr ""
+
+#: ../../assembly_language.rst:346
+msgid "Program Termination"
+msgstr ""
+
+#: ../../assembly_language.rst:348
+msgid "Since Tiny8 doesn't have a \"halt\" instruction, programs typically end with an infinite loop:"
+msgstr ""
+
+#: ../../assembly_language.rst:361
+msgid "Assembler Behavior"
+msgstr ""
+
+#: ../../assembly_language.rst:364
+msgid "Two-Pass Assembly"
+msgstr ""
+
+#: ../../assembly_language.rst:366
+msgid "The assembler makes two passes through your code:"
+msgstr ""
+
+#: ../../assembly_language.rst:368
+msgid "**First pass**: Collect all labels and their addresses"
+msgstr ""
+
+#: ../../assembly_language.rst:369
+msgid "**Second pass**: Resolve label references and generate instructions"
+msgstr ""
+
+#: ../../assembly_language.rst:371
+msgid "This allows forward references:"
+msgstr ""
+
+#: ../../assembly_language.rst:383
+msgid "Number Parsing"
+msgstr ""
+
+#: ../../assembly_language.rst:385
+msgid "The assembler recognizes several number formats:"
+msgstr ""
+
+#: ../../assembly_language.rst:391
+msgid "Format"
+msgstr ""
+
+#: ../../assembly_language.rst:392
+msgid "Example"
+msgstr ""
+
+#: ../../assembly_language.rst:393
+msgid "Value"
+msgstr ""
+
+#: ../../assembly_language.rst:394
+msgid "Decimal"
+msgstr ""
+
+#: ../../assembly_language.rst:395
+msgid "``42``"
+msgstr ""
+
+#: ../../assembly_language.rst:396
+msgid "42"
+msgstr ""
+
+#: ../../assembly_language.rst:397
+msgid "Negative decimal"
+msgstr ""
+
+#: ../../assembly_language.rst:398
+msgid "``-10``"
+msgstr ""
+
+#: ../../assembly_language.rst:399
+msgid "-10 (stored as 246 in 8-bit)"
+msgstr ""
+
+#: ../../assembly_language.rst:400
+msgid "Hexadecimal (0x)"
+msgstr ""
+
+#: ../../assembly_language.rst:401
+msgid "``0xFF``"
+msgstr ""
+
+#: ../../assembly_language.rst:402
+#: ../../assembly_language.rst:405
+#: ../../assembly_language.rst:408
+msgid "255"
+msgstr ""
+
+#: ../../assembly_language.rst:403
+msgid "Hexadecimal ($)"
+msgstr ""
+
+#: ../../assembly_language.rst:404
+msgid "``$FF``"
+msgstr ""
+
+#: ../../assembly_language.rst:406
+msgid "Binary"
+msgstr ""
+
+#: ../../assembly_language.rst:407
+msgid "``0b11111111``"
+msgstr ""
+
+#: ../../assembly_language.rst:411
+msgid "Error Handling"
+msgstr ""
+
+#: ../../assembly_language.rst:413
+msgid "The assembler will report errors for:"
+msgstr ""
+
+#: ../../assembly_language.rst:415
+msgid "Invalid instruction mnemonics"
+msgstr ""
+
+#: ../../assembly_language.rst:416
+msgid "Wrong number of operands"
+msgstr ""
+
+#: ../../assembly_language.rst:417
+msgid "Invalid register numbers (< 0 or > 31)"
+msgstr ""
+
+#: ../../assembly_language.rst:418
+msgid "Undefined label references"
+msgstr ""
+
+#: ../../assembly_language.rst:419
+msgid "Invalid number formats"
+msgstr ""
+
+#: ../../assembly_language.rst:422
+msgid "Best Practices"
+msgstr ""
+
+#: ../../assembly_language.rst:425
+msgid "Code Organization"
+msgstr ""
+
+#: ../../assembly_language.rst:427
+msgid "**Use meaningful labels**: ``calculate_sum`` not ``label1``"
+msgstr ""
+
+#: ../../assembly_language.rst:428
+msgid "**Comment liberally**: Explain what and why, not just how"
+msgstr ""
+
+#: ../../assembly_language.rst:429
+msgid "**Group related code**: Keep subroutines together"
+msgstr ""
+
+#: ../../assembly_language.rst:430
+msgid "**Use blank lines**: Separate logical sections"
+msgstr ""
+
+#: ../../assembly_language.rst:448
+msgid "Naming Conventions"
+msgstr ""
+
+#: ../../assembly_language.rst:450
+msgid "**Labels**: Use ``snake_case`` or ``CamelCase`` consistently"
+msgstr ""
+
+#: ../../assembly_language.rst:451
+msgid "**Constants**: Use ``UPPER_CASE`` for important constants"
+msgstr ""
+
+#: ../../assembly_language.rst:452
+msgid "**Temporary values**: Use lower registers (R0-R15)"
+msgstr ""
+
+#: ../../assembly_language.rst:453
+msgid "**Important data**: Use upper registers (R16-R31)"
+msgstr ""
+
+#: ../../assembly_language.rst:456
+msgid "Register Allocation"
+msgstr ""
+
+#: ../../assembly_language.rst:458
+msgid "Plan your register usage:"
+msgstr ""
+
+#: ../../assembly_language.rst:469
+msgid "Value Ranges"
+msgstr ""
+
+#: ../../assembly_language.rst:471
+msgid "Remember that Tiny8 uses 8-bit values:"
+msgstr ""
+
+#: ../../assembly_language.rst:473
+msgid "Unsigned range: 0 to 255"
+msgstr ""
+
+#: ../../assembly_language.rst:474
+msgid "Signed range: -128 to +127"
+msgstr ""
+
+#: ../../assembly_language.rst:475
+msgid "Overflow wraps around"
+msgstr ""
+
+#: ../../assembly_language.rst:486
+msgid "Common Patterns"
+msgstr ""
+
+#: ../../assembly_language.rst:488
+msgid "See the :doc:`getting_started` guide for common assembly patterns like loops, conditionals, and memory operations."
+msgstr ""
+
+#: ../../assembly_language.rst:491
+msgid "Instruction Set Reference"
+msgstr ""
+
+#: ../../assembly_language.rst:493
+msgid "The Tiny8 instruction set strictly follows the **Microchip AVR® Instruction Set Manual (DS40002198A)**. All mnemonics and register identifiers are case-insensitive. Immediates can be specified in decimal, hexadecimal (``$FF`` or ``0xFF``), or binary (``0b11111111``)."
+msgstr ""
+
+#: ../../assembly_language.rst:496
+msgid "Arithmetic and Logic Instructions"
+msgstr ""
+
+#: ../../assembly_language.rst:502
+#: ../../assembly_language.rst:606
+#: ../../assembly_language.rst:694
+#: ../../assembly_language.rst:746
+#: ../../assembly_language.rst:806
+msgid "Mnemonic & Operands"
+msgstr ""
+
+#: ../../assembly_language.rst:503
+#: ../../assembly_language.rst:607
+#: ../../assembly_language.rst:695
+#: ../../assembly_language.rst:747
+#: ../../assembly_language.rst:807
+msgid "Description (DS40002198A)"
+msgstr ""
+
+#: ../../assembly_language.rst:504
+#: ../../assembly_language.rst:608
+#: ../../assembly_language.rst:696
+#: ../../assembly_language.rst:748
+#: ../../assembly_language.rst:808
+msgid "Operation"
+msgstr ""
+
+#: ../../assembly_language.rst:505
+#: ../../assembly_language.rst:609
+#: ../../assembly_language.rst:697
+#: ../../assembly_language.rst:749
+#: ../../assembly_language.rst:809
+msgid "Flags"
+msgstr ""
+
+#: ../../assembly_language.rst:506
+msgid "``ADD Rd, Rr``"
+msgstr ""
+
+#: ../../assembly_language.rst:507
+msgid "Add without Carry"
+msgstr ""
+
+#: ../../assembly_language.rst:508
+msgid ":math:`Rd \\leftarrow Rd + Rr`"
+msgstr ""
+
+#: ../../assembly_language.rst:509
+#: ../../assembly_language.rst:513
+#: ../../assembly_language.rst:521
+#: ../../assembly_language.rst:525
+#: ../../assembly_language.rst:529
+#: ../../assembly_language.rst:533
+#: ../../assembly_language.rst:565
+#: ../../assembly_language.rst:641
+#: ../../assembly_language.rst:645
+#: ../../assembly_language.rst:761
+#: ../../assembly_language.rst:773
+msgid "H, S, V, N, Z, C"
+msgstr ""
+
+#: ../../assembly_language.rst:510
+msgid "``ADC Rd, Rr``"
+msgstr ""
+
+#: ../../assembly_language.rst:511
+msgid "Add with Carry"
+msgstr ""
+
+#: ../../assembly_language.rst:512
+msgid ":math:`Rd \\leftarrow Rd + Rr + C`"
+msgstr ""
+
+#: ../../assembly_language.rst:514
+msgid "``ADIW Rd, K``"
+msgstr ""
+
+#: ../../assembly_language.rst:515
+msgid "Add Immediate to Word"
+msgstr ""
+
+#: ../../assembly_language.rst:516
+msgid ":math:`Rd+1:Rd \\leftarrow Rd+1:Rd + K`"
+msgstr ""
+
+#: ../../assembly_language.rst:517
+#: ../../assembly_language.rst:537
+#: ../../assembly_language.rst:765
+#: ../../assembly_language.rst:769
+#: ../../assembly_language.rst:777
+msgid "S, V, N, Z, C"
+msgstr ""
+
+#: ../../assembly_language.rst:518
+msgid "``SUB Rd, Rr``"
+msgstr ""
+
+#: ../../assembly_language.rst:519
+msgid "Subtract without Carry"
+msgstr ""
+
+#: ../../assembly_language.rst:520
+msgid ":math:`Rd \\leftarrow Rd - Rr`"
+msgstr ""
+
+#: ../../assembly_language.rst:522
+msgid "``SUBI Rd, K``"
+msgstr ""
+
+#: ../../assembly_language.rst:523
+msgid "Subtract Immediate"
+msgstr ""
+
+#: ../../assembly_language.rst:524
+msgid ":math:`Rd \\leftarrow Rd - K`"
+msgstr ""
+
+#: ../../assembly_language.rst:526
+msgid "``SBC Rd, Rr``"
+msgstr ""
+
+#: ../../assembly_language.rst:527
+msgid "Subtract with Carry"
+msgstr ""
+
+#: ../../assembly_language.rst:528
+msgid ":math:`Rd \\leftarrow Rd - Rr - C`"
+msgstr ""
+
+#: ../../assembly_language.rst:530
+msgid "``SBCI Rd, K``"
+msgstr ""
+
+#: ../../assembly_language.rst:531
+msgid "Subtract Immediate with Carry"
+msgstr ""
+
+#: ../../assembly_language.rst:532
+msgid ":math:`Rd \\leftarrow Rd - K - C`"
+msgstr ""
+
+#: ../../assembly_language.rst:534
+msgid "``SBIW Rd, K``"
+msgstr ""
+
+#: ../../assembly_language.rst:535
+msgid "Subtract Immediate from Word"
+msgstr ""
+
+#: ../../assembly_language.rst:536
+msgid ":math:`Rd+1:Rd \\leftarrow Rd+1:Rd - K`"
+msgstr ""
+
+#: ../../assembly_language.rst:538
+msgid "``AND Rd, Rr``"
+msgstr ""
+
+#: ../../assembly_language.rst:539
+msgid "Logical AND"
+msgstr ""
+
+#: ../../assembly_language.rst:540
+msgid ":math:`Rd \\leftarrow Rd \\cdot Rr`"
+msgstr ""
+
+#: ../../assembly_language.rst:541
+#: ../../assembly_language.rst:545
+#: ../../assembly_language.rst:549
+#: ../../assembly_language.rst:553
+#: ../../assembly_language.rst:557
+#: ../../assembly_language.rst:577
+msgid "S, V=0, N, Z"
+msgstr ""
+
+#: ../../assembly_language.rst:542
+msgid "``ANDI Rd, K``"
+msgstr ""
+
+#: ../../assembly_language.rst:543
+msgid "Logical AND with Immediate"
+msgstr ""
+
+#: ../../assembly_language.rst:544
+msgid ":math:`Rd \\leftarrow Rd \\cdot K`"
+msgstr ""
+
+#: ../../assembly_language.rst:546
+msgid "``OR Rd, Rr``"
+msgstr ""
+
+#: ../../assembly_language.rst:547
+msgid "Logical OR"
+msgstr ""
+
+#: ../../assembly_language.rst:548
+msgid ":math:`Rd \\leftarrow Rd \\lor Rr`"
+msgstr ""
+
+#: ../../assembly_language.rst:550
+msgid "``ORI Rd, K``"
+msgstr ""
+
+#: ../../assembly_language.rst:551
+msgid "Logical OR with Immediate"
+msgstr ""
+
+#: ../../assembly_language.rst:552
+msgid ":math:`Rd \\leftarrow Rd \\lor K`"
+msgstr ""
+
+#: ../../assembly_language.rst:554
+msgid "``EOR Rd, Rr``"
+msgstr ""
+
+#: ../../assembly_language.rst:555
+msgid "Exclusive OR"
+msgstr ""
+
+#: ../../assembly_language.rst:556
+msgid ":math:`Rd \\leftarrow Rd \\oplus Rr`"
+msgstr ""
+
+#: ../../assembly_language.rst:558
+msgid "``COM Rd``"
+msgstr ""
+
+#: ../../assembly_language.rst:559
+msgid "One's Complement"
+msgstr ""
+
+#: ../../assembly_language.rst:560
+msgid ":math:`Rd \\leftarrow \\$FF - Rd`"
+msgstr ""
+
+#: ../../assembly_language.rst:561
+msgid "S, V=0, N, Z, C=1"
+msgstr ""
+
+#: ../../assembly_language.rst:562
+msgid "``NEG Rd``"
+msgstr ""
+
+#: ../../assembly_language.rst:563
+msgid "Two's Complement Negation"
+msgstr ""
+
+#: ../../assembly_language.rst:564
+msgid ":math:`Rd \\leftarrow \\$00 - Rd`"
+msgstr ""
+
+#: ../../assembly_language.rst:566
+msgid "``INC Rd``"
+msgstr ""
+
+#: ../../assembly_language.rst:567
+msgid "Increment"
+msgstr ""
+
+#: ../../assembly_language.rst:568
+msgid ":math:`Rd \\leftarrow Rd + 1`"
+msgstr ""
+
+#: ../../assembly_language.rst:569
+#: ../../assembly_language.rst:573
+msgid "S, V, N, Z"
+msgstr ""
+
+#: ../../assembly_language.rst:570
+msgid "``DEC Rd``"
+msgstr ""
+
+#: ../../assembly_language.rst:571
+msgid "Decrement"
+msgstr ""
+
+#: ../../assembly_language.rst:572
+msgid ":math:`Rd \\leftarrow Rd - 1`"
+msgstr ""
+
+#: ../../assembly_language.rst:574
+msgid "``TST Rd``"
+msgstr ""
+
+#: ../../assembly_language.rst:575
+msgid "Test for Zero or Minus"
+msgstr ""
+
+#: ../../assembly_language.rst:576
+msgid ":math:`Rd \\leftarrow Rd \\cdot Rd` (alias for AND)"
+msgstr ""
+
+#: ../../assembly_language.rst:578
+msgid "``CLR Rd``"
+msgstr ""
+
+#: ../../assembly_language.rst:579
+msgid "Clear Register"
+msgstr ""
+
+#: ../../assembly_language.rst:580
+msgid ":math:`Rd \\leftarrow Rd \\oplus Rd` (alias for EOR)"
+msgstr ""
+
+#: ../../assembly_language.rst:581
+msgid "S=0, V=0, N=0, Z=1"
+msgstr ""
+
+#: ../../assembly_language.rst:582
+msgid "``SER Rd``"
+msgstr ""
+
+#: ../../assembly_language.rst:583
+msgid "Set Register"
+msgstr ""
+
+#: ../../assembly_language.rst:584
+msgid ":math:`Rd \\leftarrow \\$FF` (alias for LDI)"
+msgstr ""
+
+#: ../../assembly_language.rst:585
+#: ../../assembly_language.rst:613
+#: ../../assembly_language.rst:617
+#: ../../assembly_language.rst:621
+#: ../../assembly_language.rst:625
+#: ../../assembly_language.rst:629
+#: ../../assembly_language.rst:637
+#: ../../assembly_language.rst:649
+#: ../../assembly_language.rst:653
+#: ../../assembly_language.rst:657
+#: ../../assembly_language.rst:661
+#: ../../assembly_language.rst:665
+#: ../../assembly_language.rst:669
+#: ../../assembly_language.rst:673
+#: ../../assembly_language.rst:677
+#: ../../assembly_language.rst:681
+#: ../../assembly_language.rst:685
+#: ../../assembly_language.rst:701
+#: ../../assembly_language.rst:705
+#: ../../assembly_language.rst:709
+#: ../../assembly_language.rst:713
+#: ../../assembly_language.rst:717
+#: ../../assembly_language.rst:721
+#: ../../assembly_language.rst:725
+#: ../../assembly_language.rst:729
+#: ../../assembly_language.rst:733
+#: ../../assembly_language.rst:737
+#: ../../assembly_language.rst:753
+#: ../../assembly_language.rst:757
+#: ../../assembly_language.rst:781
+#: ../../assembly_language.rst:785
+#: ../../assembly_language.rst:789
+#: ../../assembly_language.rst:793
+#: ../../assembly_language.rst:797
+#: ../../assembly_language.rst:813
+msgid "None"
+msgstr ""
+
+#: ../../assembly_language.rst:586
+msgid "``MUL Rd, Rr``"
+msgstr ""
+
+#: ../../assembly_language.rst:587
+msgid "Multiply Unsigned"
+msgstr ""
+
+#: ../../assembly_language.rst:588
+msgid ":math:`R1:R0 \\leftarrow Rd \\times Rr`"
+msgstr ""
+
+#: ../../assembly_language.rst:589
+#: ../../assembly_language.rst:593
+#: ../../assembly_language.rst:597
+msgid "Z, C"
+msgstr ""
+
+#: ../../assembly_language.rst:590
+msgid "``MULS Rd, Rr``"
+msgstr ""
+
+#: ../../assembly_language.rst:591
+msgid "Multiply Signed"
+msgstr ""
+
+#: ../../assembly_language.rst:592
+msgid ":math:`R1:R0 \\leftarrow Rd \\times Rr` (signed)"
+msgstr ""
+
+#: ../../assembly_language.rst:594
+msgid "``MULSU Rd, Rr``"
+msgstr ""
+
+#: ../../assembly_language.rst:595
+msgid "Multiply Signed with Unsigned"
+msgstr ""
+
+#: ../../assembly_language.rst:596
+msgid ":math:`R1:R0 \\leftarrow Rd \\times Rr` (:math:`Rd` signed, :math:`Rr` unsigned)"
+msgstr ""
+
+#: ../../assembly_language.rst:600
+msgid "Branch Instructions"
+msgstr ""
+
+#: ../../assembly_language.rst:610
+msgid "``JMP target``"
+msgstr ""
+
+#: ../../assembly_language.rst:611
+msgid "Jump"
+msgstr ""
+
+#: ../../assembly_language.rst:612
+msgid ":math:`PC \\leftarrow target`"
+msgstr ""
+
+#: ../../assembly_language.rst:614
+msgid "``RJMP offset``"
+msgstr ""
+
+#: ../../assembly_language.rst:615
+msgid "Relative Jump"
+msgstr ""
+
+#: ../../assembly_language.rst:616
+msgid ":math:`PC \\leftarrow PC + offset + 1`"
+msgstr ""
+
+#: ../../assembly_language.rst:618
+msgid "``CALL target``"
+msgstr ""
+
+#: ../../assembly_language.rst:619
+msgid "Long Call to Subroutine"
+msgstr ""
+
+#: ../../assembly_language.rst:620
+msgid ":math:`STACK \\leftarrow PC + 1, PC \\leftarrow target`"
+msgstr ""
+
+#: ../../assembly_language.rst:622
+msgid "``RCALL offset``"
+msgstr ""
+
+#: ../../assembly_language.rst:623
+msgid "Relative Call to Subroutine"
+msgstr ""
+
+#: ../../assembly_language.rst:624
+msgid ":math:`STACK \\leftarrow PC + 1, PC \\leftarrow PC + offset + 1`"
+msgstr ""
+
+#: ../../assembly_language.rst:626
+msgid "``RET``"
+msgstr ""
+
+#: ../../assembly_language.rst:627
+msgid "Return from Subroutine"
+msgstr ""
+
+#: ../../assembly_language.rst:628
+msgid ":math:`PC \\leftarrow STACK`"
+msgstr ""
+
+#: ../../assembly_language.rst:630
+msgid "``RETI``"
+msgstr ""
+
+#: ../../assembly_language.rst:631
+msgid "Return from Interrupt"
+msgstr ""
+
+#: ../../assembly_language.rst:632
+msgid ":math:`PC \\leftarrow STACK, I \\leftarrow 1`"
+msgstr ""
+
+#: ../../assembly_language.rst:633
+#: ../../assembly_language.rst:817
+#: ../../assembly_language.rst:821
+msgid "I"
+msgstr ""
+
+#: ../../assembly_language.rst:634
+msgid "``CPSE Rd, Rr``"
+msgstr ""
+
+#: ../../assembly_language.rst:635
+msgid "Compare Skip if Equal"
+msgstr ""
+
+#: ../../assembly_language.rst:636
+msgid "If :math:`Rd = Rr` then skip next instruction"
+msgstr ""
+
+#: ../../assembly_language.rst:638
+msgid "``CP Rd, Rr``"
+msgstr ""
+
+#: ../../assembly_language.rst:639
+msgid "Compare"
+msgstr ""
+
+#: ../../assembly_language.rst:640
+msgid ":math:`Rd - Rr`"
+msgstr ""
+
+#: ../../assembly_language.rst:642
+msgid "``CPI Rd, K``"
+msgstr ""
+
+#: ../../assembly_language.rst:643
+msgid "Compare with Immediate"
+msgstr ""
+
+#: ../../assembly_language.rst:644
+msgid ":math:`Rd - K`"
+msgstr ""
+
+#: ../../assembly_language.rst:646
+msgid "``BREQ label``"
+msgstr ""
+
+#: ../../assembly_language.rst:647
+msgid "Branch if Equal"
+msgstr ""
+
+#: ../../assembly_language.rst:648
+msgid "If :math:`Z = 1` then :math:`PC \\leftarrow label`"
+msgstr ""
+
+#: ../../assembly_language.rst:650
+msgid "``BRNE label``"
+msgstr ""
+
+#: ../../assembly_language.rst:651
+msgid "Branch if Not Equal"
+msgstr ""
+
+#: ../../assembly_language.rst:652
+msgid "If :math:`Z = 0` then :math:`PC \\leftarrow label`"
+msgstr ""
+
+#: ../../assembly_language.rst:654
+msgid "``BRCS label``"
+msgstr ""
+
+#: ../../assembly_language.rst:655
+msgid "Branch if Carry Set"
+msgstr ""
+
+#: ../../assembly_language.rst:656
+msgid "If :math:`C = 1` then :math:`PC \\leftarrow label`"
+msgstr ""
+
+#: ../../assembly_language.rst:658
+msgid "``BRCC label``"
+msgstr ""
+
+#: ../../assembly_language.rst:659
+msgid "Branch if Carry Clear"
+msgstr ""
+
+#: ../../assembly_language.rst:660
+msgid "If :math:`C = 0` then :math:`PC \\leftarrow label`"
+msgstr ""
+
+#: ../../assembly_language.rst:662
+msgid "``BRLO label``"
+msgstr ""
+
+#: ../../assembly_language.rst:663
+msgid "Branch if Lower (Unsigned)"
+msgstr ""
+
+#: ../../assembly_language.rst:664
+msgid "If :math:`C = 1` then :math:`PC \\leftarrow label` (alias for BRCS)"
+msgstr ""
+
+#: ../../assembly_language.rst:666
+msgid "``BRSH label``"
+msgstr ""
+
+#: ../../assembly_language.rst:667
+msgid "Branch if Same or Higher"
+msgstr ""
+
+#: ../../assembly_language.rst:668
+msgid "If :math:`C = 0` then :math:`PC \\leftarrow label` (alias for BRCC)"
+msgstr ""
+
+#: ../../assembly_language.rst:670
+msgid "``BRGE label``"
+msgstr ""
+
+#: ../../assembly_language.rst:671
+msgid "Branch if Greater or Equal (Signed)"
+msgstr ""
+
+#: ../../assembly_language.rst:672
+msgid "If :math:`S = 0` (:math:`N \\oplus V = 0`) then :math:`PC \\leftarrow label`"
+msgstr ""
+
+#: ../../assembly_language.rst:674
+msgid "``BRLT label``"
+msgstr ""
+
+#: ../../assembly_language.rst:675
+msgid "Branch if Less Than (Signed)"
+msgstr ""
+
+#: ../../assembly_language.rst:676
+msgid "If :math:`S = 1` (:math:`N \\oplus V = 1`) then :math:`PC \\leftarrow label`"
+msgstr ""
+
+#: ../../assembly_language.rst:678
+msgid "``BRMI label``"
+msgstr ""
+
+#: ../../assembly_language.rst:679
+msgid "Branch if Minus"
+msgstr ""
+
+#: ../../assembly_language.rst:680
+msgid "If :math:`N = 1` then :math:`PC \\leftarrow label`"
+msgstr ""
+
+#: ../../assembly_language.rst:682
+msgid "``BRPL label``"
+msgstr ""
+
+#: ../../assembly_language.rst:683
+msgid "Branch if Plus"
+msgstr ""
+
+#: ../../assembly_language.rst:684
+msgid "If :math:`N = 0` then :math:`PC \\leftarrow label`"
+msgstr ""
+
+#: ../../assembly_language.rst:688
+msgid "Data Transfer Instructions"
+msgstr ""
+
+#: ../../assembly_language.rst:698
+msgid "``MOV Rd, Rr``"
+msgstr ""
+
+#: ../../assembly_language.rst:699
+msgid "Copy Register"
+msgstr ""
+
+#: ../../assembly_language.rst:700
+msgid ":math:`Rd \\leftarrow Rr`"
+msgstr ""
+
+#: ../../assembly_language.rst:702
+msgid "``LDI Rd, K``"
+msgstr ""
+
+#: ../../assembly_language.rst:703
+msgid "Load Immediate"
+msgstr ""
+
+#: ../../assembly_language.rst:704
+msgid ":math:`Rd \\leftarrow K` (:math:`16 \\le d \\le 31`)"
+msgstr ""
+
+#: ../../assembly_language.rst:706
+msgid "``LD Rd, addr_reg``"
+msgstr ""
+
+#: ../../assembly_language.rst:707
+msgid "Load Indirect from Data Space"
+msgstr ""
+
+#: ../../assembly_language.rst:708
+msgid ":math:`Rd \\leftarrow (addr\\_reg)`"
+msgstr ""
+
+#: ../../assembly_language.rst:710
+msgid "``ST addr_reg, Rr``"
+msgstr ""
+
+#: ../../assembly_language.rst:711
+msgid "Store Indirect to Data Space"
+msgstr ""
+
+#: ../../assembly_language.rst:712
+msgid ":math:`(addr\\_reg) \\leftarrow Rr`"
+msgstr ""
+
+#: ../../assembly_language.rst:714
+msgid "``LDS Rd, addr``"
+msgstr ""
+
+#: ../../assembly_language.rst:715
+msgid "Load Direct from Data Space"
+msgstr ""
+
+#: ../../assembly_language.rst:716
+msgid ":math:`Rd \\leftarrow (addr)`"
+msgstr ""
+
+#: ../../assembly_language.rst:718
+msgid "``STS addr, Rr``"
+msgstr ""
+
+#: ../../assembly_language.rst:719
+msgid "Store Direct to Data Space"
+msgstr ""
+
+#: ../../assembly_language.rst:720
+msgid ":math:`(addr) \\leftarrow Rr`"
+msgstr ""
+
+#: ../../assembly_language.rst:722
+msgid "``IN Rd, port``"
+msgstr ""
+
+#: ../../assembly_language.rst:723
+msgid "Load an I/O Location to Register"
+msgstr ""
+
+#: ../../assembly_language.rst:724
+msgid ":math:`Rd \\leftarrow P`"
+msgstr ""
+
+#: ../../assembly_language.rst:726
+msgid "``OUT port, Rr``"
+msgstr ""
+
+#: ../../assembly_language.rst:727
+msgid "Store Register to an I/O Location"
+msgstr ""
+
+#: ../../assembly_language.rst:728
+msgid ":math:`P \\leftarrow Rr`"
+msgstr ""
+
+#: ../../assembly_language.rst:730
+msgid "``PUSH Rr``"
+msgstr ""
+
+#: ../../assembly_language.rst:731
+msgid "Push Register on Stack"
+msgstr ""
+
+#: ../../assembly_language.rst:732
+msgid ":math:`STACK \\leftarrow Rr, SP \\leftarrow SP - 1`"
+msgstr ""
+
+#: ../../assembly_language.rst:734
+msgid "``POP Rd``"
+msgstr ""
+
+#: ../../assembly_language.rst:735
+msgid "Pop Register from Stack"
+msgstr ""
+
+#: ../../assembly_language.rst:736
+msgid ":math:`SP \\leftarrow SP + 1, Rd \\leftarrow STACK`"
+msgstr ""
+
+#: ../../assembly_language.rst:740
+msgid "Bit and Bit-Test Instructions"
+msgstr ""
+
+#: ../../assembly_language.rst:750
+msgid "``SBI port, bit``"
+msgstr ""
+
+#: ../../assembly_language.rst:751
+msgid "Set Bit in I/O Register"
+msgstr ""
+
+#: ../../assembly_language.rst:752
+msgid ":math:`I/O(P, bit) \\leftarrow 1`"
+msgstr ""
+
+#: ../../assembly_language.rst:754
+msgid "``CBI port, bit``"
+msgstr ""
+
+#: ../../assembly_language.rst:755
+msgid "Clear Bit in I/O Register"
+msgstr ""
+
+#: ../../assembly_language.rst:756
+msgid ":math:`I/O(P, bit) \\leftarrow 0`"
+msgstr ""
+
+#: ../../assembly_language.rst:758
+msgid "``LSL Rd``"
+msgstr ""
+
+#: ../../assembly_language.rst:759
+msgid "Logical Shift Left"
+msgstr ""
+
+#: ../../assembly_language.rst:760
+msgid ":math:`Rd \\leftarrow Rd \\ll 1` (alias for ADD Rd, Rd)"
+msgstr ""
+
+#: ../../assembly_language.rst:762
+msgid "``LSR Rd``"
+msgstr ""
+
+#: ../../assembly_language.rst:763
+msgid "Logical Shift Right"
+msgstr ""
+
+#: ../../assembly_language.rst:764
+msgid ":math:`0 \\rightarrow Rd7 \\dots Rd0 \\rightarrow C`"
+msgstr ""
+
+#: ../../assembly_language.rst:766
+msgid "``ASR Rd``"
+msgstr ""
+
+#: ../../assembly_language.rst:767
+msgid "Arithmetic Shift Right"
+msgstr ""
+
+#: ../../assembly_language.rst:768
+msgid ":math:`Rd7 \\rightarrow Rd7 \\dots Rd0 \\rightarrow C`"
+msgstr ""
+
+#: ../../assembly_language.rst:770
+msgid "``ROL Rd``"
+msgstr ""
+
+#: ../../assembly_language.rst:771
+msgid "Rotate Left through Carry"
+msgstr ""
+
+#: ../../assembly_language.rst:772
+msgid ":math:`C \\leftarrow Rd7 \\dots Rd0 \\leftarrow C` (alias for ADC Rd, Rd)"
+msgstr ""
+
+#: ../../assembly_language.rst:774
+msgid "``ROR Rd``"
+msgstr ""
+
+#: ../../assembly_language.rst:775
+msgid "Rotate Right through Carry"
+msgstr ""
+
+#: ../../assembly_language.rst:776
+msgid ":math:`C \\rightarrow Rd7 \\dots Rd0 \\rightarrow C`"
+msgstr ""
+
+#: ../../assembly_language.rst:778
+msgid "``SWAP Rd``"
+msgstr ""
+
+#: ../../assembly_language.rst:779
+msgid "Swap Nibbles"
+msgstr ""
+
+#: ../../assembly_language.rst:780
+msgid ":math:`Rd(7..4) \\leftrightarrow Rd(3..0)`"
+msgstr ""
+
+#: ../../assembly_language.rst:782
+msgid "``SBRS Rd, bit``"
+msgstr ""
+
+#: ../../assembly_language.rst:783
+msgid "Skip if Bit in Register is Set"
+msgstr ""
+
+#: ../../assembly_language.rst:784
+msgid "If :math:`Rd(bit) = 1` then skip next instruction"
+msgstr ""
+
+#: ../../assembly_language.rst:786
+msgid "``SBRC Rd, bit``"
+msgstr ""
+
+#: ../../assembly_language.rst:787
+msgid "Skip if Bit in Register is Cleared"
+msgstr ""
+
+#: ../../assembly_language.rst:788
+msgid "If :math:`Rd(bit) = 0` then skip next instruction"
+msgstr ""
+
+#: ../../assembly_language.rst:790
+msgid "``SBIS port, bit``"
+msgstr ""
+
+#: ../../assembly_language.rst:791
+msgid "Skip if Bit in I/O Register is Set"
+msgstr ""
+
+#: ../../assembly_language.rst:792
+msgid "If :math:`I/O(P, bit) = 1` then skip next instruction"
+msgstr ""
+
+#: ../../assembly_language.rst:794
+msgid "``SBIC port, bit``"
+msgstr ""
+
+#: ../../assembly_language.rst:795
+msgid "Skip if Bit in I/O Register is Cleared"
+msgstr ""
+
+#: ../../assembly_language.rst:796
+msgid "If :math:`I/O(P, bit) = 0` then skip next instruction"
+msgstr ""
+
+#: ../../assembly_language.rst:800
+msgid "MCU Control Instructions"
+msgstr ""
+
+#: ../../assembly_language.rst:810
+msgid "``NOP``"
+msgstr ""
+
+#: ../../assembly_language.rst:811
+msgid "No Operation"
+msgstr ""
+
+#: ../../assembly_language.rst:812
+msgid "No operation performed"
+msgstr ""
+
+#: ../../assembly_language.rst:814
+msgid "``SEI``"
+msgstr ""
+
+#: ../../assembly_language.rst:815
+msgid "Set Global Interrupt Flag"
+msgstr ""
+
+#: ../../assembly_language.rst:816
+msgid ":math:`I \\leftarrow 1`"
+msgstr ""
+
+#: ../../assembly_language.rst:818
+msgid "``CLI``"
+msgstr ""
+
+#: ../../assembly_language.rst:819
+msgid "Clear Global Interrupt Flag"
+msgstr ""
+
+#: ../../assembly_language.rst:820
+msgid ":math:`I \\leftarrow 0`"
+msgstr ""
diff --git a/docs/locales/pot/examples.pot b/docs/locales/pot/examples.pot
new file mode 100644
index 0000000..9037a54
--- /dev/null
+++ b/docs/locales/pot/examples.pot
@@ -0,0 +1,1335 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:17+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../examples/array_sum.rst:2
+#: ../../examples/index.rst:113
+msgid "Array Sum"
+msgstr ""
+
+#: ../../examples/array_sum.rst:4
+msgid "Sums elements of an array stored in memory."
+msgstr ""
+
+#: ../../examples/array_sum.rst:10
+msgid "Demonstrates memory access and array processing."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:2
+#: ../../examples/bubblesort.rst:351
+#: ../../examples/index.rst:125
+msgid "Bubble Sort"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:4
+msgid "This advanced example demonstrates bubble sort: a classic sorting algorithm that sorts an array in memory."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:7
+#: ../../examples/fibonacci.rst:7
+#: ../../examples/index.rst:7
+msgid "Overview"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:9
+msgid "**Difficulty**: Advanced"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:11
+msgid "**Concepts**: Nested loops, memory operations, array manipulation, pseudo-random number generation"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:13
+msgid "**Output**: Sorted array at RAM[0x60..0x7F] (32 bytes in ascending order)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:16
+#: ../../examples/fibonacci.rst:16
+msgid "The Program"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:23
+msgid "Algorithm Overview"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:25
+msgid "The program has two main phases:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:27
+msgid "**Initialization**: Generate 32 pseudo-random values and store them in RAM"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:28
+msgid "**Bubble Sort**: Sort the array using the bubble sort algorithm"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:31
+msgid "Phase 1: Array Initialization"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:34
+msgid "Pseudo-Random Number Generator"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:36
+msgid "The program uses a simple linear congruential generator (LCG):"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:42
+msgid "This generates a sequence of pseudo-random 8-bit values."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:56
+msgid "After 32 iterations, RAM[0x60..0x7F] contains pseudo-random values."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:59
+msgid "Phase 2: Bubble Sort"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:62
+#: ../../examples/fibonacci.rst:23
+msgid "Algorithm Explanation"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:64
+msgid "Bubble sort works by repeatedly stepping through the array, comparing adjacent elements, and swapping them if they're in the wrong order."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:74
+msgid "Outer Loop"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:87
+msgid "Runs 31 times (i = 0 to 30)."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:90
+msgid "Inner Loop"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:119
+msgid "For each j:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:121
+msgid "Load adjacent elements (j and j+1)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:122
+msgid "Compare them"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:123
+msgid "Swap if first > second (for ascending order)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:124
+msgid "Advance to next pair"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:127
+msgid "Register Usage"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:129
+msgid "Register Allocation"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:133
+msgid "Register"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:134
+msgid "Purpose"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:135
+msgid "R16"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:136
+msgid "Memory address pointer / base address"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:137
+msgid "R17"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:138
+msgid "Array index during initialization"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:139
+msgid "R18"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:140
+msgid "PRNG seed / outer loop counter (i)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:141
+msgid "R19"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:142
+msgid "Inner loop counter (j)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:143
+msgid "R20"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:144
+msgid "Address of element A"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:145
+msgid "R21"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:146
+msgid "Value of element A"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:147
+msgid "R22"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:148
+msgid "Address of element B"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:149
+msgid "R23"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:150
+msgid "Temporary comparison value"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:151
+msgid "R24"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:152
+msgid "Value of element B"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:153
+msgid "R25"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:154
+msgid "PRNG multiplier constant (75)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:157
+msgid "Memory Layout"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:174
+msgid "Execution Example"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:177
+msgid "Initial Array (pseudo-random)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:184
+msgid "After Bubble Sort"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:190
+msgid "Bubble sort compares and swaps adjacent elements until the entire array is sorted."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:193
+#: ../../examples/fibonacci.rst:139
+msgid "Running the Example"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:196
+#: ../../examples/fibonacci.rst:142
+msgid "Interactive Debugger"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:202
+msgid "Watch the sorting process step-by-step. Set marks at the beginning of inner_loop to track passes."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:205
+#: ../../examples/fibonacci.rst:151
+msgid "Animation"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:212
+msgid "Creates a visualization showing:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:214
+msgid "Memory heatmap of the array being sorted"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:215
+msgid "Register changes during comparisons"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:216
+msgid "Visual pattern of values moving to their correct positions"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:219
+#: ../../examples/fibonacci.rst:160
+msgid "Python API"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:239
+msgid "Performance Analysis"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:242
+#: ../../examples/bubblesort.rst:348
+msgid "Time Complexity"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:244
+msgid "**Best case**: O(n²) - 31 × 31 = 961 comparisons"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:245
+msgid "**Worst case**: O(n²) - Same as best (this implementation doesn't optimize)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:246
+msgid "**Average case**: O(n²)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:248
+msgid "For 32 elements:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:250
+msgid "Outer loop: 31 iterations"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:251
+msgid "Inner loop: 31 iterations per outer"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:252
+msgid "Total comparisons: ~961"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:253
+msgid "Total swaps: Variable (depends on initial order)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:256
+msgid "Instruction Count"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:258
+msgid "Each comparison involves approximately:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:260
+msgid "10 instructions to load addresses and values"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:261
+msgid "5 instructions for comparison and potential swap"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:262
+msgid "3 instructions for loop control"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:264
+msgid "Total: ~15,000+ instructions for a complete sort."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:267
+#: ../../examples/fibonacci.rst:173
+msgid "Key Concepts"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:270
+msgid "Nested Loops"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:272
+msgid "Two loop counters working together:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:286
+msgid "Address Calculation"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:288
+msgid "Computing memory addresses dynamically:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:297
+msgid "Conditional Swapping"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:308
+#: ../../examples/fibonacci.rst:202
+msgid "Exercises"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:310
+msgid "**Count swaps**: Add a counter to track number of swaps"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:311
+msgid "**Optimize**: Add early exit if no swaps occurred in a pass"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:312
+msgid "**Different sizes**: Sort 16 or 64 elements instead"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:313
+msgid "**Descending order**: Modify to sort in descending order"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:314
+msgid "**Different algorithm**: Implement selection sort or insertion sort"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:317
+msgid "Solutions Hints"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:319
+msgid "**Count swaps**: Add ``inc r26`` in the swap section, initialize R26 to 0."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:321
+msgid "**Optimize**: Set a flag when swapping, check it at end of outer loop."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:323
+msgid "**Descending order**: Change ``brcs no_swap`` to ``brcc no_swap``."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:326
+msgid "Visualization Tips"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:328
+msgid "When viewing the animation:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:330
+msgid "**Memory panel**: Watch values \"bubble\" to their positions"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:331
+msgid "**Register panel**: R19 (j) cycles 0-30 repeatedly"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:332
+msgid "**Register panel**: R18 (i) increments slowly"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:334
+msgid "Look for:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:336
+msgid "Large values moving right (higher addresses)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:337
+msgid "Small values moving left (lower addresses)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:338
+msgid "Progressively fewer changes as array becomes sorted"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:341
+msgid "Comparison with Other Sorts"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:343
+msgid "Sorting Algorithm Comparison"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:347
+msgid "Algorithm"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:349
+msgid "Space"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:350
+msgid "Stability"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:352
+#: ../../examples/bubblesort.rst:356
+#: ../../examples/bubblesort.rst:360
+msgid "O(n²)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:353
+#: ../../examples/bubblesort.rst:357
+#: ../../examples/bubblesort.rst:361
+msgid "O(1)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:354
+#: ../../examples/bubblesort.rst:362
+msgid "Yes"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:355
+msgid "Selection Sort"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:358
+#: ../../examples/bubblesort.rst:366
+msgid "No"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:359
+msgid "Insertion Sort"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:363
+msgid "Quick Sort"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:364
+msgid "O(n log n)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:365
+msgid "O(log n)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:368
+msgid "Bubble sort is chosen for this example because it's conceptually simple and demonstrates memory operations clearly."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:371
+#: ../../examples/fibonacci.rst:232
+msgid "Related Examples"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:373
+msgid ":doc:`linear_search` - Sequential array access"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:374
+msgid ":doc:`find_max` - Array comparison operations"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:375
+msgid ":doc:`reverse` - Array manipulation"
+msgstr ""
+
+#: ../../examples/count_bits.rst:2
+#: ../../examples/index.rst:137
+msgid "Count Bits"
+msgstr ""
+
+#: ../../examples/count_bits.rst:4
+msgid "Counts the number of set bits (1s) in a value."
+msgstr ""
+
+#: ../../examples/count_bits.rst:10
+msgid "Demonstrates bit manipulation and counting operations."
+msgstr ""
+
+#: ../../examples/factorial.rst:2
+msgid "Factorial"
+msgstr ""
+
+#: ../../examples/factorial.rst:4
+msgid "Computes factorial of a number using iterative multiplication."
+msgstr ""
+
+#: ../../examples/factorial.rst:10
+msgid "Calculates 5! = 120 using repeated multiplication and demonstrates loop control."
+msgstr ""
+
+#: ../../examples/fibonacci.rst:2
+msgid "Fibonacci Sequence"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:4
+msgid "This example calculates the 10th Fibonacci number using an iterative approach."
+msgstr ""
+
+#: ../../examples/fibonacci.rst:9
+msgid "**Difficulty**: Beginner"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:11
+msgid "**Concepts**: Loops, register arithmetic, conditional branching"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:13
+msgid "**Output**: R17 contains F(10) = 55"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:25
+msgid "The Fibonacci sequence is defined as:"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:27
+msgid "F(0) = 0"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:28
+msgid "F(1) = 1"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:29
+msgid "F(n) = F(n-1) + F(n-2) for n > 1"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:31
+msgid "This program uses an iterative approach with three registers:"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:33
+msgid "**R16**: Previous Fibonacci number (F(n-1))"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:34
+msgid "**R17**: Current Fibonacci number (F(n))"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:35
+msgid "**R18**: Counter (remaining iterations)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:38
+msgid "Step-by-Step Walkthrough"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:41
+msgid "Initialization (Lines 8-10)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:49
+msgid "We start with F(0) = 0 and F(1) = 1. Since we want F(10), we need 9 more iterations (F(2) through F(10))."
+msgstr ""
+
+#: ../../examples/fibonacci.rst:52
+msgid "Main Loop (Lines 12-18)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:64
+msgid "Each iteration:"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:66
+msgid "**Add**: Compute next Fibonacci number (R16 + R17)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:67
+msgid "**Save**: Store result in temporary register R19"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:68
+msgid "**Shift**: Move R17 to R16 (previous ← current)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:69
+msgid "**Update**: Move R19 to R17 (current ← new result)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:70
+msgid "**Decrement**: Decrease counter"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:71
+msgid "**Branch**: Loop if counter ≠ 0"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:74
+msgid "Execution Trace"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:76
+msgid "Here's how the registers evolve:"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:78
+msgid "Fibonacci Calculation"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:82
+msgid "Iter"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:83
+msgid "R16 (prev)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:84
+msgid "R17 (curr)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:85
+msgid "R18 (count)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:86
+msgid "Calculation"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:87
+msgid "Init"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:88
+#: ../../examples/fibonacci.rst:135
+msgid "0"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:89
+#: ../../examples/fibonacci.rst:92
+#: ../../examples/fibonacci.rst:93
+#: ../../examples/fibonacci.rst:94
+#: ../../examples/fibonacci.rst:98
+#: ../../examples/fibonacci.rst:130
+msgid "1"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:90
+#: ../../examples/fibonacci.rst:132
+msgid "9"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:91
+msgid "F(0), F(1)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:95
+#: ../../examples/fibonacci.rst:114
+#: ../../examples/fibonacci.rst:118
+#: ../../examples/fibonacci.rst:127
+msgid "8"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:96
+msgid "F(2) = 0 + 1 = 1"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:97
+#: ../../examples/fibonacci.rst:99
+#: ../../examples/fibonacci.rst:103
+#: ../../examples/fibonacci.rst:125
+msgid "2"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:100
+#: ../../examples/fibonacci.rst:122
+msgid "7"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:101
+msgid "F(3) = 1 + 1 = 2"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:102
+#: ../../examples/fibonacci.rst:104
+#: ../../examples/fibonacci.rst:108
+#: ../../examples/fibonacci.rst:120
+msgid "3"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:105
+#: ../../examples/fibonacci.rst:117
+msgid "6"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:106
+msgid "F(4) = 1 + 2 = 3"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:107
+#: ../../examples/fibonacci.rst:115
+msgid "4"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:109
+#: ../../examples/fibonacci.rst:110
+#: ../../examples/fibonacci.rst:112
+#: ../../examples/fibonacci.rst:113
+msgid "5"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:111
+msgid "F(5) = 2 + 3 = 5"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:116
+msgid "F(6) = 3 + 5 = 8"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:119
+#: ../../examples/fibonacci.rst:123
+msgid "13"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:121
+msgid "F(7) = 5 + 8 = 13"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:124
+#: ../../examples/fibonacci.rst:128
+msgid "21"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:126
+msgid "F(8) = 8 + 13 = 21"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:129
+#: ../../examples/fibonacci.rst:133
+msgid "34"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:131
+msgid "F(9) = 13 + 21 = 34"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:134
+msgid "55"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:136
+msgid "F(10) = 21 + 34 = 55"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:148
+msgid "Step through with ``j`` and watch registers R16, R17, and R18 evolve."
+msgstr ""
+
+#: ../../examples/fibonacci.rst:157
+msgid "Visualize the register changes over time."
+msgstr ""
+
+#: ../../examples/fibonacci.rst:176
+msgid "Loop Structure"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:178
+msgid "The loop pattern is common in assembly:"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:189
+msgid "Register Shifting"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:191
+msgid "Moving values between registers for state management:"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:199
+msgid "This \"register rotation\" is a fundamental technique in assembly programming."
+msgstr ""
+
+#: ../../examples/fibonacci.rst:204
+msgid "**Modify the counter**: Calculate F(15) instead of F(10)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:205
+msgid "**Different starting values**: Try F(0) = 1, F(1) = 1 (alternative definition)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:206
+msgid "**Store in memory**: Save each Fibonacci number to memory"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:207
+msgid "**Detect overflow**: Check when the result exceeds 255"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:210
+msgid "Solutions"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:212
+msgid "**F(15) modification**:"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:218
+msgid "Note: F(15) = 610, which exceeds 8-bit range (wraps to 98)."
+msgstr ""
+
+#: ../../examples/fibonacci.rst:220
+msgid "**Store in memory**:"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:234
+msgid ":doc:`factorial` - Another iterative calculation"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:235
+msgid ":doc:`sum_1_to_n` - Similar loop structure"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:236
+msgid ":doc:`power` - Repeated operation pattern"
+msgstr ""
+
+#: ../../examples/find_max.rst:2
+msgid "Find Maximum"
+msgstr ""
+
+#: ../../examples/find_max.rst:4
+msgid "Finds the maximum value in an array."
+msgstr ""
+
+#: ../../examples/find_max.rst:10
+msgid "Demonstrates comparison operations and conditional logic."
+msgstr ""
+
+#: ../../examples/gcd.rst:2
+msgid "GCD (Greatest Common Divisor)"
+msgstr ""
+
+#: ../../examples/gcd.rst:4
+msgid "Computes the GCD of two numbers using Euclidean algorithm."
+msgstr ""
+
+#: ../../examples/gcd.rst:10
+msgid "Demonstrates subtraction-based Euclidean algorithm and conditional comparison."
+msgstr ""
+
+#: ../../examples/hello_world.rst:2
+#: ../../examples/index.rst:98
+msgid "Hello World"
+msgstr ""
+
+#: ../../examples/hello_world.rst:4
+msgid "A minimal Tiny8 program demonstrating basic structure."
+msgstr ""
+
+#: ../../examples/hello_world.rst:10
+msgid "This program demonstrates the simplest possible Tiny8 program structure with initialization and an infinite loop."
+msgstr ""
+
+#: ../../examples/index.rst:2
+msgid "Examples"
+msgstr ""
+
+#: ../../examples/index.rst:4
+msgid "This section contains detailed walkthroughs of example programs that demonstrate Tiny8's capabilities and teach assembly programming concepts."
+msgstr ""
+
+#: ../../examples/index.rst:9
+msgid "The examples are organized by complexity and concept:"
+msgstr ""
+
+#: ../../examples/index.rst:11
+msgid "**Basic Examples**"
+msgstr ""
+
+#: ../../examples/index.rst:12
+msgid "Simple programs demonstrating fundamental operations"
+msgstr ""
+
+#: ../../examples/index.rst:14
+msgid "**Intermediate Examples**"
+msgstr ""
+
+#: ../../examples/index.rst:15
+msgid "Programs using loops, conditionals, and memory operations"
+msgstr ""
+
+#: ../../examples/index.rst:17
+msgid "**Advanced Examples**"
+msgstr ""
+
+#: ../../examples/index.rst:18
+msgid "Complex algorithms including sorting and mathematical computations"
+msgstr ""
+
+#: ../../examples/index.rst:20
+msgid "All examples are available in the ``examples/`` directory of the Tiny8 repository."
+msgstr ""
+
+#: ../../examples/index.rst:23
+msgid "Running Examples"
+msgstr ""
+
+#: ../../examples/index.rst:25
+msgid "You can run any example with the interactive debugger:"
+msgstr ""
+
+#: ../../examples/index.rst:31
+msgid "Or use the Python API:"
+msgstr ""
+
+#: ../../examples/index.rst:42
+msgid "Example Programs"
+msgstr ""
+
+#: ../../examples/index.rst:45
+msgid "Basic Examples"
+msgstr ""
+
+#: ../../examples/index.rst:55
+msgid "Intermediate Examples"
+msgstr ""
+
+#: ../../examples/index.rst:67
+msgid "Advanced Examples"
+msgstr ""
+
+#: ../../examples/index.rst:81
+msgid "C Language Programs & Interactive Demos"
+msgstr ""
+
+#: ../../examples/index.rst:83
+msgid "Tiny8 includes an embedded C subset compiler capable of compiling and running C programs directly on the simulated CPU:"
+msgstr ""
+
+#: ../../examples/index.rst:85
+msgid "**factorial.c**: Recursive factorial calculation demonstration."
+msgstr ""
+
+#: ../../examples/index.rst:86
+msgid "**mnist_heatmap.c**: 28x28 MNIST real digit heatmap transfer to 32x32 VRAM."
+msgstr ""
+
+#: ../../examples/index.rst:89
+msgid "Quick Reference"
+msgstr ""
+
+#: ../../examples/index.rst:91
+msgid "Example Summary"
+msgstr ""
+
+#: ../../examples/index.rst:95
+msgid "Program"
+msgstr ""
+
+#: ../../examples/index.rst:96
+msgid "Concept"
+msgstr ""
+
+#: ../../examples/index.rst:97
+msgid "Key Instructions / Language"
+msgstr ""
+
+#: ../../examples/index.rst:99
+msgid "Basic memory writing"
+msgstr ""
+
+#: ../../examples/index.rst:100
+msgid "LDI, ST, INC, JMP"
+msgstr ""
+
+#: ../../examples/index.rst:101
+msgid "Fibonacci"
+msgstr ""
+
+#: ../../examples/index.rst:102
+msgid "Iterative sequence"
+msgstr ""
+
+#: ../../examples/index.rst:103
+msgid "ADD, MOV, DEC, BRNE"
+msgstr ""
+
+#: ../../examples/index.rst:104
+msgid "Factorial (ASM)"
+msgstr ""
+
+#: ../../examples/index.rst:105
+msgid "Iterative multiplication"
+msgstr ""
+
+#: ../../examples/index.rst:106
+msgid "MUL, DEC, CPI, BRGE"
+msgstr ""
+
+#: ../../examples/index.rst:107
+msgid "Factorial (C)"
+msgstr ""
+
+#: ../../examples/index.rst:108
+msgid "Recursive function calls"
+msgstr ""
+
+#: ../../examples/index.rst:109
+msgid "C Compiler (CALL, RET, PUSH, POP)"
+msgstr ""
+
+#: ../../examples/index.rst:110
+#: ../../examples/sum_1_to_n.rst:2
+msgid "Sum 1 to N"
+msgstr ""
+
+#: ../../examples/index.rst:111
+msgid "Loop accumulation"
+msgstr ""
+
+#: ../../examples/index.rst:112
+msgid "ADD, INC, CP, BRLT, BREQ"
+msgstr ""
+
+#: ../../examples/index.rst:114
+msgid "Pointer iteration"
+msgstr ""
+
+#: ../../examples/index.rst:115
+msgid "LD, ST, ADD, INC, BRNE"
+msgstr ""
+
+#: ../../examples/index.rst:116
+msgid "Find Max"
+msgstr ""
+
+#: ../../examples/index.rst:117
+msgid "Array scanning & comparison"
+msgstr ""
+
+#: ../../examples/index.rst:118
+msgid "LD, ST, CP, BRGE, MOV"
+msgstr ""
+
+#: ../../examples/index.rst:119
+#: ../../examples/linear_search.rst:2
+msgid "Linear Search"
+msgstr ""
+
+#: ../../examples/index.rst:120
+msgid "Target search & sentinel"
+msgstr ""
+
+#: ../../examples/index.rst:121
+msgid "LD, ST, CP, BREQ, INC"
+msgstr ""
+
+#: ../../examples/index.rst:122
+#: ../../examples/memory_copy.rst:2
+msgid "Memory Copy"
+msgstr ""
+
+#: ../../examples/index.rst:123
+msgid "Block memory transfer"
+msgstr ""
+
+#: ../../examples/index.rst:124
+msgid "LD, ST, INC, DEC, BRNE"
+msgstr ""
+
+#: ../../examples/index.rst:126
+msgid "PRNG & in-place sort"
+msgstr ""
+
+#: ../../examples/index.rst:127
+msgid "MUL, LD, ST, CP, BRCS"
+msgstr ""
+
+#: ../../examples/index.rst:128
+msgid "GCD"
+msgstr ""
+
+#: ../../examples/index.rst:129
+msgid "Euclidean algorithm"
+msgstr ""
+
+#: ../../examples/index.rst:130
+msgid "DIV, MOV, CPI, BREQ"
+msgstr ""
+
+#: ../../examples/index.rst:131
+msgid "Power"
+msgstr ""
+
+#: ../../examples/index.rst:132
+msgid "Exponentiation"
+msgstr ""
+
+#: ../../examples/index.rst:133
+msgid "MUL, INC, CP, BRLT"
+msgstr ""
+
+#: ../../examples/index.rst:134
+#: ../../examples/multiply_by_shift.rst:2
+msgid "Multiply by Shift"
+msgstr ""
+
+#: ../../examples/index.rst:135
+msgid "Binary shift multiplication"
+msgstr ""
+
+#: ../../examples/index.rst:136
+msgid "LSL, LSR, ANDI, ADD"
+msgstr ""
+
+#: ../../examples/index.rst:138
+msgid "Bit testing & division"
+msgstr ""
+
+#: ../../examples/index.rst:139
+msgid "AND, DIV, CPI, BRNE"
+msgstr ""
+
+#: ../../examples/index.rst:140
+#: ../../examples/is_prime.rst:2
+msgid "Is Prime"
+msgstr ""
+
+#: ../../examples/index.rst:141
+msgid "Trial division"
+msgstr ""
+
+#: ../../examples/index.rst:142
+msgid "DIV, MUL, CP, BRGE, BRLT"
+msgstr ""
+
+#: ../../examples/index.rst:143
+#: ../../examples/reverse.rst:2
+msgid "Reverse Array"
+msgstr ""
+
+#: ../../examples/index.rst:144
+msgid "Two-pointer array reverse"
+msgstr ""
+
+#: ../../examples/index.rst:145
+msgid "LD, ST, CP, BRGE, INC, DEC"
+msgstr ""
+
+#: ../../examples/index.rst:146
+msgid "MNIST Heatmap (C)"
+msgstr ""
+
+#: ../../examples/index.rst:147
+msgid "28x28 digit VRAM heatmap"
+msgstr ""
+
+#: ../../examples/index.rst:148
+msgid "C (VRAM 0x0200..0x05FF)"
+msgstr ""
+
+#: ../../examples/index.rst:149
+msgid "MNIST Diffusion (ASM)"
+msgstr ""
+
+#: ../../examples/index.rst:150
+msgid "Iterative reverse-diffusion synthesis"
+msgstr ""
+
+#: ../../examples/index.rst:151
+msgid "ASM (diffusion_mnist8.asm)"
+msgstr ""
+
+#: ../../examples/index.rst:154
+msgid "Learning Path"
+msgstr ""
+
+#: ../../examples/index.rst:156
+msgid "Recommended order for learning:"
+msgstr ""
+
+#: ../../examples/index.rst:158
+msgid "**Start with basics**: hello_world, fibonacci, factorial"
+msgstr ""
+
+#: ../../examples/index.rst:159
+msgid "**Learn memory**: array_sum, memory_copy, find_max"
+msgstr ""
+
+#: ../../examples/index.rst:160
+msgid "**Master control flow**: linear_search, gcd"
+msgstr ""
+
+#: ../../examples/index.rst:161
+msgid "**Tackle algorithms**: bubblesort, power, is_prime"
+msgstr ""
+
+#: ../../examples/index.rst:162
+msgid "**Explore bit operations**: multiply_by_shift, count_bits"
+msgstr ""
+
+#: ../../examples/is_prime.rst:4
+msgid "Tests whether a number is prime."
+msgstr ""
+
+#: ../../examples/is_prime.rst:10
+msgid "Demonstrates trial division and number theory concepts."
+msgstr ""
+
+#: ../../examples/linear_search.rst:4
+msgid "Searches for a value in an array."
+msgstr ""
+
+#: ../../examples/linear_search.rst:10
+msgid "Demonstrates sequential search and early loop exit."
+msgstr ""
+
+#: ../../examples/memory_copy.rst:4
+msgid "Copies data from one memory location to another."
+msgstr ""
+
+#: ../../examples/memory_copy.rst:10
+msgid "Demonstrates memory-to-memory data transfer."
+msgstr ""
+
+#: ../../examples/multiply_by_shift.rst:4
+msgid "Multiplies numbers using bit shifting instead of MUL instruction."
+msgstr ""
+
+#: ../../examples/multiply_by_shift.rst:10
+msgid "Demonstrates bit manipulation and efficient multiplication."
+msgstr ""
+
+#: ../../examples/power.rst:2
+msgid "Power Function"
+msgstr ""
+
+#: ../../examples/power.rst:4
+msgid "Computes x^n using repeated multiplication."
+msgstr ""
+
+#: ../../examples/power.rst:10
+msgid "Demonstrates exponentiation through iteration."
+msgstr ""
+
+#: ../../examples/reverse.rst:4
+msgid "Reverses an array in place."
+msgstr ""
+
+#: ../../examples/reverse.rst:10
+msgid "Demonstrates two-pointer technique and array manipulation."
+msgstr ""
+
+#: ../../examples/sum_1_to_n.rst:4
+msgid "Calculates the sum of integers from 1 to N."
+msgstr ""
+
+#: ../../examples/sum_1_to_n.rst:10
+msgid "Demonstrates accumulation pattern and loop control."
+msgstr ""
diff --git a/docs/locales/pot/examples/array_sum.pot b/docs/locales/pot/examples/array_sum.pot
new file mode 100644
index 0000000..36a510e
--- /dev/null
+++ b/docs/locales/pot/examples/array_sum.pot
@@ -0,0 +1,29 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:30+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../examples/array_sum.rst:2
+msgid "Array Sum"
+msgstr ""
+
+#: ../../examples/array_sum.rst:4
+msgid "Sums elements of an array stored in memory."
+msgstr ""
+
+#: ../../examples/array_sum.rst:10
+msgid "Demonstrates memory access and array processing."
+msgstr ""
diff --git a/docs/locales/pot/examples/bubblesort.pot b/docs/locales/pot/examples/bubblesort.pot
new file mode 100644
index 0000000..7ac50b1
--- /dev/null
+++ b/docs/locales/pot/examples/bubblesort.pot
@@ -0,0 +1,525 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:30+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../examples/bubblesort.rst:2
+#: ../../examples/bubblesort.rst:351
+msgid "Bubble Sort"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:4
+msgid "This advanced example demonstrates bubble sort: a classic sorting algorithm that sorts an array in memory."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:7
+msgid "Overview"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:9
+msgid "**Difficulty**: Advanced"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:11
+msgid "**Concepts**: Nested loops, memory operations, array manipulation, pseudo-random number generation"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:13
+msgid "**Output**: Sorted array at RAM[0x60..0x7F] (32 bytes in ascending order)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:16
+msgid "The Program"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:23
+msgid "Algorithm Overview"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:25
+msgid "The program has two main phases:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:27
+msgid "**Initialization**: Generate 32 pseudo-random values and store them in RAM"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:28
+msgid "**Bubble Sort**: Sort the array using the bubble sort algorithm"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:31
+msgid "Phase 1: Array Initialization"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:34
+msgid "Pseudo-Random Number Generator"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:36
+msgid "The program uses a simple linear congruential generator (LCG):"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:42
+msgid "This generates a sequence of pseudo-random 8-bit values."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:56
+msgid "After 32 iterations, RAM[0x60..0x7F] contains pseudo-random values."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:59
+msgid "Phase 2: Bubble Sort"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:62
+msgid "Algorithm Explanation"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:64
+msgid "Bubble sort works by repeatedly stepping through the array, comparing adjacent elements, and swapping them if they're in the wrong order."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:74
+msgid "Outer Loop"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:87
+msgid "Runs 31 times (i = 0 to 30)."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:90
+msgid "Inner Loop"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:119
+msgid "For each j:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:121
+msgid "Load adjacent elements (j and j+1)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:122
+msgid "Compare them"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:123
+msgid "Swap if first > second (for ascending order)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:124
+msgid "Advance to next pair"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:127
+msgid "Register Usage"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:129
+msgid "Register Allocation"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:133
+msgid "Register"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:134
+msgid "Purpose"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:135
+msgid "R16"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:136
+msgid "Memory address pointer / base address"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:137
+msgid "R17"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:138
+msgid "Array index during initialization"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:139
+msgid "R18"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:140
+msgid "PRNG seed / outer loop counter (i)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:141
+msgid "R19"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:142
+msgid "Inner loop counter (j)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:143
+msgid "R20"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:144
+msgid "Address of element A"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:145
+msgid "R21"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:146
+msgid "Value of element A"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:147
+msgid "R22"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:148
+msgid "Address of element B"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:149
+msgid "R23"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:150
+msgid "Temporary comparison value"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:151
+msgid "R24"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:152
+msgid "Value of element B"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:153
+msgid "R25"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:154
+msgid "PRNG multiplier constant (75)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:157
+msgid "Memory Layout"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:174
+msgid "Execution Example"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:177
+msgid "Initial Array (pseudo-random)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:184
+msgid "After Bubble Sort"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:190
+msgid "Bubble sort compares and swaps adjacent elements until the entire array is sorted."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:193
+msgid "Running the Example"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:196
+msgid "Interactive Debugger"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:202
+msgid "Watch the sorting process step-by-step. Set marks at the beginning of inner_loop to track passes."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:205
+msgid "Animation"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:212
+msgid "Creates a visualization showing:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:214
+msgid "Memory heatmap of the array being sorted"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:215
+msgid "Register changes during comparisons"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:216
+msgid "Visual pattern of values moving to their correct positions"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:219
+msgid "Python API"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:239
+msgid "Performance Analysis"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:242
+#: ../../examples/bubblesort.rst:348
+msgid "Time Complexity"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:244
+msgid "**Best case**: O(n²) - 31 × 31 = 961 comparisons"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:245
+msgid "**Worst case**: O(n²) - Same as best (this implementation doesn't optimize)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:246
+msgid "**Average case**: O(n²)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:248
+msgid "For 32 elements:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:250
+msgid "Outer loop: 31 iterations"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:251
+msgid "Inner loop: 31 iterations per outer"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:252
+msgid "Total comparisons: ~961"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:253
+msgid "Total swaps: Variable (depends on initial order)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:256
+msgid "Instruction Count"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:258
+msgid "Each comparison involves approximately:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:260
+msgid "10 instructions to load addresses and values"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:261
+msgid "5 instructions for comparison and potential swap"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:262
+msgid "3 instructions for loop control"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:264
+msgid "Total: ~15,000+ instructions for a complete sort."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:267
+msgid "Key Concepts"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:270
+msgid "Nested Loops"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:272
+msgid "Two loop counters working together:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:286
+msgid "Address Calculation"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:288
+msgid "Computing memory addresses dynamically:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:297
+msgid "Conditional Swapping"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:308
+msgid "Exercises"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:310
+msgid "**Count swaps**: Add a counter to track number of swaps"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:311
+msgid "**Optimize**: Add early exit if no swaps occurred in a pass"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:312
+msgid "**Different sizes**: Sort 16 or 64 elements instead"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:313
+msgid "**Descending order**: Modify to sort in descending order"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:314
+msgid "**Different algorithm**: Implement selection sort or insertion sort"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:317
+msgid "Solutions Hints"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:319
+msgid "**Count swaps**: Add ``inc r26`` in the swap section, initialize R26 to 0."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:321
+msgid "**Optimize**: Set a flag when swapping, check it at end of outer loop."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:323
+msgid "**Descending order**: Change ``brcs no_swap`` to ``brcc no_swap``."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:326
+msgid "Visualization Tips"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:328
+msgid "When viewing the animation:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:330
+msgid "**Memory panel**: Watch values \"bubble\" to their positions"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:331
+msgid "**Register panel**: R19 (j) cycles 0-30 repeatedly"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:332
+msgid "**Register panel**: R18 (i) increments slowly"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:334
+msgid "Look for:"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:336
+msgid "Large values moving right (higher addresses)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:337
+msgid "Small values moving left (lower addresses)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:338
+msgid "Progressively fewer changes as array becomes sorted"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:341
+msgid "Comparison with Other Sorts"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:343
+msgid "Sorting Algorithm Comparison"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:347
+msgid "Algorithm"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:349
+msgid "Space"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:350
+msgid "Stability"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:352
+#: ../../examples/bubblesort.rst:356
+#: ../../examples/bubblesort.rst:360
+msgid "O(n²)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:353
+#: ../../examples/bubblesort.rst:357
+#: ../../examples/bubblesort.rst:361
+msgid "O(1)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:354
+#: ../../examples/bubblesort.rst:362
+msgid "Yes"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:355
+msgid "Selection Sort"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:358
+#: ../../examples/bubblesort.rst:366
+msgid "No"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:359
+msgid "Insertion Sort"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:363
+msgid "Quick Sort"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:364
+msgid "O(n log n)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:365
+msgid "O(log n)"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:368
+msgid "Bubble sort is chosen for this example because it's conceptually simple and demonstrates memory operations clearly."
+msgstr ""
+
+#: ../../examples/bubblesort.rst:371
+msgid "Related Examples"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:373
+msgid ":doc:`linear_search` - Sequential array access"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:374
+msgid ":doc:`find_max` - Array comparison operations"
+msgstr ""
+
+#: ../../examples/bubblesort.rst:375
+msgid ":doc:`reverse` - Array manipulation"
+msgstr ""
diff --git a/docs/locales/pot/examples/count_bits.pot b/docs/locales/pot/examples/count_bits.pot
new file mode 100644
index 0000000..ddb1e61
--- /dev/null
+++ b/docs/locales/pot/examples/count_bits.pot
@@ -0,0 +1,29 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:30+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../examples/count_bits.rst:2
+msgid "Count Bits"
+msgstr ""
+
+#: ../../examples/count_bits.rst:4
+msgid "Counts the number of set bits (1s) in a value."
+msgstr ""
+
+#: ../../examples/count_bits.rst:10
+msgid "Demonstrates bit manipulation and counting operations."
+msgstr ""
diff --git a/docs/locales/pot/examples/factorial.pot b/docs/locales/pot/examples/factorial.pot
new file mode 100644
index 0000000..5779c17
--- /dev/null
+++ b/docs/locales/pot/examples/factorial.pot
@@ -0,0 +1,29 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:30+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../examples/factorial.rst:2
+msgid "Factorial"
+msgstr ""
+
+#: ../../examples/factorial.rst:4
+msgid "Computes factorial of a number using iterative multiplication."
+msgstr ""
+
+#: ../../examples/factorial.rst:10
+msgid "Calculates 5! = 120 using repeated multiplication and demonstrates loop control."
+msgstr ""
diff --git a/docs/locales/pot/examples/fibonacci.pot b/docs/locales/pot/examples/fibonacci.pot
new file mode 100644
index 0000000..e37ef46
--- /dev/null
+++ b/docs/locales/pot/examples/fibonacci.pot
@@ -0,0 +1,382 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:30+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../examples/fibonacci.rst:2
+msgid "Fibonacci Sequence"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:4
+msgid "This example calculates the 10th Fibonacci number using an iterative approach."
+msgstr ""
+
+#: ../../examples/fibonacci.rst:7
+msgid "Overview"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:9
+msgid "**Difficulty**: Beginner"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:11
+msgid "**Concepts**: Loops, register arithmetic, conditional branching"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:13
+msgid "**Output**: R17 contains F(10) = 55"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:16
+msgid "The Program"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:23
+msgid "Algorithm Explanation"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:25
+msgid "The Fibonacci sequence is defined as:"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:27
+msgid "F(0) = 0"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:28
+msgid "F(1) = 1"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:29
+msgid "F(n) = F(n-1) + F(n-2) for n > 1"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:31
+msgid "This program uses an iterative approach with three registers:"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:33
+msgid "**R16**: Previous Fibonacci number (F(n-1))"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:34
+msgid "**R17**: Current Fibonacci number (F(n))"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:35
+msgid "**R18**: Counter (remaining iterations)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:38
+msgid "Step-by-Step Walkthrough"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:41
+msgid "Initialization (Lines 8-10)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:49
+msgid "We start with F(0) = 0 and F(1) = 1. Since we want F(10), we need 9 more iterations (F(2) through F(10))."
+msgstr ""
+
+#: ../../examples/fibonacci.rst:52
+msgid "Main Loop (Lines 12-18)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:64
+msgid "Each iteration:"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:66
+msgid "**Add**: Compute next Fibonacci number (R16 + R17)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:67
+msgid "**Save**: Store result in temporary register R19"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:68
+msgid "**Shift**: Move R17 to R16 (previous ← current)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:69
+msgid "**Update**: Move R19 to R17 (current ← new result)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:70
+msgid "**Decrement**: Decrease counter"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:71
+msgid "**Branch**: Loop if counter ≠ 0"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:74
+msgid "Execution Trace"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:76
+msgid "Here's how the registers evolve:"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:78
+msgid "Fibonacci Calculation"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:82
+msgid "Iter"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:83
+msgid "R16 (prev)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:84
+msgid "R17 (curr)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:85
+msgid "R18 (count)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:86
+msgid "Calculation"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:87
+msgid "Init"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:88
+#: ../../examples/fibonacci.rst:135
+msgid "0"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:89
+#: ../../examples/fibonacci.rst:92
+#: ../../examples/fibonacci.rst:93
+#: ../../examples/fibonacci.rst:94
+#: ../../examples/fibonacci.rst:98
+#: ../../examples/fibonacci.rst:130
+msgid "1"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:90
+#: ../../examples/fibonacci.rst:132
+msgid "9"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:91
+msgid "F(0), F(1)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:95
+#: ../../examples/fibonacci.rst:114
+#: ../../examples/fibonacci.rst:118
+#: ../../examples/fibonacci.rst:127
+msgid "8"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:96
+msgid "F(2) = 0 + 1 = 1"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:97
+#: ../../examples/fibonacci.rst:99
+#: ../../examples/fibonacci.rst:103
+#: ../../examples/fibonacci.rst:125
+msgid "2"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:100
+#: ../../examples/fibonacci.rst:122
+msgid "7"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:101
+msgid "F(3) = 1 + 1 = 2"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:102
+#: ../../examples/fibonacci.rst:104
+#: ../../examples/fibonacci.rst:108
+#: ../../examples/fibonacci.rst:120
+msgid "3"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:105
+#: ../../examples/fibonacci.rst:117
+msgid "6"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:106
+msgid "F(4) = 1 + 2 = 3"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:107
+#: ../../examples/fibonacci.rst:115
+msgid "4"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:109
+#: ../../examples/fibonacci.rst:110
+#: ../../examples/fibonacci.rst:112
+#: ../../examples/fibonacci.rst:113
+msgid "5"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:111
+msgid "F(5) = 2 + 3 = 5"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:116
+msgid "F(6) = 3 + 5 = 8"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:119
+#: ../../examples/fibonacci.rst:123
+msgid "13"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:121
+msgid "F(7) = 5 + 8 = 13"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:124
+#: ../../examples/fibonacci.rst:128
+msgid "21"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:126
+msgid "F(8) = 8 + 13 = 21"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:129
+#: ../../examples/fibonacci.rst:133
+msgid "34"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:131
+msgid "F(9) = 13 + 21 = 34"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:134
+msgid "55"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:136
+msgid "F(10) = 21 + 34 = 55"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:139
+msgid "Running the Example"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:142
+msgid "Interactive Debugger"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:148
+msgid "Step through with ``j`` and watch registers R16, R17, and R18 evolve."
+msgstr ""
+
+#: ../../examples/fibonacci.rst:151
+msgid "Animation"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:157
+msgid "Visualize the register changes over time."
+msgstr ""
+
+#: ../../examples/fibonacci.rst:160
+msgid "Python API"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:173
+msgid "Key Concepts"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:176
+msgid "Loop Structure"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:178
+msgid "The loop pattern is common in assembly:"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:189
+msgid "Register Shifting"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:191
+msgid "Moving values between registers for state management:"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:199
+msgid "This \"register rotation\" is a fundamental technique in assembly programming."
+msgstr ""
+
+#: ../../examples/fibonacci.rst:202
+msgid "Exercises"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:204
+msgid "**Modify the counter**: Calculate F(15) instead of F(10)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:205
+msgid "**Different starting values**: Try F(0) = 1, F(1) = 1 (alternative definition)"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:206
+msgid "**Store in memory**: Save each Fibonacci number to memory"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:207
+msgid "**Detect overflow**: Check when the result exceeds 255"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:210
+msgid "Solutions"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:212
+msgid "**F(15) modification**:"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:218
+msgid "Note: F(15) = 610, which exceeds 8-bit range (wraps to 98)."
+msgstr ""
+
+#: ../../examples/fibonacci.rst:220
+msgid "**Store in memory**:"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:232
+msgid "Related Examples"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:234
+msgid ":doc:`factorial` - Another iterative calculation"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:235
+msgid ":doc:`sum_1_to_n` - Similar loop structure"
+msgstr ""
+
+#: ../../examples/fibonacci.rst:236
+msgid ":doc:`power` - Repeated operation pattern"
+msgstr ""
diff --git a/docs/locales/pot/examples/find_max.pot b/docs/locales/pot/examples/find_max.pot
new file mode 100644
index 0000000..ec8d382
--- /dev/null
+++ b/docs/locales/pot/examples/find_max.pot
@@ -0,0 +1,29 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:30+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../examples/find_max.rst:2
+msgid "Find Maximum"
+msgstr ""
+
+#: ../../examples/find_max.rst:4
+msgid "Finds the maximum value in an array."
+msgstr ""
+
+#: ../../examples/find_max.rst:10
+msgid "Demonstrates comparison operations and conditional logic."
+msgstr ""
diff --git a/docs/locales/pot/examples/gcd.pot b/docs/locales/pot/examples/gcd.pot
new file mode 100644
index 0000000..1eb3d12
--- /dev/null
+++ b/docs/locales/pot/examples/gcd.pot
@@ -0,0 +1,29 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:30+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../examples/gcd.rst:2
+msgid "GCD (Greatest Common Divisor)"
+msgstr ""
+
+#: ../../examples/gcd.rst:4
+msgid "Computes the GCD of two numbers using Euclidean algorithm."
+msgstr ""
+
+#: ../../examples/gcd.rst:10
+msgid "Demonstrates subtraction-based Euclidean algorithm and conditional comparison."
+msgstr ""
diff --git a/docs/locales/pot/examples/hello_world.pot b/docs/locales/pot/examples/hello_world.pot
new file mode 100644
index 0000000..0c0b091
--- /dev/null
+++ b/docs/locales/pot/examples/hello_world.pot
@@ -0,0 +1,29 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:30+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../examples/hello_world.rst:2
+msgid "Hello World"
+msgstr ""
+
+#: ../../examples/hello_world.rst:4
+msgid "A minimal Tiny8 program demonstrating basic structure."
+msgstr ""
+
+#: ../../examples/hello_world.rst:10
+msgid "This program demonstrates the simplest possible Tiny8 program structure with initialization and an infinite loop."
+msgstr ""
diff --git a/docs/locales/pot/examples/index.pot b/docs/locales/pot/examples/index.pot
new file mode 100644
index 0000000..5fa0ad5
--- /dev/null
+++ b/docs/locales/pot/examples/index.pot
@@ -0,0 +1,369 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:30+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../examples/index.rst:2
+msgid "Examples"
+msgstr ""
+
+#: ../../examples/index.rst:4
+msgid "This section contains detailed walkthroughs of example programs that demonstrate Tiny8's capabilities and teach assembly programming concepts."
+msgstr ""
+
+#: ../../examples/index.rst:7
+msgid "Overview"
+msgstr ""
+
+#: ../../examples/index.rst:9
+msgid "The examples are organized by complexity and concept:"
+msgstr ""
+
+#: ../../examples/index.rst:11
+msgid "**Basic Examples**"
+msgstr ""
+
+#: ../../examples/index.rst:12
+msgid "Simple programs demonstrating fundamental operations"
+msgstr ""
+
+#: ../../examples/index.rst:14
+msgid "**Intermediate Examples**"
+msgstr ""
+
+#: ../../examples/index.rst:15
+msgid "Programs using loops, conditionals, and memory operations"
+msgstr ""
+
+#: ../../examples/index.rst:17
+msgid "**Advanced Examples**"
+msgstr ""
+
+#: ../../examples/index.rst:18
+msgid "Complex algorithms including sorting and mathematical computations"
+msgstr ""
+
+#: ../../examples/index.rst:20
+msgid "All examples are available in the ``examples/`` directory of the Tiny8 repository."
+msgstr ""
+
+#: ../../examples/index.rst:23
+msgid "Running Examples"
+msgstr ""
+
+#: ../../examples/index.rst:25
+msgid "You can run any example with the interactive debugger:"
+msgstr ""
+
+#: ../../examples/index.rst:31
+msgid "Or use the Python API:"
+msgstr ""
+
+#: ../../examples/index.rst:42
+msgid "Example Programs"
+msgstr ""
+
+#: ../../examples/index.rst:45
+msgid "Basic Examples"
+msgstr ""
+
+#: ../../examples/index.rst:55
+msgid "Intermediate Examples"
+msgstr ""
+
+#: ../../examples/index.rst:67
+msgid "Advanced Examples"
+msgstr ""
+
+#: ../../examples/index.rst:81
+msgid "C Language Programs & Interactive Demos"
+msgstr ""
+
+#: ../../examples/index.rst:83
+msgid "Tiny8 includes an embedded C subset compiler capable of compiling and running C programs directly on the simulated CPU:"
+msgstr ""
+
+#: ../../examples/index.rst:85
+msgid "**factorial.c**: Recursive factorial calculation demonstration."
+msgstr ""
+
+#: ../../examples/index.rst:86
+msgid "**mnist_heatmap.c**: 28x28 MNIST real digit heatmap transfer to 32x32 VRAM."
+msgstr ""
+
+#: ../../examples/index.rst:89
+msgid "Quick Reference"
+msgstr ""
+
+#: ../../examples/index.rst:91
+msgid "Example Summary"
+msgstr ""
+
+#: ../../examples/index.rst:95
+msgid "Program"
+msgstr ""
+
+#: ../../examples/index.rst:96
+msgid "Concept"
+msgstr ""
+
+#: ../../examples/index.rst:97
+msgid "Key Instructions / Language"
+msgstr ""
+
+#: ../../examples/index.rst:98
+msgid "Hello World"
+msgstr ""
+
+#: ../../examples/index.rst:99
+msgid "Basic memory writing"
+msgstr ""
+
+#: ../../examples/index.rst:100
+msgid "LDI, ST, INC, JMP"
+msgstr ""
+
+#: ../../examples/index.rst:101
+msgid "Fibonacci"
+msgstr ""
+
+#: ../../examples/index.rst:102
+msgid "Iterative sequence"
+msgstr ""
+
+#: ../../examples/index.rst:103
+msgid "ADD, MOV, DEC, BRNE"
+msgstr ""
+
+#: ../../examples/index.rst:104
+msgid "Factorial (ASM)"
+msgstr ""
+
+#: ../../examples/index.rst:105
+msgid "Iterative multiplication"
+msgstr ""
+
+#: ../../examples/index.rst:106
+msgid "MUL, DEC, CPI, BRGE"
+msgstr ""
+
+#: ../../examples/index.rst:107
+msgid "Factorial (C)"
+msgstr ""
+
+#: ../../examples/index.rst:108
+msgid "Recursive function calls"
+msgstr ""
+
+#: ../../examples/index.rst:109
+msgid "C Compiler (CALL, RET, PUSH, POP)"
+msgstr ""
+
+#: ../../examples/index.rst:110
+msgid "Sum 1 to N"
+msgstr ""
+
+#: ../../examples/index.rst:111
+msgid "Loop accumulation"
+msgstr ""
+
+#: ../../examples/index.rst:112
+msgid "ADD, INC, CP, BRLT, BREQ"
+msgstr ""
+
+#: ../../examples/index.rst:113
+msgid "Array Sum"
+msgstr ""
+
+#: ../../examples/index.rst:114
+msgid "Pointer iteration"
+msgstr ""
+
+#: ../../examples/index.rst:115
+msgid "LD, ST, ADD, INC, BRNE"
+msgstr ""
+
+#: ../../examples/index.rst:116
+msgid "Find Max"
+msgstr ""
+
+#: ../../examples/index.rst:117
+msgid "Array scanning & comparison"
+msgstr ""
+
+#: ../../examples/index.rst:118
+msgid "LD, ST, CP, BRGE, MOV"
+msgstr ""
+
+#: ../../examples/index.rst:119
+msgid "Linear Search"
+msgstr ""
+
+#: ../../examples/index.rst:120
+msgid "Target search & sentinel"
+msgstr ""
+
+#: ../../examples/index.rst:121
+msgid "LD, ST, CP, BREQ, INC"
+msgstr ""
+
+#: ../../examples/index.rst:122
+msgid "Memory Copy"
+msgstr ""
+
+#: ../../examples/index.rst:123
+msgid "Block memory transfer"
+msgstr ""
+
+#: ../../examples/index.rst:124
+msgid "LD, ST, INC, DEC, BRNE"
+msgstr ""
+
+#: ../../examples/index.rst:125
+msgid "Bubble Sort"
+msgstr ""
+
+#: ../../examples/index.rst:126
+msgid "PRNG & in-place sort"
+msgstr ""
+
+#: ../../examples/index.rst:127
+msgid "MUL, LD, ST, CP, BRCS"
+msgstr ""
+
+#: ../../examples/index.rst:128
+msgid "GCD"
+msgstr ""
+
+#: ../../examples/index.rst:129
+msgid "Euclidean algorithm"
+msgstr ""
+
+#: ../../examples/index.rst:130
+msgid "DIV, MOV, CPI, BREQ"
+msgstr ""
+
+#: ../../examples/index.rst:131
+msgid "Power"
+msgstr ""
+
+#: ../../examples/index.rst:132
+msgid "Exponentiation"
+msgstr ""
+
+#: ../../examples/index.rst:133
+msgid "MUL, INC, CP, BRLT"
+msgstr ""
+
+#: ../../examples/index.rst:134
+msgid "Multiply by Shift"
+msgstr ""
+
+#: ../../examples/index.rst:135
+msgid "Binary shift multiplication"
+msgstr ""
+
+#: ../../examples/index.rst:136
+msgid "LSL, LSR, ANDI, ADD"
+msgstr ""
+
+#: ../../examples/index.rst:137
+msgid "Count Bits"
+msgstr ""
+
+#: ../../examples/index.rst:138
+msgid "Bit testing & division"
+msgstr ""
+
+#: ../../examples/index.rst:139
+msgid "AND, DIV, CPI, BRNE"
+msgstr ""
+
+#: ../../examples/index.rst:140
+msgid "Is Prime"
+msgstr ""
+
+#: ../../examples/index.rst:141
+msgid "Trial division"
+msgstr ""
+
+#: ../../examples/index.rst:142
+msgid "DIV, MUL, CP, BRGE, BRLT"
+msgstr ""
+
+#: ../../examples/index.rst:143
+msgid "Reverse Array"
+msgstr ""
+
+#: ../../examples/index.rst:144
+msgid "Two-pointer array reverse"
+msgstr ""
+
+#: ../../examples/index.rst:145
+msgid "LD, ST, CP, BRGE, INC, DEC"
+msgstr ""
+
+#: ../../examples/index.rst:146
+msgid "MNIST Heatmap (C)"
+msgstr ""
+
+#: ../../examples/index.rst:147
+msgid "28x28 digit VRAM heatmap"
+msgstr ""
+
+#: ../../examples/index.rst:148
+msgid "C (VRAM 0x0200..0x05FF)"
+msgstr ""
+
+#: ../../examples/index.rst:149
+msgid "MNIST Diffusion (ASM)"
+msgstr ""
+
+#: ../../examples/index.rst:150
+msgid "Iterative reverse-diffusion synthesis"
+msgstr ""
+
+#: ../../examples/index.rst:151
+msgid "ASM (diffusion_mnist8.asm)"
+msgstr ""
+
+#: ../../examples/index.rst:154
+msgid "Learning Path"
+msgstr ""
+
+#: ../../examples/index.rst:156
+msgid "Recommended order for learning:"
+msgstr ""
+
+#: ../../examples/index.rst:158
+msgid "**Start with basics**: hello_world, fibonacci, factorial"
+msgstr ""
+
+#: ../../examples/index.rst:159
+msgid "**Learn memory**: array_sum, memory_copy, find_max"
+msgstr ""
+
+#: ../../examples/index.rst:160
+msgid "**Master control flow**: linear_search, gcd"
+msgstr ""
+
+#: ../../examples/index.rst:161
+msgid "**Tackle algorithms**: bubblesort, power, is_prime"
+msgstr ""
+
+#: ../../examples/index.rst:162
+msgid "**Explore bit operations**: multiply_by_shift, count_bits"
+msgstr ""
diff --git a/docs/locales/pot/examples/is_prime.pot b/docs/locales/pot/examples/is_prime.pot
new file mode 100644
index 0000000..8a58729
--- /dev/null
+++ b/docs/locales/pot/examples/is_prime.pot
@@ -0,0 +1,29 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:30+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../examples/is_prime.rst:2
+msgid "Is Prime"
+msgstr ""
+
+#: ../../examples/is_prime.rst:4
+msgid "Tests whether a number is prime."
+msgstr ""
+
+#: ../../examples/is_prime.rst:10
+msgid "Demonstrates trial division and number theory concepts."
+msgstr ""
diff --git a/docs/locales/pot/examples/linear_search.pot b/docs/locales/pot/examples/linear_search.pot
new file mode 100644
index 0000000..0541338
--- /dev/null
+++ b/docs/locales/pot/examples/linear_search.pot
@@ -0,0 +1,29 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:30+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../examples/linear_search.rst:2
+msgid "Linear Search"
+msgstr ""
+
+#: ../../examples/linear_search.rst:4
+msgid "Searches for a value in an array."
+msgstr ""
+
+#: ../../examples/linear_search.rst:10
+msgid "Demonstrates sequential search and early loop exit."
+msgstr ""
diff --git a/docs/locales/pot/examples/memory_copy.pot b/docs/locales/pot/examples/memory_copy.pot
new file mode 100644
index 0000000..6b770cd
--- /dev/null
+++ b/docs/locales/pot/examples/memory_copy.pot
@@ -0,0 +1,29 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:30+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../examples/memory_copy.rst:2
+msgid "Memory Copy"
+msgstr ""
+
+#: ../../examples/memory_copy.rst:4
+msgid "Copies data from one memory location to another."
+msgstr ""
+
+#: ../../examples/memory_copy.rst:10
+msgid "Demonstrates memory-to-memory data transfer."
+msgstr ""
diff --git a/docs/locales/pot/examples/multiply_by_shift.pot b/docs/locales/pot/examples/multiply_by_shift.pot
new file mode 100644
index 0000000..57ab49f
--- /dev/null
+++ b/docs/locales/pot/examples/multiply_by_shift.pot
@@ -0,0 +1,29 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:30+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../examples/multiply_by_shift.rst:2
+msgid "Multiply by Shift"
+msgstr ""
+
+#: ../../examples/multiply_by_shift.rst:4
+msgid "Multiplies numbers using bit shifting instead of MUL instruction."
+msgstr ""
+
+#: ../../examples/multiply_by_shift.rst:10
+msgid "Demonstrates bit manipulation and efficient multiplication."
+msgstr ""
diff --git a/docs/locales/pot/examples/power.pot b/docs/locales/pot/examples/power.pot
new file mode 100644
index 0000000..cb23ad4
--- /dev/null
+++ b/docs/locales/pot/examples/power.pot
@@ -0,0 +1,29 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:30+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../examples/power.rst:2
+msgid "Power Function"
+msgstr ""
+
+#: ../../examples/power.rst:4
+msgid "Computes x^n using repeated multiplication."
+msgstr ""
+
+#: ../../examples/power.rst:10
+msgid "Demonstrates exponentiation through iteration."
+msgstr ""
diff --git a/docs/locales/pot/examples/reverse.pot b/docs/locales/pot/examples/reverse.pot
new file mode 100644
index 0000000..b4cfe03
--- /dev/null
+++ b/docs/locales/pot/examples/reverse.pot
@@ -0,0 +1,29 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:30+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../examples/reverse.rst:2
+msgid "Reverse Array"
+msgstr ""
+
+#: ../../examples/reverse.rst:4
+msgid "Reverses an array in place."
+msgstr ""
+
+#: ../../examples/reverse.rst:10
+msgid "Demonstrates two-pointer technique and array manipulation."
+msgstr ""
diff --git a/docs/locales/pot/examples/sum_1_to_n.pot b/docs/locales/pot/examples/sum_1_to_n.pot
new file mode 100644
index 0000000..b518325
--- /dev/null
+++ b/docs/locales/pot/examples/sum_1_to_n.pot
@@ -0,0 +1,29 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:30+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../examples/sum_1_to_n.rst:2
+msgid "Sum 1 to N"
+msgstr ""
+
+#: ../../examples/sum_1_to_n.rst:4
+msgid "Calculates the sum of integers from 1 to N."
+msgstr ""
+
+#: ../../examples/sum_1_to_n.rst:10
+msgid "Demonstrates accumulation pattern and loop control."
+msgstr ""
diff --git a/docs/locales/pot/getting_started.pot b/docs/locales/pot/getting_started.pot
new file mode 100644
index 0000000..9ba910c
--- /dev/null
+++ b/docs/locales/pot/getting_started.pot
@@ -0,0 +1,289 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-24 22:30+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../getting_started.rst:2
+msgid "Getting Started"
+msgstr ""
+
+#: ../../getting_started.rst:4
+msgid "This guide will help you get started with Tiny8, from installation to running your first programs."
+msgstr ""
+
+#: ../../getting_started.rst:7
+msgid "Installation"
+msgstr ""
+
+#: ../../getting_started.rst:10
+msgid "Requirements"
+msgstr ""
+
+#: ../../getting_started.rst:12
+msgid "Tiny8 requires Python 3.11 or later. Check your Python version:"
+msgstr ""
+
+#: ../../getting_started.rst:19
+msgid "Installing Tiny8"
+msgstr ""
+
+#: ../../getting_started.rst:21
+msgid "Install Tiny8 using pip:"
+msgstr ""
+
+#: ../../getting_started.rst:27
+msgid "This will install the ``tiny8`` command-line tool and make the Python API available for import."
+msgstr ""
+
+#: ../../getting_started.rst:30
+msgid "Verifying Installation"
+msgstr ""
+
+#: ../../getting_started.rst:32
+msgid "Verify that Tiny8 is installed correctly:"
+msgstr ""
+
+#: ../../getting_started.rst:38
+msgid "You should see the version number printed to the terminal."
+msgstr ""
+
+#: ../../getting_started.rst:41
+msgid "Your First Program"
+msgstr ""
+
+#: ../../getting_started.rst:43
+msgid "Let's write a simple program that adds two numbers."
+msgstr ""
+
+#: ../../getting_started.rst:46
+msgid "Create the Assembly File"
+msgstr ""
+
+#: ../../getting_started.rst:48
+msgid "Create a new file called ``add.asm`` with the following content:"
+msgstr ""
+
+#: ../../getting_started.rst:63
+msgid "Understanding the Code"
+msgstr ""
+
+#: ../../getting_started.rst:65
+msgid "Let's break down what each line does:"
+msgstr ""
+
+#: ../../getting_started.rst:67
+msgid "``ldi r16, 5`` - **L** oa **d** **I** mmediate: Loads the value 5 directly into register 16"
+msgstr ""
+
+#: ../../getting_started.rst:68
+msgid "``ldi r17, 3`` - Loads the value 3 into register 17"
+msgstr ""
+
+#: ../../getting_started.rst:69
+msgid "``add r16, r17`` - Adds the contents of R17 to R16, storing the result in R16"
+msgstr ""
+
+#: ../../getting_started.rst:70
+msgid "``jmp done`` - Jumps to the label ``done``, creating an infinite loop"
+msgstr ""
+
+#: ../../getting_started.rst:73
+msgid "Lines starting with ``;`` are comments and are ignored by the assembler."
+msgstr ""
+
+#: ../../getting_started.rst:76
+msgid "Running with the Interactive Debugger"
+msgstr ""
+
+#: ../../getting_started.rst:78
+msgid "Run your program using the Tiny8 interactive debugger:"
+msgstr ""
+
+#: ../../getting_started.rst:84
+msgid "You'll see a terminal-based interface showing:"
+msgstr ""
+
+#: ../../getting_started.rst:86
+msgid "**Source code** - Your assembly program with the current instruction highlighted"
+msgstr ""
+
+#: ../../getting_started.rst:87
+msgid "**Registers** - The 32 general-purpose registers (R0-R31)"
+msgstr ""
+
+#: ../../getting_started.rst:88
+msgid "**Status flags** - The SREG flags (I, T, H, S, V, N, Z, C)"
+msgstr ""
+
+#: ../../getting_started.rst:89
+msgid "**Memory** - RAM contents"
+msgstr ""
+
+#: ../../getting_started.rst:90
+msgid "**Control information** - Program counter (PC), stack pointer (SP), and step count"
+msgstr ""
+
+#: ../../getting_started.rst:93
+msgid "Debugger Controls"
+msgstr ""
+
+#: ../../getting_started.rst:95
+msgid "Use these keyboard shortcuts to control execution:"
+msgstr ""
+
+#: ../../getting_started.rst:97
+msgid "**Execution:**"
+msgstr ""
+
+#: ../../getting_started.rst:99
+msgid "``Space`` - Play / pause automatic continuous execution"
+msgstr ""
+
+#: ../../getting_started.rst:100
+msgid "``Shift+Space`` - Reverse playback execution"
+msgstr ""
+
+#: ../../getting_started.rst:101
+msgid "``n`` - Step forward 1 instruction (+1 step)"
+msgstr ""
+
+#: ../../getting_started.rst:102
+msgid "``p`` - Step backward 1 instruction (-1 step, time-travel)"
+msgstr ""
+
+#: ../../getting_started.rst:103
+msgid "``c`` - Continue forward to next breakpoint"
+msgstr ""
+
+#: ../../getting_started.rst:104
+msgid "``C`` (``Shift+c``) - Reverse continue backward to previous breakpoint"
+msgstr ""
+
+#: ../../getting_started.rst:105
+msgid "``b`` - Toggle breakpoint at current PC"
+msgstr ""
+
+#: ../../getting_started.rst:106
+msgid "``+`` / ``-`` - Increase / decrease playback speed"
+msgstr ""
+
+#: ../../getting_started.rst:107
+msgid "``r`` - Reset execution back to Step 0"
+msgstr ""
+
+#: ../../getting_started.rst:109
+msgid "**Display & Navigation:**"
+msgstr ""
+
+#: ../../getting_started.rst:111
+msgid "``j`` / ``k`` - Scroll memory view down / up by 32 bytes (1 row)"
+msgstr ""
+
+#: ../../getting_started.rst:112
+msgid "``J`` / ``K`` - Fast scroll memory view down / up by 128 bytes (4 rows)"
+msgstr ""
+
+#: ../../getting_started.rst:113
+msgid "``g`` - Toggle Grayscale / Viridis color palette"
+msgstr ""
+
+#: ../../getting_started.rst:114
+msgid "``x`` - Toggle Hexadecimal (02X) / Graphic Pixel blocks"
+msgstr ""
+
+#: ../../getting_started.rst:115
+msgid "``m`` - Cycle view modes"
+msgstr ""
+
+#: ../../getting_started.rst:116
+msgid "``i`` - Inspect details of currently executing instruction"
+msgstr ""
+
+#: ../../getting_started.rst:117
+msgid "``h`` or ``?`` - Open full help and keyboard guide modal"
+msgstr ""
+
+#: ../../getting_started.rst:118
+msgid "``e`` - Open built-in Vim modal editor"
+msgstr ""
+
+#: ../../getting_started.rst:120
+msgid "**Command Bar Prompt:**"
+msgstr ""
+
+#: ../../getting_started.rst:122
+msgid "``:`` - Enter command prompt (e.g. ``:goto <step>``, ``:b <pc>``, ``:q``)"
+msgstr ""
+
+#: ../../getting_started.rst:124
+msgid "**Exit:**"
+msgstr ""
+
+#: ../../getting_started.rst:126
+msgid "``q`` - Quit debugger"
+msgstr ""
+
+#: ../../getting_started.rst:128
+msgid "Try stepping through your program with ``n`` and watch how the registers change!"
+msgstr ""
+
+#: ../../getting_started.rst:131
+msgid "Running from Python"
+msgstr ""
+
+#: ../../getting_started.rst:133
+msgid "You can also run Tiny8 programs from Python code."
+msgstr ""
+
+#: ../../getting_started.rst:136
+msgid "Basic Execution"
+msgstr ""
+
+#: ../../getting_started.rst:158
+msgid "Step-by-Step Execution"
+msgstr ""
+
+#: ../../getting_started.rst:160
+msgid "For more control, you can step through the program manually:"
+msgstr ""
+
+#: ../../getting_started.rst:188
+msgid "Inspecting CPU State"
+msgstr ""
+
+#: ../../getting_started.rst:190
+msgid "You can inspect various aspects of the CPU state:"
+msgstr ""
+
+#: ../../getting_started.rst:209
+msgid "Common Assembly Patterns"
+msgstr ""
+
+#: ../../getting_started.rst:212
+msgid "Loading Immediate Values"
+msgstr ""
+
+#: ../../getting_started.rst:221
+msgid "Working with Memory"
+msgstr ""
+
+#: ../../getting_started.rst:233
+msgid "Loops"
+msgstr ""
+
+#: ../../getting_started.rst:247
+msgid "Conditional Branching"
+msgstr ""
diff --git a/docs/locales/pot/index.pot b/docs/locales/pot/index.pot
new file mode 100644
index 0000000..dfd7b94
--- /dev/null
+++ b/docs/locales/pot/index.pot
@@ -0,0 +1,181 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-25 01:27+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../index.rst:117
+msgid "User Guide"
+msgstr ""
+
+#: ../../index.rst:126
+msgid "Examples"
+msgstr ""
+
+#: ../../index.rst:132
+msgid "API Reference"
+msgstr ""
+
+#: ../../index.rst:4
+msgid "Tiny8 Documentation"
+msgstr ""
+
+#: ../../index.rst:6
+msgid "**From bare-metal computer architecture to Generative AI — an educational 8-bit AVR RISC CPU simulator with real-time interactive visualization**"
+msgstr ""
+
+#: ../../index.rst:8
+msgid "Tiny8 is a lightweight educational toolkit that bridges bare-metal computer architecture and modern Generative AI. Designed for hands-on learning and experimentation, it guides you through the full stack of computing — from 32 general-purpose registers, ALU operations, stack frames, and C compilation up to executing an iterative reverse-diffusion model synthesizing 28x28 MNIST digits directly on an AVR 8-bit RISC processor. With an interactive Vim-inspired terminal debugger, time-travel reverse execution, and a 32x32 TrueColor memory heatmap, Tiny8 lets you see, step through, and understand computation at every level."
+msgstr ""
+
+#: ../../index.rst:10
+msgid "Animated bubble sort visualization"
+msgstr ""
+
+#: ../../index.rst:16
+msgid "Real-time visualization of a bubble sort algorithm executing on Tiny8"
+msgstr ""
+
+#: ../../index.rst:18
+msgid "Features"
+msgstr ""
+
+#: ../../index.rst:21
+msgid "Interactive Terminal Debugger"
+msgstr ""
+
+#: ../../index.rst:23
+msgid "CLI visualizer screenshot"
+msgstr ""
+
+#: ../../index.rst:28
+msgid "**Vim-style navigation**: Step through execution with intuitive keyboard controls"
+msgstr ""
+
+#: ../../index.rst:29
+msgid "**Change highlighting**: See exactly what changed at each step (registers, flags, memory)"
+msgstr ""
+
+#: ../../index.rst:30
+msgid "**Time-travel debugging**: Step forward and backward with sparse checkpoint restoration"
+msgstr ""
+
+#: ../../index.rst:31
+msgid "**32x32 TrueColor Heatmap**: VRAM memory matrix with Viridis/Grayscale visualization"
+msgstr ""
+
+#: ../../index.rst:32
+msgid "**Built-in Vim Editor**: Launch full-screen modal editor anytime with ``e``"
+msgstr ""
+
+#: ../../index.rst:33
+msgid "**Internationalization**: English (en) and Japanese (ja) localization support"
+msgstr ""
+
+#: ../../index.rst:36
+msgid "Complete 8-bit Architecture"
+msgstr ""
+
+#: ../../index.rst:38
+msgid "**32 general-purpose registers** (R0-R31)"
+msgstr ""
+
+#: ../../index.rst:39
+msgid "**8-bit ALU** with arithmetic, logical, and bit manipulation operations"
+msgstr ""
+
+#: ../../index.rst:40
+msgid "**Status register (SREG)** with 8 condition flags"
+msgstr ""
+
+#: ../../index.rst:41
+msgid "**64KB address space** for unified memory and I/O"
+msgstr ""
+
+#: ../../index.rst:42
+msgid "**Stack operations** with dedicated stack pointer"
+msgstr ""
+
+#: ../../index.rst:43
+msgid "**AVR instruction set** with 67 instructions compliant with Microchip DS40002198A"
+msgstr ""
+
+#: ../../index.rst:46
+msgid "Educational Focus"
+msgstr ""
+
+#: ../../index.rst:48
+msgid "Clean, readable Python implementation"
+msgstr ""
+
+#: ../../index.rst:49
+msgid "Comprehensive examples (Fibonacci, bubble sort, factorial, and more)"
+msgstr ""
+
+#: ../../index.rst:50
+msgid "Step-by-step execution traces for debugging"
+msgstr ""
+
+#: ../../index.rst:51
+msgid "Full API documentation and instruction set reference"
+msgstr ""
+
+#: ../../index.rst:54
+msgid "Quick Start"
+msgstr ""
+
+#: ../../index.rst:57
+msgid "Installation"
+msgstr ""
+
+#: ../../index.rst:59
+msgid "Install Tiny8 using pip:"
+msgstr ""
+
+#: ../../index.rst:66
+msgid "Your First Program"
+msgstr ""
+
+#: ../../index.rst:68
+msgid "Create a file called ``fibonacci.asm``:"
+msgstr ""
+
+#: ../../index.rst:90
+msgid "Run it with the interactive debugger:"
+msgstr ""
+
+#: ../../index.rst:97
+msgid "Using the Python API"
+msgstr ""
+
+#: ../../index.rst:115
+msgid "Documentation Contents"
+msgstr ""
+
+#: ../../index.rst:139
+msgid "Indices and Tables"
+msgstr ""
+
+#: ../../index.rst:141
+msgid ":ref:`genindex`"
+msgstr ""
+
+#: ../../index.rst:142
+msgid ":ref:`modindex`"
+msgstr ""
+
+#: ../../index.rst:143
+msgid ":ref:`search`"
+msgstr ""
diff --git a/docs/locales/pot/visualization.pot b/docs/locales/pot/visualization.pot
new file mode 100644
index 0000000..d89a46b
--- /dev/null
+++ b/docs/locales/pot/visualization.pot
@@ -0,0 +1,343 @@
+# SOME DESCRIPTIVE TITLE.
+# Copyright (C) 2025, sql-hkr
+# This file is distributed under the same license as the Tiny8 package.
+# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
+#
+#, fuzzy
+msgid ""
+msgstr ""
+"Project-Id-Version: Tiny8 0.2.0\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2026-10-25 00:49+0900\n"
+"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
+"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
+"Language-Team: LANGUAGE <LL@li.org>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: ../../visualization.rst:2
+msgid "Visualization & Debugger"
+msgstr ""
+
+#: ../../visualization.rst:4
+msgid "Tiny8 features a modern, real-time terminal visualizer and visual debugger powered by `Textual <https://textual.textualize.io/>`_. It provides interactive execution controls, sparse checkpoint time-travel, a 32x32 TrueColor memory heatmap, and a full-screen built-in modal editor."
+msgstr ""
+
+#: ../../visualization.rst:7
+msgid "Launching the TUI"
+msgstr ""
+
+#: ../../visualization.rst:9
+msgid "To run any assembly or C program with the interactive debugger:"
+msgstr ""
+
+#: ../../visualization.rst:16
+msgid "You can also specify options such as step limits or editor launch:"
+msgstr ""
+
+#: ../../visualization.rst:30
+msgid "Interface Overview"
+msgstr ""
+
+#: ../../visualization.rst:32
+msgid "Real-time generative reverse-diffusion synthesis (MNIST 8) at x5,000 speed in Tiny8 TUI (Viridis Palette, Forward Pixel + Reverse Hex)"
+msgstr ""
+
+#: ../../visualization.rst:37
+msgid "*Real-time generative reverse-diffusion synthesis (MNIST 8) executing at x5,000 speed in Tiny8 TUI (Viridis Palette: Forward Pixel + Reverse Hex)*"
+msgstr ""
+
+#: ../../visualization.rst:39
+msgid "Real-time generative reverse-diffusion synthesis (MNIST 8) at x5,000 speed in Tiny8 TUI (Grayscale Palette, Forward Pixel + Reverse Hex)"
+msgstr ""
+
+#: ../../visualization.rst:44
+msgid "*Real-time generative reverse-diffusion synthesis (MNIST 8) executing at x5,000 speed in Tiny8 TUI (Grayscale Palette: Forward Pixel + Reverse Hex)*"
+msgstr ""
+
+#: ../../visualization.rst:46
+msgid "The debugger interface provides real-time reactive panels:"
+msgstr ""
+
+#: ../../visualization.rst:66
+msgid "Interactive Controls"
+msgstr ""
+
+#: ../../visualization.rst:69
+msgid "Execution & Time-Travel"
+msgstr ""
+
+#: ../../visualization.rst:75
+#: ../../visualization.rst:105
+msgid "Key"
+msgstr ""
+
+#: ../../visualization.rst:76
+#: ../../visualization.rst:106
+msgid "Action"
+msgstr ""
+
+#: ../../visualization.rst:77
+msgid "``Space``"
+msgstr ""
+
+#: ../../visualization.rst:78
+msgid "Play / pause automatic continuous execution"
+msgstr ""
+
+#: ../../visualization.rst:79
+msgid "``Shift+Space``"
+msgstr ""
+
+#: ../../visualization.rst:80
+msgid "Reverse playback automatic continuous execution"
+msgstr ""
+
+#: ../../visualization.rst:81
+msgid "``n``"
+msgstr ""
+
+#: ../../visualization.rst:82
+msgid "Step forward 1 instruction (+1 step)"
+msgstr ""
+
+#: ../../visualization.rst:83
+msgid "``p``"
+msgstr ""
+
+#: ../../visualization.rst:84
+msgid "Step backward 1 instruction (-1 step, Time-Travel debug)"
+msgstr ""
+
+#: ../../visualization.rst:85
+msgid "``c``"
+msgstr ""
+
+#: ../../visualization.rst:86
+msgid "Continue forward until next breakpoint or program halt"
+msgstr ""
+
+#: ../../visualization.rst:87
+msgid "``C`` (``Shift+c``)"
+msgstr ""
+
+#: ../../visualization.rst:88
+msgid "Reverse continue backward until previous breakpoint or start"
+msgstr ""
+
+#: ../../visualization.rst:89
+msgid "``b``"
+msgstr ""
+
+#: ../../visualization.rst:90
+msgid "Toggle breakpoint at current PC"
+msgstr ""
+
+#: ../../visualization.rst:91
+msgid "``+`` / ``-``"
+msgstr ""
+
+#: ../../visualization.rst:92
+msgid "Increase / decrease automatic playback execution speed"
+msgstr ""
+
+#: ../../visualization.rst:93
+msgid "``r``"
+msgstr ""
+
+#: ../../visualization.rst:94
+msgid "Reset execution back to Step 0"
+msgstr ""
+
+#: ../../visualization.rst:95
+msgid "``q``"
+msgstr ""
+
+#: ../../visualization.rst:96
+msgid "Quit Tiny8 application"
+msgstr ""
+
+#: ../../visualization.rst:99
+msgid "View & Display Controls"
+msgstr ""
+
+#: ../../visualization.rst:107
+msgid "``j`` / ``k``"
+msgstr ""
+
+#: ../../visualization.rst:108
+msgid "Scroll memory viewport down / up by 32 bytes (1 row)"
+msgstr ""
+
+#: ../../visualization.rst:109
+msgid "``J`` / ``K``"
+msgstr ""
+
+#: ../../visualization.rst:110
+msgid "Fast scroll memory viewport down / up by 128 bytes (4 rows)"
+msgstr ""
+
+#: ../../visualization.rst:111
+msgid "``g``"
+msgstr ""
+
+#: ../../visualization.rst:112
+msgid "Toggle between Viridis and Grayscale color palettes"
+msgstr ""
+
+#: ../../visualization.rst:113
+msgid "``x``"
+msgstr ""
+
+#: ../../visualization.rst:114
+msgid "Toggle between Hexadecimal digits (02X) and Graphic Pixel blocks"
+msgstr ""
+
+#: ../../visualization.rst:115
+msgid "``m``"
+msgstr ""
+
+#: ../../visualization.rst:116
+msgid "Cycle view modes (Viridis+Hex -> Viridis+Pixel -> Grayscale+Pixel -> Grayscale+Hex)"
+msgstr ""
+
+#: ../../visualization.rst:117
+msgid "``i``"
+msgstr ""
+
+#: ../../visualization.rst:118
+msgid "Inspect details of the currently executing instruction"
+msgstr ""
+
+#: ../../visualization.rst:119
+msgid "``h`` or ``?``"
+msgstr ""
+
+#: ../../visualization.rst:120
+msgid "Open full TUI Application Usage & Keyboard Guide"
+msgstr ""
+
+#: ../../visualization.rst:121
+msgid "``e``"
+msgstr ""
+
+#: ../../visualization.rst:122
+msgid "Launch the built-in full-screen Vim-style modal editor"
+msgstr ""
+
+#: ../../visualization.rst:125
+msgid "Command Bar Prompt (:)"
+msgstr ""
+
+#: ../../visualization.rst:127
+msgid "Press ``:`` anytime from the debugger to enter commands:"
+msgstr ""
+
+#: ../../visualization.rst:133
+msgid "Command"
+msgstr ""
+
+#: ../../visualization.rst:134
+msgid "Description"
+msgstr ""
+
+#: ../../visualization.rst:135
+msgid "``:goto <step>``"
+msgstr ""
+
+#: ../../visualization.rst:136
+msgid "Seek directly to an execution step (e.g., ``:goto 500``)"
+msgstr ""
+
+#: ../../visualization.rst:137
+msgid "``:b <pc> [if expr]``"
+msgstr ""
+
+#: ../../visualization.rst:138
+msgid "Set conditional breakpoint (e.g., ``:b 0x0010 if R16 > 10``)"
+msgstr ""
+
+#: ../../visualization.rst:139
+msgid "``:watch <target>``"
+msgstr ""
+
+#: ../../visualization.rst:140
+msgid "Set watchpoint on register or memory address"
+msgstr ""
+
+#: ../../visualization.rst:141
+msgid "``:set <reg> <val>``"
+msgstr ""
+
+#: ../../visualization.rst:142
+msgid "Modify register value dynamically (e.g., ``:set R16 42``)"
+msgstr ""
+
+#: ../../visualization.rst:143
+msgid "``:poke <addr> <val>``"
+msgstr ""
+
+#: ../../visualization.rst:144
+msgid "Modify RAM byte value dynamically (e.g., ``:poke 0x0200 255``)"
+msgstr ""
+
+#: ../../visualization.rst:145
+msgid "``:exec <asm>``"
+msgstr ""
+
+#: ../../visualization.rst:146
+msgid "Execute an assembly instruction immediately (e.g., ``:exec LDI R16, 5``)"
+msgstr ""
+
+#: ../../visualization.rst:147
+msgid "``:speed <ms>``"
+msgstr ""
+
+#: ../../visualization.rst:148
+msgid "Set playback speed interval in milliseconds"
+msgstr ""
+
+#: ../../visualization.rst:149
+msgid "``:m <addr>``"
+msgstr ""
+
+#: ../../visualization.rst:150
+msgid "Jump memory viewport to specified address"
+msgstr ""
+
+#: ../../visualization.rst:151
+msgid "``:q`` / ``:quit``"
+msgstr ""
+
+#: ../../visualization.rst:152
+msgid "Exit debugger"
+msgstr ""
+
+#: ../../visualization.rst:155
+msgid "Built-in Vim Modal Editor"
+msgstr ""
+
+#: ../../visualization.rst:157
+msgid "Press ``e`` anytime or pass ``--edit`` on the command line to enter the full-screen Vim editor:"
+msgstr ""
+
+#: ../../visualization.rst:159
+msgid "**NORMAL Mode**: Full cursor navigation with ``h``/``j``/``k``/``l``, word jump ``w``/``b``, line bounds ``0``/``$``, file bounds ``gg``/``G``, delete character ``x``, delete line ``dd``, copy line ``yy``, paste ``p``, undo ``u``, redo ``Ctrl+r``."
+msgstr ""
+
+#: ../../visualization.rst:160
+msgid "**INSERT Mode**: Press ``i``, ``a``, or ``o`` to write code freely. Press ``Esc`` to return to NORMAL mode."
+msgstr ""
+
+#: ../../visualization.rst:161
+msgid "**COMMAND Mode**: Press ``:`` to enter commands: * ``:w`` - Save code to file * ``:wq`` or ``:x`` - Save and return to debugger * ``:run`` - Compile/assemble code and restart debugging immediately * ``:q`` or ``:q!`` - Exit editor back to debugger"
+msgstr ""
+
+#: ../../visualization.rst:168
+msgid "Documentation Internationalization (i18n)"
+msgstr ""
+
+#: ../../visualization.rst:170
+msgid "Tiny8 documentation supports English (en) and Japanese (ja) localization via Sphinx gettext:"
+msgstr ""
diff --git a/docs/visualization.rst b/docs/visualization.rst
index 5e98858..31f76f4 100644
--- a/docs/visualization.rst
+++ b/docs/visualization.rst
@@ -1,438 +1,175 @@
-Visualization
-=============
+Visualization & Debugger
+========================
 
-Tiny8 provides two powerful visualization tools to help you understand program execution: an **interactive terminal debugger** and a **graphical animation system** for generating videos.
+Tiny8 features a modern, real-time terminal visualizer and visual debugger powered by `Textual <https://textual.textualize.io/>`_. It provides interactive execution controls, sparse checkpoint time-travel, a 32x32 TrueColor memory heatmap, and a full-screen built-in modal editor.
 
-Terminal Debugger
+Launching the TUI
 -----------------
 
-The interactive terminal debugger provides a comprehensive, real-time view of your program execution with Vim-style keyboard controls.
-
-Launching the Debugger
-~~~~~~~~~~~~~~~~~~~~~~
-
-Run any assembly program with the ``tiny8`` command:
+To run any assembly or C program with the interactive debugger:
 
 .. code-block:: bash
 
    tiny8 program.asm
+   tiny8 program.c
 
-This opens the terminal-based visualizer showing your program state.
-
-Interface Overview
-~~~~~~~~~~~~~~~~~~
-
-The debugger interface is divided into several sections:
-
-.. code-block:: text
-
-   ┌─────────────────────────────────────────────┐
-   │          SOURCE CODE (with PC)              │
-   │  Shows your assembly with current line      │
-   ├─────────────────────────────────────────────┤
-   │              REGISTERS                      │
-   │  R0-R31 with changed values highlighted     │
-   ├─────────────────────────────────────────────┤
-   │            STATUS FLAGS (SREG)              │
-   │  I T H S V N Z C - visual indicators        │
-   ├─────────────────────────────────────────────┤
-   │               MEMORY                        │
-   │  RAM contents with addresses and values     │
-   ├─────────────────────────────────────────────┤
-   │            CONTROL INFO                     │
-   │  PC, SP, Step count, Help hint              │
-   └─────────────────────────────────────────────┘
-
-Keyboard Controls
-~~~~~~~~~~~~~~~~~
-
-Navigation
-^^^^^^^^^^
-
-.. list-table::
-   :header-rows: 1
-   :widths: 30 70
-
-   * - Key
-     - Action
-   * - ``l`` or ``→``
-     - Step forward one instruction
-   * - ``h`` or ``←``
-     - Step backward one instruction
-   * - ``0``
-     - Go to first step
-   * - ``$``
-     - Go to last step
-   * - ``w``
-     - Jump forward 10 steps
-   * - ``b``
-     - Jump backward 10 steps
-   * - ``Space``
-     - Toggle play/pause mode
-   * - ``[`` / ``]``
-     - Slower/faster playback speed
-
-Auto-Play Mode
-^^^^^^^^^^^^^^
-
-Press ``Space`` to automatically advance through execution:
-
-* Program steps forward continuously
-* Use ``[`` and ``]`` to adjust playback speed (slower/faster)
-* Press ``Space`` again to pause
-* Press ``l``/``h`` to take manual control
+You can also specify options such as step limits or editor launch:
 
-Commands and Search
-^^^^^^^^^^^^^^^^^^^
+.. code-block:: bash
 
-Press ``:`` to enter command mode for advanced navigation:
+   # Launch with maximum execution steps
+   tiny8 program.asm --max-steps 1000
 
-**Command Examples:**
+   # Launch directly into the Vim editor
+   tiny8 my_code.c --edit
 
-* ``123`` - Jump to step 123
-* ``+50`` - Jump forward 50 steps  
-* ``-20`` - Jump backward 20 steps
-* ``/add`` - Search forward for "add" instruction
-* ``?ldi`` - Search backward for "ldi" instruction
-* ``@100`` - Jump to PC address 100
-* ``r10`` - Find next change to register R10
-* ``r10=42`` - Find where R10 equals 42
-* ``m100`` - Find next change to memory[100]
-* ``m100=0xFF`` - Find where memory[100] equals 0xFF
-* ``fZ`` - Find next change to flag Z
-* ``fC=1`` - Find where flag C equals 1
-* ``h`` or ``help`` - Show command help
+   # Compile C to assembly without running
+   tiny8 my_code.c --compile-only
 
-Marks and Bookmarks
-^^^^^^^^^^^^^^^^^^^
+Interface Overview
+------------------
 
-Set marks to quickly jump to important execution points:
+.. figure:: https://github.com/user-attachments/assets/bd3e88da-9bcb-4a41-bb9e-57d9d4e39bc6
+   :alt: Real-time generative reverse-diffusion synthesis (MNIST 8) at x5,000 speed in Tiny8 TUI (Viridis Palette, HEX init -> PIXEL denoising)
+   :align: center
+   :width: 100%
 
-.. list-table::
-   :header-rows: 1
-   :widths: 30 70
+   *Real-time generative reverse-diffusion synthesis (MNIST 8) executing at x5,000 speed in Tiny8 TUI (Viridis Palette: HEX init &rarr; PIXEL denoising)*
 
-   * - Key
-     - Action
-   * - ``m`` + letter
-     - Set mark at current step (e.g., ``ma``, ``mb``)
-   * - ``'`` + letter
-     - Jump to mark (e.g., ``'a``, ``'b``)
 
-Example workflow:
+The debugger interface provides real-time reactive panels:
 
-1. Step to an interesting point: ``ma`` (set mark 'a')
-2. Explore elsewhere in execution
-3. Return instantly: ``'a`` (jump to mark 'a')
+.. code-block:: text
 
-View Options
-^^^^^^^^^^^^
+   ┌──────────────────────────────────┬──────────────────────────────────┐
+   │ CODE VIEW                        │ REGISTERS (R00..R31)             │
+   │ Source listing & disassembly     │ Live values & delta highlights   │
+   │ Current PC pointer & Breakpoints ├──────────────────────────────────┤
+   │                                  │ STATUS REGISTER (SREG)           │
+   │                                  │ I  T  H  S  V  N  Z  C flags     │
+   ├──────────────────────────────────┴──────────────────────────────────┤
+   │ TABS: [Memory] [C Variables] [Call Stack]                           │
+   │ • 32x32 TrueColor Heatmap Grid (VRAM 0x0200..0x05FF)                │
+   │ • Live memory byte inspector & address scroll                       │
+   │ • Reconstructed C variable symbols and call stack frames            │
+   ├─────────────────────────────────────────────────────────────────────┤
+   │ STATUSLINE: [NORMAL] factorial.c  Step: 120/120  PC: 0x0014   h: help │
+   └─────────────────────────────────────────────────────────────────────┘
+
+Interactive Controls
+--------------------
+
+Execution & Time-Travel
+~~~~~~~~~~~~~~~~~~~~~~~
 
 .. list-table::
    :header-rows: 1
-   :widths: 30 70
+   :widths: 25 75
 
    * - Key
      - Action
+   * - ``Space``
+     - Play / pause automatic continuous execution
+   * - ``Shift+Space``
+     - Reverse playback automatic continuous execution
+   * - ``n``
+     - Step forward 1 instruction (+1 step)
+   * - ``p``
+     - Step backward 1 instruction (-1 step, Time-Travel debug)
+   * - ``c``
+     - Continue forward until next breakpoint or program halt
+   * - ``C`` (``Shift+c``)
+     - Reverse continue backward until previous breakpoint or start
+   * - ``b``
+     - Toggle breakpoint at current PC
+   * - ``+`` / ``-``
+     - Increase / decrease automatic playback execution speed
    * - ``r``
-     - Toggle between changed/all registers view
-   * - ``M``
-     - Toggle between non-zero/all memory view
-   * - ``j``
-     - Scroll memory view down
-   * - ``k``
-     - Scroll memory view up
-   * - ``=``
-     - Show detailed step information
-
-Other Controls
-^^^^^^^^^^^^^^
+     - Reset execution back to Step 0
+   * - ``q``
+     - Quit Tiny8 application
+
+View & Display Controls
+~~~~~~~~~~~~~~~~~~~~~~~
 
 .. list-table::
    :header-rows: 1
-   :widths: 30 70
+   :widths: 25 75
 
    * - Key
      - Action
-   * - ``/``
-     - Show help screen
-   * - ``q`` or ``Esc``
-     - Quit debugger
-
-Visual Indicators
-~~~~~~~~~~~~~~~~~
-
-Change Highlighting
-^^^^^^^^^^^^^^^^^^^
-
-The debugger highlights changes at each step:
-
-* **Registers**: Changed values appear in a different color
-* **Flags**: Set flags are highlighted
-* **Memory**: Modified memory cells are marked
-* **PC indicator**: Shows current instruction with ``►`` or color
-
-Understanding the Display
-^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-**Registers Display**
-
-.. code-block:: text
-
-   R0:  000  R1:  000  R2:  000  R3:  000
-   R16: 042  R17: 010  R18: 005  R19: 000
-        ^^^       ^^^  (highlighted if changed)
-
-**Status Flags (SREG)**
-
-.. code-block:: text
-
-   SREG: [I:0] [T:0] [H:0] [S:0] [V:0] [N:0] [Z:1] [C:0]
-                                             ^^^
-                                             (set flags highlighted)
-
-**Memory Display**
-
-.. code-block:: text
-
-   0x0200: 42  ← Changed this step
-   0x0201: 00
-   0x0202: FF  ← Changed this step
-
-Tips and Tricks
-~~~~~~~~~~~~~~~
-
-Debugging Workflow
-^^^^^^^^^^^^^^^^^^
-
-1. **Set marks at key points**: Before loops, after calculations
-2. **Use search**: Find where registers or memory addresses are accessed
-3. **Toggle views**: Show only changed registers when debugging large programs
-4. **Auto-play**: Watch algorithm execution in real-time
-
-Finding Issues
-^^^^^^^^^^^^^^
-
-* **Infinite loops**: Watch step counter; if PC stops changing, you're stuck
-* **Wrong results**: Step through and watch registers; mark where values diverge
-* **Memory issues**: Search for memory addresses; check reads/writes
-* **Flag problems**: Watch SREG; verify flags after comparisons
-
-Graphical Animation
--------------------
-
-Generate high-quality GIF or MP4 videos showing program execution with register and memory evolution.
-
-Basic Animation
-~~~~~~~~~~~~~~~
-
-Create an animation from your program:
-
-.. code-block:: bash
-
-   tiny8 program.asm -m ani -o output.gif
-
-This generates ``output.gif`` showing:
-
-* SREG flag evolution over time
-* All 32 registers as a heatmap
-* Memory contents in a specified range
-
-Advanced Options
-~~~~~~~~~~~~~~~~
-
-Command-Line Arguments
-^^^^^^^^^^^^^^^^^^^^^^
-
-.. code-block:: bash
+   * - ``j`` / ``k``
+     - Scroll memory viewport down / up by 32 bytes (1 row)
+   * - ``J`` / ``K``
+     - Fast scroll memory viewport down / up by 128 bytes (4 rows)
+   * - ``g``
+     - Toggle between Viridis and Grayscale color palettes
+   * - ``x``
+     - Toggle between Hexadecimal digits (02X) and Graphic Pixel blocks
+   * - ``m``
+     - Cycle view modes (Viridis+Hex -> Viridis+Pixel -> Grayscale+Pixel -> Grayscale+Hex)
+   * - ``i``
+     - Inspect details of the currently executing instruction
+   * - ``h`` or ``?``
+     - Open full TUI Application Usage & Keyboard Guide
+   * - ``e``
+     - Launch the built-in full-screen Vim-style modal editor
+
+Command Bar Prompt (:)
+~~~~~~~~~~~~~~~~~~~~~~
 
-   tiny8 program.asm -m ani \
-       --output animation.gif \
-       --mem-start 0x0200 \
-       --mem-end 0x02FF \
-       --interval 200 \
-       --fps 30
+Press ``:`` anytime from the debugger to enter commands:
 
 .. list-table::
    :header-rows: 1
    :widths: 30 70
 
-   * - Option
+   * - Command
      - Description
-   * - ``-m ani``
-     - Enable animation mode
-   * - ``-o FILE``
-     - Output filename (.gif or .mp4)
-   * - ``--mem-start ADDR``
-     - Start address for memory visualization
-   * - ``--mem-end ADDR``
-     - End address for memory visualization
-   * - ``--interval MS``
-     - Milliseconds per frame
-   * - ``--fps N``
-     - Frames per second (for video)
-
-Animation Layout
-~~~~~~~~~~~~~~~~
-
-The generated animation has three panels:
-
-**Top Panel: SREG Flags**
-  8 rows showing each flag (I, T, H, S, V, N, Z, C) over time
-  * Bright = flag set (1)
-  * Dark = flag clear (0)
-
-**Middle Panel: Registers**
-  32 rows (R0-R31) showing register values over time
-  * Color intensity = value (0-255)
-  * Bright = high values
-  * Dark = low values
-
-**Bottom Panel: Memory**
-  Selected memory range showing contents over time
-  * Same color scheme as registers
-  * Track data structure evolution
-
-Reading the Animation
-~~~~~~~~~~~~~~~~~~~~~
-
-**Time Axis (Horizontal)**
-  Each column represents one execution step
-  * Left side: Program start
-  * Right side: Program end
-  * Watch values change across time
-
-**Value Axis (Vertical)**
-  Each row is a register or memory location
-  * Track individual items vertically
-  * See patterns and data flow
-
-Example Use Cases
-~~~~~~~~~~~~~~~~~
-
-Visualizing Algorithms
-^^^^^^^^^^^^^^^^^^^^^^
-
-.. code-block:: bash
-
-   # Visualize bubble sort
-   tiny8 examples/bubblesort.asm -m ani -o bubblesort.gif
-
-Watch the sorting algorithm:
-
-* Registers holding array indices
-* Memory showing array elements being swapped
-* Flags changing during comparisons
-
-Debugging Data Flow
-^^^^^^^^^^^^^^^^^^^
+   * - ``:goto <step>``
+     - Seek directly to an execution step (e.g., ``:goto 500``)
+   * - ``:b <pc> [if expr]``
+     - Set conditional breakpoint (e.g., ``:b 0x0010 if R16 > 10``)
+   * - ``:watch <target>``
+     - Set watchpoint on register or memory address
+   * - ``:set <reg> <val>``
+     - Modify register value dynamically (e.g., ``:set R16 42``)
+   * - ``:poke <addr> <val>``
+     - Modify RAM byte value dynamically (e.g., ``:poke 0x0200 255``)
+   * - ``:exec <asm>``
+     - Execute an assembly instruction immediately (e.g., ``:exec LDI R16, 5``)
+   * - ``:speed <ms>``
+     - Set playback speed interval in milliseconds
+   * - ``:m <addr>``
+     - Jump memory viewport to specified address
+   * - ``:q`` / ``:quit``
+     - Exit debugger
+
+Built-in Vim Modal Editor
+-------------------------
+
+Press ``e`` anytime or pass ``--edit`` on the command line to enter the full-screen Vim editor:
+
+* **NORMAL Mode**: Full cursor navigation with ``h``/``j``/``k``/``l``, word jump ``w``/``b``, line bounds ``0``/``$``, file bounds ``gg``/``G``, delete character ``x``, delete line ``dd``, copy line ``yy``, paste ``p``, undo ``u``, redo ``Ctrl+r``.
+* **INSERT Mode**: Press ``i``, ``a``, or ``o`` to write code freely. Press ``Esc`` to return to NORMAL mode.
+* **COMMAND Mode**: Press ``:`` to enter commands:
+  * ``:w`` - Save code to file
+  * ``:wq`` or ``:x`` - Save and return to debugger
+  * ``:run`` - Compile/assemble code and restart debugging immediately
+  * ``:q`` or ``:q!`` - Exit editor back to debugger
+
+Documentation Internationalization (i18n)
+-----------------------------------------
+
+Tiny8 documentation supports English (en) and Japanese (ja) localization via Sphinx gettext:
 
 .. code-block:: bash
 
-   # Track Fibonacci sequence generation
-   tiny8 examples/fibonacci.asm -m ani -o fib.gif
-
-Observe:
-
-* R16 and R17 alternating as Fibonacci numbers grow
-* Loop counter (R18) decrementing
-* Flag changes at each iteration
-
-Presentations and Education
-^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-Animations are perfect for:
-
-* Teaching computer architecture concepts
-* Explaining algorithms visually
-* Documenting program behavior
-* Creating engaging educational content
-
-Python API for Visualization
------------------------------
-
-You can also create visualizations programmatically using the Python API.
-
-Using the Visualizer Class
-~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-.. code-block:: python
-
-   from tiny8 import CPU, assemble, Visualizer
-   
-   # Create and run program
-   code = """
-       ldi r16, 0
-       ldi r17, 10
-   loop:
-       add r16, r17
-       dec r17
-       brne loop
-   """
-   
-   asm = assemble(code)
-   cpu = CPU()
-   cpu.load_program(asm)
-   cpu.run(max_steps=100)
-   
-   # Create visualization
-   viz = Visualizer(cpu)
-   viz.animate_execution(
-       mem_addr_start=0x0200,
-       mem_addr_end=0x02FF,
-       filename="my_animation.gif",
-       interval=200,  # ms between frames
-       fps=30,
-       cmap="viridis"  # matplotlib colormap
-   )
-
-Customization Options
-~~~~~~~~~~~~~~~~~~~~~
-
-The ``animate_execution`` method accepts several parameters:
-
-.. code-block:: python
-
-   viz.animate_execution(
-       mem_addr_start=0x60,      # Start of memory range
-       mem_addr_end=0x7F,        # End of memory range
-       filename="output.gif",    # Output file
-       interval=200,              # Frame interval (ms)
-       fps=30,                   # Frames per second
-       fontsize=9,               # Label font size
-       cmap="inferno",           # Color map name
-       plot_every=1              # Downsample: plot every N steps
-   )
-
-Available colormaps: ``viridis``, ``plasma``, ``inferno``, ``magma``, ``cividis``, ``cool``, ``hot``, and many more from Matplotlib.
-
-Visualization Best Practices
------------------------------
-
-For Terminal Debugging
-~~~~~~~~~~~~~~~~~~~~~~
-
-1. **Start simple**: Run through once to understand program flow
-2. **Mark key points**: Set marks at loop starts, branches, important calculations
-3. **Use search**: Find where specific registers/memory are modified
-4. **Toggle views**: Hide unchanged registers for clarity in large programs
-5. **Auto-play for overview**: Watch execution flow at high level
-
-For Animations
-~~~~~~~~~~~~~~
-
-1. **Choose memory range carefully**: Show only relevant data
-2. **Adjust frame rate**: Slower for detailed analysis, faster for overview
-3. **Pick good colormaps**: High contrast for presentations, perceptually uniform for analysis
-4. **Downsample long programs**: Use ``plot_every`` to skip steps
-5. **Combine with comments**: Explain what viewers should watch for
-
-Performance Tips
-~~~~~~~~~~~~~~~~
+   # Build Japanese HTML documentation
+   make -C docs html-ja
 
-For very long-running programs:
+   # Build English HTML documentation
+   make -C docs html-en
 
-* Use ``max_steps`` parameter to limit execution
-* Enable ``plot_every`` downsampling for animations
-* Focus memory range on active data regions
-* Consider using the CLI debugger instead of generating full animation
+   # Build all languages
+   make -C docs html-all
diff --git a/examples/bubblesort.asm b/examples/bubblesort.asm
index 0aba750..3da2278 100644
--- a/examples/bubblesort.asm
+++ b/examples/bubblesort.asm
@@ -11,6 +11,7 @@
 init_loop:
     ; Generate random byte: seed = (seed * 75) + 1
     mul r18, r25
+    mov r18, r0
     inc r18
     
     st r16, r18       ; Store random value
@@ -39,9 +40,10 @@ inner_loop:
     add r22, r23
     ld r24, r22       ; r24 = B
     
-    ; Swap if A > B (ascending order)
+    ; Swap if A > B (ascending order: smallest first)
     cp r21, r24
     brcs no_swap      ; Skip if A < B
+    breq no_swap      ; Skip if A == B
     st r20, r24       ; RAM[addr_A] = B
     st r22, r21       ; RAM[addr_B] = A
 
diff --git a/examples/count_bits.asm b/examples/count_bits.asm
index 59fc4cc..f3959c1 100644
--- a/examples/count_bits.asm
+++ b/examples/count_bits.asm
@@ -20,9 +20,8 @@ loop:
     inc r16
 
 no_inc:
-    ; shift right (divide by 2)
-    ldi r20, 2
-    div r18, r20
+    ; shift right (logical shift right by 1 bit)
+    lsr r18
     
     jmp loop
 
diff --git a/examples/diffusion_mnist8.asm b/examples/diffusion_mnist8.asm
new file mode 100644
index 0000000..62a1877
--- /dev/null
+++ b/examples/diffusion_mnist8.asm
@@ -0,0 +1,61995 @@
+; ==================================================================
+; TINY8 NATIVE 28x28 DIFFUSION MODEL FOR MNIST DIGIT 8
+; Trained on torchvision.datasets.MNIST (8 reverse steps)
+; Direct 32x32 Heatmap VRAM: 0x0200..0x05FF (1024 bytes)
+; Progressive Denoising Trajectory: t = 8 -> 7 -> ... -> 0
+; ==================================================================
+
+; Memory Map in RAM (0x0000..0xFFFF, 64KB total):
+;   0x0060..0x006B: hidden (12 bytes, activations 0..127)
+;   0x0070..0x007F: temps (step_t, counters)
+;   0x0200..0x05FF: 32x32 VRAM (1024 bytes heatmap monitor)
+;   0x0600..0x090F: img (784 bytes, 28x28 pixel intensity 0..255)
+;   0x0A00..0x2EBF: w_enc (12 x 784 = 9408 bytes, signed int8)
+;   0x2EC0..0x2F1F: t_embed (8 x 12 = 96 bytes, signed int8)
+;   0x2F20..0x53DF: w_dec (784 x 12 = 9408 bytes, signed int8)
+;   0x53E0..0x59FF: b_dec (784 x 2 = 1568 bytes, signed int16)
+;   0x5D20..0x5D2F: c1, c2 blend coefficients (8 + 8 bytes)
+
+.data_init:
+; Initialize w_enc at 0x0A00 (9408 bytes)
+    LDI R30, 0
+    LDI R31, 10
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
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+    ADIW R30, 1
+    LDI R16, 253
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+    ADIW R30, 1
+    LDI R16, 254
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 254
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+    ADIW R30, 1
+    LDI R16, 255
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+    ADIW R30, 1
+    LDI R16, 255
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+    ADIW R30, 1
+    LDI R16, 254
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 254
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+    ADIW R30, 1
+    LDI R16, 254
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+    ADIW R30, 1
+    LDI R16, 253
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 2
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 2
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 2
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 3
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 2
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 3
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 2
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 2
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    LDI R31, 0
+
+; Initialize t_embed at 0x2EC0 (96 bytes)
+    LDI R30, 192
+    LDI R31, 46
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 246
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 5
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 241
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 2
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 4
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 13
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 249
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 251
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 9
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 2
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 7
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 4
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 1
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 18
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 9
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 14
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 6
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 2
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 13
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 5
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 248
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 6
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 243
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 35
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 6
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 9
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 250
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 25
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 23
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 16
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 17
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 11
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 24
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 16
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 20
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 43
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 30
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 32
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 18
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 59
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 63
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 78
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 67
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 27
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 77
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 50
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 67
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 67
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 59
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 71
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 23
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 57
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 100
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 127
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 96
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 127
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 127
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 68
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 127
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 81
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 127
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 127
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 76
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 84
+    ST R30, R16
+    LDI R31, 0
+
+; Initialize w_dec at 0x2F20 (9408 bytes)
+    LDI R30, 32
+    LDI R31, 47
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 251
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 253
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 254
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 254
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
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+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
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+    ADIW R30, 1
+    LDI R16, 252
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+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
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+    ADIW R30, 1
+    LDI R16, 252
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+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
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+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
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+    ADIW R30, 1
+    LDI R16, 252
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+    ADIW R30, 1
+    LDI R16, 254
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+    ADIW R30, 1
+    LDI R16, 252
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 254
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+    ADIW R30, 1
+    LDI R16, 252
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 254
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
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+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
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+    ADIW R30, 1
+    LDI R16, 253
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 254
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+    ADIW R30, 1
+    LDI R16, 252
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 252
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 254
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 254
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 254
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 254
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 254
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
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+    ADIW R30, 1
+    LDI R16, 252
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 253
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+    ADIW R30, 1
+    LDI R16, 255
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+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 255
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+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
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+    ADIW R30, 1
+    LDI R16, 254
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+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
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+    ADIW R30, 1
+    LDI R16, 254
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 250
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 254
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 250
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+    ADIW R30, 1
+    LDI R16, 254
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+    ADIW R30, 1
+    LDI R16, 255
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 254
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+    ADIW R30, 1
+    LDI R16, 255
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+    ADIW R30, 1
+    LDI R16, 254
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 254
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 255
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+    ADIW R30, 1
+    LDI R16, 251
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 248
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+    LDI R16, 252
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 244
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 2
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+    ADIW R30, 1
+    LDI R16, 255
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+    ADIW R30, 1
+    LDI R16, 0
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 255
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+    ADIW R30, 1
+    LDI R16, 242
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 243
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 245
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+    ADIW R30, 1
+    LDI R16, 254
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 254
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+    ADIW R30, 1
+    LDI R16, 254
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+    ADIW R30, 1
+    LDI R16, 248
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+    ADIW R30, 1
+    LDI R16, 254
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+    ADIW R30, 1
+    LDI R16, 253
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 253
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+    ADIW R30, 1
+    LDI R16, 251
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+    ADIW R30, 1
+    LDI R16, 253
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    LDI R16, 254
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+    ST R30, R16
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+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 253
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 252
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 254
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 254
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+    ADIW R30, 1
+    LDI R16, 252
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 253
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 254
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 251
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 252
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 253
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 254
+    ST R30, R16
+    LDI R31, 0
+
+; Initialize b_dec at 0x53E0 (1568 bytes)
+    LDI R30, 224
+    LDI R31, 83
+    LDI R16, 110
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 112
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 34
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 114
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 124
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 108
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 120
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 119
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 114
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 93
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 114
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 123
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 92
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 108
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
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+    LDI R16, 120
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+    ADIW R30, 1
+    LDI R16, 255
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+    ADIW R30, 1
+    LDI R16, 119
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+    ADIW R30, 1
+    LDI R16, 255
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+    ADIW R30, 1
+    LDI R16, 101
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+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 117
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+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 109
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+    ADIW R30, 1
+    LDI R16, 255
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+    ADIW R30, 1
+    LDI R16, 112
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 113
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 121
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 112
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ST R30, R16
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+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 142
+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
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+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 172
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 203
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 234
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    LDI R16, 244
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    LDI R16, 255
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+    ADIW R30, 1
+    LDI R16, 11
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 237
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 233
+    ST R30, R16
+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 228
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 202
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 208
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 226
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 177
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
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+    ADIW R30, 1
+    LDI R16, 127
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 122
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 123
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 136
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 107
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 121
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 154
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 169
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 202
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 202
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 211
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 219
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 223
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 228
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 231
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 225
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 217
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 196
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 178
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 165
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 135
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 126
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 116
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 105
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 74
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 128
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 115
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 110
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 110
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 110
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 118
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 70
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 120
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 104
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 126
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 124
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 151
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 145
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 152
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 152
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 140
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 154
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 174
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 113
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 118
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 143
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 117
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 136
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 121
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 117
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 131
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 109
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 111
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 109
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 117
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 88
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 133
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 121
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 109
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 130
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 122
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 123
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 120
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 120
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 120
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 127
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 119
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 128
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 127
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 114
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 117
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 131
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 115
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 113
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 117
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 114
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 125
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 125
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 110
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 116
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 121
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 119
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 125
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 108
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 109
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 126
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 128
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 119
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 125
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 94
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 122
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 124
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 124
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 119
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 120
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 89
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 133
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 117
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 128
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 121
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 117
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 124
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 127
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 115
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 120
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 119
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 83
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 122
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 105
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 120
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 107
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 118
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 255
+    ST R30, R16
+    LDI R31, 0
+
+; Blend coefficients (c1: 8 bytes, c2: 8 bytes at 0x5D20)
+    LDI R30, 0x20
+    LDI R31, 0x5D
+    LDI R16, 16
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 10
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 7
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 6
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 5
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 4
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 4
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 3
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 0
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 6
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 9
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 10
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 11
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 12
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 12
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 13
+    ST R30, R16
+    ADIW R30, 1
+    LDI R31, 0
+
+main:
+    ; Generate initial pseudo-Gaussian noise (step 8) into img buffer (0x0600)
+    ; 784 bytes = 4 outer * 196 inner, using 16-bit Galois LFSR + 2-byte average
+    LDI R26, 0x00      ; X = &img[0] (0x0600)
+    LDI R27, 0x06
+    LDI R24, 0xE1      ; 16-bit LFSR seed low byte (0xACE1)
+    LDI R25, 0xAC      ; 16-bit LFSR seed high byte
+    LDI R18, 0xB4      ; LFSR polynomial tap mask
+    LDI R22, 4
+gen_noise_outer:
+    LDI R23, 196
+gen_noise_inner:
+    LSR R25
+    ROR R24
+    BRCC no_xor
+    EOR R25, R18
+no_xor:
+    MOV R20, R24
+    ADD R20, R25
+    ROR R20            ; average two uniform bytes -> bell-shaped 0..255
+    ST X, R20
+    ADIW R26, 1
+    DEC R23
+    BRNE gen_noise_inner
+    DEC R22
+    BRNE gen_noise_outer
+
+    ; Render Initial Step 8 (Pure Noise)
+    LDI R16, 8
+    STS 0x0070, R16    ; cur_step = 8
+    RCALL render_vram
+
+    ; Denoising Loop: t = 7 down to 0
+    LDI R19, 7         ; R19 = current step t
+diffusion_step_loop:
+    STS 0x0070, R19    ; save step t
+
+    ; ----------------------------------------------------------------
+    ; Stage 1: Encoder - Compute 12 Hidden Activations
+    ; h_k = ReLU( ((t_embed[t, k] << 4) + sum(w_enc[k, j] * img[j])) >> 5 )
+    ; ----------------------------------------------------------------
+    LDI R22, 0         ; k = 0
+node_loop:
+    ; Load t_embed[t, k] from 0x2EC0 + t * 12 + k
+    LDS R16, 0x0070    ; R16 = t
+    LDI R17, 12
+    MUL R16, R17       ; R1:R0 = t * 12
+    ADD R0, R22        ; + k
+    LDI R30, 0xC0
+    LDI R31, 0x2E
+    ADD R30, R0
+    ADC R31, R1
+    LD R24, Z          ; R24 = t_embed[t, k] (signed 8-bit)
+    LDI R25, 0
+    SBRC R24, 7
+    LDI R25, 255       ; sign extend
+
+    ; Shift left 4: R25:R24 << 4
+    LDI R18, 4
+t_shl_loop:
+    LSL R24
+    ROL R25
+    DEC R18
+    BRNE t_shl_loop
+
+    ; Base address for w_enc[k]: 0x0A00 + k * 784
+    ; 784 = 256 * 3 + 16 (0x0310)
+    LDI R16, 16
+    MUL R22, R16       ; R1:R0 = k * 16
+    MOV R20, R0
+    MOV R21, R1
+    LDI R16, 3
+    MUL R22, R16       ; R1:R0 = k * 3
+    ADD R21, R0        ; R21:R20 = k * 784
+    LDI R30, 0x00
+    LDI R31, 0x0A
+    ADD R30, R20
+    ADC R31, R21       ; Z = &w_enc[k, 0]
+
+    ; X = &img[0] (0x0600)
+    LDI R26, 0x00
+    LDI R27, 0x06
+
+    ; 784 MAC operations: 28 outer * 28 inner
+    LDI R18, 28
+enc_mac_outer:
+    LDI R19, 28
+enc_mac_inner:
+    LD R16, Z          ; R16 = w_enc[k, j] (signed)
+    LD R17, X          ; R17 = img[j] (unsigned)
+    MULSU R16, R17     ; R1:R0 = w_enc * img (signed 16-bit)
+    ADD R24, R0
+    ADC R25, R1
+    ADIW R30, 1
+    ADIW R26, 1
+    DEC R19
+    BRNE enc_mac_inner
+    DEC R18
+    BRNE enc_mac_outer
+
+    ; Shift right 5 arithmetic: (R25:R24) >> 5
+    LDI R18, 5
+enc_shr_loop:
+    ASR R25
+    ROR R24
+    DEC R18
+    BRNE enc_shr_loop
+
+    ; ReLU: if sum < 0 then 0, clamp max 127
+    SBRC R25, 7
+    RJMP relu_zero
+    CPI R25, 0
+    BRNE relu_clamp_max
+    CPI R24, 127
+    BRCS relu_ok
+relu_clamp_max:
+    LDI R24, 127
+    RJMP relu_ok
+relu_zero:
+    LDI R24, 0
+relu_ok:
+    ; Store into hidden[k] (at 0x0060 + k)
+    LDI R30, 0x60
+    LDI R31, 0x00
+    ADD R30, R22
+    ST R30, R24
+
+    INC R22            ; k++
+    CPI R22, 12
+    BRNE node_loop
+
+    ; Cache hidden activations into R2..R13 for high-throughput unrolled decoding
+    LDS R2, 0x0060
+    LDS R3, 0x0061
+    LDS R4, 0x0062
+    LDS R5, 0x0063
+    LDS R6, 0x0064
+    LDS R7, 0x0065
+    LDS R8, 0x0066
+    LDS R9, 0x0067
+    LDS R10, 0x0068
+    LDS R11, 0x0069
+    LDS R12, 0x006A
+    LDS R13, 0x006B
+
+    ; ----------------------------------------------------------------
+    ; Stage 2: Decoder & Blend - Reconstruct and Update img (784 pixels)
+    ; Sequential pointers: Y=&b_dec, Z=&w_dec, X=&img
+    ; ----------------------------------------------------------------
+    LDS R19, 0x0070    ; restore t
+    ; Load c1 from 0x5D20 + t, c2 from 0x5D28 + t
+    LDI R30, 0x20
+    LDI R31, 0x5D
+    ADD R30, R19
+    LD R14, Z          ; R14 = c1
+    LDI R30, 0x28
+    LDI R31, 0x5D
+    ADD R30, R19
+    LD R15, Z          ; R15 = c2
+
+    ; Pointers for sequential pass:
+    ; Y = &b_dec[0] (0x53E0)
+    ; Z = &w_dec[0, 0] (0x2F20)
+    ; X = &img[0] (0x0600)
+    LDI R28, 0xE0
+    LDI R29, 0x53
+    LDI R30, 0x20
+    LDI R31, 0x2F
+    LDI R26, 0x00
+    LDI R27, 0x06
+
+    ; 784 pixels: 28 outer * 28 inner
+    LDI R22, 28        ; outer loop counter
+pixel_dec_outer:
+    LDI R23, 28        ; inner loop counter
+pixel_dec_inner:
+    ; Load 16-bit b_dec from Y
+    LD R24, Y
+    ADIW R28, 1
+    LD R25, Y
+    ADIW R28, 1
+
+    ; Unrolled 12-term MAC directly against cached hidden registers R2..R13
+    LD R16, Z
+    ADIW R30, 1
+    MULS R16, R2
+    ADD R24, R0
+    ADC R25, R1
+
+    LD R16, Z
+    ADIW R30, 1
+    MULS R16, R3
+    ADD R24, R0
+    ADC R25, R1
+
+    LD R16, Z
+    ADIW R30, 1
+    MULS R16, R4
+    ADD R24, R0
+    ADC R25, R1
+
+    LD R16, Z
+    ADIW R30, 1
+    MULS R16, R5
+    ADD R24, R0
+    ADC R25, R1
+
+    LD R16, Z
+    ADIW R30, 1
+    MULS R16, R6
+    ADD R24, R0
+    ADC R25, R1
+
+    LD R16, Z
+    ADIW R30, 1
+    MULS R16, R7
+    ADD R24, R0
+    ADC R25, R1
+
+    LD R16, Z
+    ADIW R30, 1
+    MULS R16, R8
+    ADD R24, R0
+    ADC R25, R1
+
+    LD R16, Z
+    ADIW R30, 1
+    MULS R16, R9
+    ADD R24, R0
+    ADC R25, R1
+
+    LD R16, Z
+    ADIW R30, 1
+    MULS R16, R10
+    ADD R24, R0
+    ADC R25, R1
+
+    LD R16, Z
+    ADIW R30, 1
+    MULS R16, R11
+    ADD R24, R0
+    ADC R25, R1
+
+    LD R16, Z
+    ADIW R30, 1
+    MULS R16, R12
+    ADD R24, R0
+    ADC R25, R1
+
+    LD R16, Z
+    ADIW R30, 1
+    MULS R16, R13
+    ADD R24, R0
+    ADC R25, R1
+
+    ; Piecewise Linear Sigmoid: R25:R24 = (R25:R24) >> 2 + 128
+    ASR R25
+    ROR R24
+    ASR R25
+    ROR R24
+    LDI R16, 128
+    ADD R24, R16
+    LDI R16, 0
+    ADC R25, R16
+
+    ; Clamp to [0, 255] in R16
+    SBRS R25, 7        ; if negative sign bit set -> clamp to 0
+    RJMP check_pos_clamp
+    LDI R16, 0
+    RJMP clamp_done
+check_pos_clamp:
+    CPI R25, 0
+    BREQ clamp_ok
+    LDI R16, 255       ; clamp high
+    RJMP clamp_done
+clamp_ok:
+    MOV R16, R24       ; x0_hat[i] is in R16
+clamp_done:
+
+    ; Blend: res = (c1 * R16 + c2 * img[i]) / 16
+    MUL R16, R14       ; c1 * x0_hat
+    MOV R20, R0
+    MOV R21, R1
+
+    LD R16, X          ; R16 = old img[i]
+    MUL R16, R15       ; c2 * img[i]
+    ADD R20, R0
+    ADC R21, R1
+
+    ; Divide by 16: shift right 4
+    LSR R21
+    ROR R20
+    LSR R21
+    ROR R20
+    LSR R21
+    ROR R20
+    LSR R21
+    ROR R20
+
+    ; Store into img[i] and advance X
+    ST X, R20
+    ADIW R26, 1
+
+    DEC R23
+    BRNE pixel_dec_inner
+    DEC R22
+    BRNE pixel_dec_outer
+
+    ; Render current step to VRAM
+    RCALL render_vram
+
+    LDS R19, 0x0070    ; restore step t
+    DEC R19
+    CPI R19, 255       ; checks underflow below 0
+    BREQ diffusion_done
+    RJMP diffusion_step_loop
+
+diffusion_done:
+    ; Infinite halt display loop
+halt_loop:
+    RJMP halt_loop
+
+; ==================================================================
+; SUBROUTINE: render_vram
+; 1:1 Direct copy of 28x28 img (0x0600) into 32x32 VRAM (0x0200)
+; Center region: rows 2..29, cols 2..29
+; Also writes Header row 0 and Footer row 31
+; ==================================================================
+render_vram:
+    ; Clear Row 0
+    LDI R30, 0x00
+    LDI R31, 0x02
+    LDI R16, 32        ; ' '
+    LDI R18, 32
+clr_hdr_loop:
+    ST R30, R16
+    ADIW R30, 1
+    DEC R18
+    BRNE clr_hdr_loop
+
+    ; Write Header Text at 0x0201: 'DIFFUSION MNIST:8'
+    LDI R30, 0x01
+    LDI R31, 0x02
+    LDI R16, 68 ; 'D'
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 73 ; 'I'
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 70 ; 'F'
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 70 ; 'F'
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 85 ; 'U'
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 83 ; 'S'
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 73 ; 'I'
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 79 ; 'O'
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 78 ; 'N'
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 32 ; ' '
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 77 ; 'M'
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 78 ; 'N'
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 73 ; 'I'
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 83 ; 'S'
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 84 ; 'T'
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 58 ; ':'
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 56 ; '8'
+    ST R30, R16
+    ADIW R30, 1
+
+    ; Step indicator: 'STEP:[' t ']' at 0x0216
+    LDI R30, 0x16
+    LDI R31, 0x02
+    LDI R16, 83 ; 'S'
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 84 ; 'T'
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 69 ; 'E'
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 80 ; 'P'
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 58 ; ':'
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 91 ; '['
+    ST R30, R16
+    ADIW R30, 1
+    LDS R16, 0x0070    ; step t
+    LDI R17, 48        ; '0'
+    ADD R16, R17       ; ASCII digit
+    ST R30, R16
+    ADIW R30, 1
+    LDI R16, 93 ; ']'
+    ST R30, R16
+
+    ; Direct 1:1 copy of 28x28 img into centered 28x28 VRAM (rows 2..29, cols 2..29)
+    ; X = &img[0] (0x0600)
+    LDI R26, 0x00
+    LDI R27, 0x06
+    LDI R22, 0         ; r = 0..27
+render_r_loop:
+    ; VRAM row = 2 + r, col = 2
+    ; VRAM row start: 0x0200 + (r + 2) * 32 + 2
+    LDI R16, 2
+    ADD R16, R22       ; R16 = r + 2
+    LDI R17, 32
+    MUL R16, R17       ; R1:R0 = (r + 2) * 32
+    LDI R30, 0x02      ; col offset 2
+    LDI R31, 0x02      ; base 0x0200
+    ADD R30, R0
+    ADC R31, R1        ; Z = &VRAM[r + 2, 2]
+
+    LDI R23, 28        ; 28 columns
+render_c_loop:
+    LD R16, X
+    ST R30, R16
+    ADIW R26, 1
+    ADIW R30, 1
+    DEC R23
+    BRNE render_c_loop
+
+    INC R22
+    CPI R22, 28
+    BRNE render_r_loop
+
+    ; Clear Footer row 31 (0x05E0..0x05FF)
+    LDI R30, 0xE0
+    LDI R31, 0x05
+    LDI R16, 32
+    LDI R18, 32
+clr_ftr_loop:
+    ST R30, R16
+    ADIW R30, 1
+    DEC R18
+    BRNE clr_ftr_loop
+
+    RET
+
diff --git a/examples/factorial.asm b/examples/factorial.asm
index 7ba28af..7f0c279 100644
--- a/examples/factorial.asm
+++ b/examples/factorial.asm
@@ -2,22 +2,23 @@
 ; Output: R16 = 120
 
 start:
-    ldi r17, 5        ; n = 5
+    ldi r18, 5        ; n = 5
     ldi r16, 1        ; result = 1
     
     ; if n <= 1, done
-    cpi r17, 2
+    cpi r18, 2
     brlt done
 
 loop:
-    ; result *= n
-    mul r16, r17
+    ; result *= n (stores product in R1:R0 per AVR specification)
+    mul r16, r18
+    mov r16, r0
     
     ; n--
-    dec r17
+    dec r18
     
     ; continue if n > 1
-    cpi r17, 2
+    cpi r18, 2
     brge loop
 
 done:
diff --git a/examples/factorial.c b/examples/factorial.c
new file mode 100644
index 0000000..cf2611f
--- /dev/null
+++ b/examples/factorial.c
@@ -0,0 +1,13 @@
+// Compute factorial in Tiny C
+int factorial(int n) {
+    if (n <= 1) {
+        return 1;
+    }
+    return n * factorial(n - 1);
+}
+
+int main() {
+    int res = factorial(5);
+    poke(0x80, res); // 5! = 120
+    return 0;
+}
diff --git a/examples/gcd.asm b/examples/gcd.asm
index c0a5a63..4d8e9fd 100644
--- a/examples/gcd.asm
+++ b/examples/gcd.asm
@@ -4,25 +4,18 @@
 
 start:
     ldi r16, 48       ; a = 48
-    ldi r17, 18       ; b = 18
-    
-    cpi r17, 0
-    breq done
+    ldi r18, 18       ; b = 18
 
 loop:
-    ; Compute remainder: a % b
-    mov r18, r16      ; Save a
-    div r16, r17      ; a / b
-    mul r16, r17      ; (a / b) * b
-    mov r19, r18
-    sub r19, r16      ; remainder = a - (a/b)*b
-    
-    ; Shift: a = b, b = remainder
-    mov r16, r17
-    mov r17, r19
-    
-    cpi r17, 0
-    brne loop
+    cp r16, r18       ; compare a and b
+    breq done         ; if a == b, gcd found in R16
+    brlt less         ; if a < b, branch
+    sub r16, r18      ; a = a - b
+    jmp loop
+
+less:
+    sub r18, r16      ; b = b - a
+    jmp loop
 
 done:
     jmp done
diff --git a/examples/is_prime.asm b/examples/is_prime.asm
index bc36f07..670adff 100644
--- a/examples/is_prime.asm
+++ b/examples/is_prime.asm
@@ -14,30 +14,35 @@ start:
     cpi r17, 2
     breq is_prime
     
-    ; test divisibility: check divisors from 2 to n/2
-    ldi r18, 2        ; divisor = 2 (start with smallest prime)
+    ; test divisibility: check divisors from 2 upwards
+    ldi r18, 2        ; divisor = 2
 
 check_loop:
-    ; optimization: if divisor * 2 > n, no need to continue
-    mov r19, r18
-    ldi r20, 2
-    mul r19, r20      ; r19 = divisor * 2
-    cp r19, r17       ; compare with n
-    brge is_prime     ; if divisor * 2 > n, number is prime
-    
     ; check if n is divisible by current divisor: n % divisor == 0
     mov r19, r17
-    div r19, r18      ; r19 = n / divisor (quotient)
-    mul r19, r18      ; r19 = quotient * divisor
-    mov r20, r17
-    sub r20, r19      ; r20 = n - (quotient * divisor) = remainder
-    
-    ; if remainder == 0, n is divisible (not prime)
-    cpi r20, 0
+
+mod_loop:
+    cp r19, r18
+    brlt mod_done
+    sub r19, r18
+    jmp mod_loop
+
+mod_done:
+    ; if remainder in r19 == 0, n is divisible (not prime)
+    cpi r19, 0
     breq not_prime
     
     ; try next divisor
-    inc r18           ; divisor++
+    inc r18
+    
+    ; optimization: if divisor * 2 > n, no need to continue (number is prime)
+    mov r19, r18
+    ldi r20, 2
+    mul r19, r20      ; product in R1:R0 per AVR specification
+    mov r19, r0       ; r19 = divisor * 2
+    cp r17, r19       ; compare n with divisor * 2
+    brlt is_prime     ; if n < divisor * 2, number is prime
+    
     jmp check_loop
 
 is_prime:
diff --git a/examples/multiply_by_shift.asm b/examples/multiply_by_shift.asm
index 9404688..0f6f4ab 100644
--- a/examples/multiply_by_shift.asm
+++ b/examples/multiply_by_shift.asm
@@ -13,19 +13,17 @@ loop:
     
     ; if multiplier LSB is 1, add multiplicand
     mov r19, r18
-    ldi r20, 1
-    and r19, r20
+    andi r19, 1
     cpi r19, 1
     brne no_add
     add r16, r17
 
 no_add:
-    ; shift multiplicand left (*2)
-    ldi r20, 2
-    mul r17, r20
+    ; shift multiplicand left (*2) using AVR LSL
+    lsl r17
     
-    ; shift multiplier right (/2)
-    div r18, r20
+    ; shift multiplier right (/2) using AVR LSR
+    lsr r18
     
     jmp loop
 
diff --git a/examples/power.asm b/examples/power.asm
index 3f23f1b..ce7dc71 100644
--- a/examples/power.asm
+++ b/examples/power.asm
@@ -3,31 +3,32 @@
 
 start:
     ldi r16, 3        ; base = 3
-    ldi r17, 4        ; exp = 4
+    ldi r18, 4        ; exp = 4
     
     ; save base
-    mov r18, r16
+    mov r19, r16
     
     ; if exp == 0, result = 1
-    cpi r17, 0
+    cpi r18, 0
     breq exp_zero
     
     ; if exp == 1, done
-    cpi r17, 1
+    cpi r18, 1
     breq done
     
     ; counter = 1
-    ldi r19, 1
+    ldi r20, 1
 
 loop:
-    ; result *= base
-    mul r16, r18
+    ; result *= base (stores into R1:R0 per AVR specification)
+    mul r16, r19
+    mov r16, r0
     
     ; counter++
-    inc r19
+    inc r20
     
     ; continue if counter < exp
-    cp r19, r17
+    cp r20, r18
     brlt loop
     
     jmp done
diff --git a/pyproject.toml b/pyproject.toml
index 4018759..012d1f9 100644
--- a/pyproject.toml
+++ b/pyproject.toml
@@ -1,7 +1,7 @@
 [project]
 name = "tiny8"
 version = "0.2.0"
-description = "An educational 8-bit CPU simulator with interactive visualization and assembly programming tools"
+description = "From bare metal to Generative AI: educational 8-bit AVR RISC CPU simulator with interactive visualization"
 readme = "README.md"
 authors = [{ name = "sql-hkr", email = "sql.hkr@gmail.com" }]
 requires-python = ">=3.11"
@@ -12,8 +12,7 @@ classifiers = [
     "Programming Language :: Python :: 3.13",
 ]
 dependencies = [
-    "matplotlib>=3.10.7",
-    "windows-curses ; sys_platform == 'win32'",
+    "textual>=1.0.0",
 ]
 
 [build-system]
@@ -22,12 +21,32 @@ build-backend = "uv_build"
 
 [dependency-groups]
 dev = [
+    "pillow>=13.0.0",
     "pytest>=8.4.2",
     "pytest-cov>=6.0.0",
+    "resvg-py>=0.5.0",
     "ruff>=0.14.1",
     "shibuya>=2025.10.20",
     "sphinx>=8.2.3",
+    "sphinx-intl>=2.4.0",
+    "torch>=2.0.0",
+    "torchvision>=0.15.0",
 ]
 
 [project.scripts]
-tiny8 = "tiny8.cli:main"
+tiny8 = "tiny8.tui:main"
+
+[tool.ruff]
+line-length = 88
+target-version = "py311"
+
+[tool.ruff.lint]
+select = [
+    "E",
+    "F",
+    "W",
+    "I",
+]
+ignore = [
+    "E501",
+]
diff --git a/pytest.ini b/pytest.ini
index eee0408..287eb1c 100644
--- a/pytest.ini
+++ b/pytest.ini
@@ -4,6 +4,7 @@ testpaths = tests
 python_files = test_*.py
 python_classes = Test*
 python_functions = test_*
+pythonpath = .
 
 # Output options
 addopts = 
diff --git a/scripts/__init__.py b/scripts/__init__.py
new file mode 100644
index 0000000..0b294d3
--- /dev/null
+++ b/scripts/__init__.py
@@ -0,0 +1 @@
+"""Package marker for scripts."""
diff --git a/scripts/generate_diffusion_gif.py b/scripts/generate_diffusion_gif.py
new file mode 100644
index 0000000..8f1d5e2
--- /dev/null
+++ b/scripts/generate_diffusion_gif.py
@@ -0,0 +1,476 @@
+"""Generate high-resolution animated GIF of diffusion_mnist8.asm in Tiny8 TUI.
+
+Sequential storytelling format with clean upper-right status label (transparent black bg with white text):
+1. Weight Initialization & LFSR Noise Generation in HEX mode (showing low-level CPU memory manipulation)
+2. Reverse Diffusion Denoising Trajectory (STEP 8 -> STEP 0) in PIXEL mode (showing AI digit 8 convergence)
+"""
+
+import argparse
+import asyncio
+from dataclasses import dataclass
+import io
+from pathlib import Path
+import shutil
+import subprocess
+from typing import Any
+
+from PIL import Image, ImageDraw, ImageFont
+import resvg_py
+
+from tiny8 import CPU, assemble
+from tiny8.tui import PLAYBACK_RATES, MemoryWidget, Tiny8App
+
+
+@dataclass
+class FrameSpec:
+    target_step: int
+    show_hex: bool
+    mem_start: int
+    duration_ms: int
+    label: str
+
+
+# Comprehensive, easy-to-follow diffusion process checkpoints
+DEFAULT_FRAME_SPECS = [
+    # Phase 1: Boot & Weight Initialization in HEX
+    FrameSpec(1, True, 0x0A00, 800, "CPU Boot | Memory Init (HEX)"),
+    FrameSpec(10000, True, 0x0A00, 200, "Encoder weights (0x0A00) (HEX)"),
+    FrameSpec(40000, True, 0x2F20, 200, "Decoder weights (0x2F20) (HEX)"),
+    FrameSpec(58000, True, 0x53E0, 250, "Decoder biases (0x53E0) (HEX)"),
+    # Phase 2: 16-bit PRNG LFSR Noise Generation in HEX (0x0200)
+    FrameSpec(65000, True, 0x0200, 250, "16-bit LFSR noise gen (HEX)"),
+    FrameSpec(72000, True, 0x0200, 250, "Loading noise into VRAM (HEX)"),
+    FrameSpec(75149, True, 0x0200, 700, "STEP 8: Initial noise (HEX)"),
+    # Phase 3: Mode Toggle to PIXEL Mode (STEP 8)
+    FrameSpec(75149, False, 0x0200, 500, "STEP 8: Initial noise (PIXEL)"),
+    # Phase 4: Reverse Diffusion Trajectory (STEP 8 -> 0) in PIXEL mode
+    FrameSpec(160000, False, 0x0200, 160, "Denoising step 8 -> 7"),
+    FrameSpec(241412, False, 0x0200, 200, "STEP 7: Coarse centroid"),
+    FrameSpec(325000, False, 0x0200, 160, "Denoising step 7 -> 6"),
+    FrameSpec(407675, False, 0x0200, 200, "STEP 6: Vertical lobes forming"),
+    FrameSpec(490000, False, 0x0200, 160, "Denoising step 6 -> 5"),
+    FrameSpec(573938, False, 0x0200, 220, "STEP 5: Dual loops separating"),
+    FrameSpec(655000, False, 0x0200, 160, "Denoising step 5 -> 4"),
+    FrameSpec(740205, False, 0x0200, 220, "STEP 4: Digit 8 shape clear"),
+    FrameSpec(820000, False, 0x0200, 160, "Denoising step 4 -> 3"),
+    FrameSpec(906436, False, 0x0200, 220, "STEP 3: Background cleared"),
+    FrameSpec(990000, False, 0x0200, 160, "Denoising step 3 -> 2"),
+    FrameSpec(1072668, False, 0x0200, 220, "STEP 2: Stroke refined"),
+    FrameSpec(1155000, False, 0x0200, 160, "Denoising step 2 -> 1"),
+    FrameSpec(1238899, False, 0x0200, 250, "STEP 1: Final reverse step"),
+    FrameSpec(1320000, False, 0x0200, 180, "Final pixel reconstruction"),
+    FrameSpec(1400400, False, 0x0200, 400, "STEP 0: Synthesized digit 8"),
+    # Phase 5: Synthesis Convergence
+    FrameSpec(1405127, False, 0x0200, 2200, "Convergence complete (RJMP halt)"),
+]
+
+DEFAULT_FONT = 'Menlo, Monaco, "SF Mono", "Cascadia Code", "JetBrains Mono", monospace'
+
+
+def _draw_top_right_label(
+    img: Image.Image,
+    label: str,
+) -> Image.Image:
+    """Render a compact, transparent black pill with white text in the upper-right corner."""
+    if not label:
+        return img
+
+    overlay = Image.new("RGBA", img.size, (0, 0, 0, 0))
+    ov = ImageDraw.Draw(overlay)
+
+    font_candidates = [
+        "/System/Library/Fonts/SFNSMono.ttf",
+        "/System/Library/Fonts/Menlo.ttc",
+        "/System/Library/Fonts/Monaco.ttf",
+        "/Library/Fonts/Arial Unicode.ttf",
+    ]
+    font = None
+    for fp in font_candidates:
+        if Path(fp).exists():
+            try:
+                font = ImageFont.truetype(fp, 36)
+                break
+            except Exception:
+                continue
+
+    if font is None:
+        font = ImageFont.load_default()
+
+    bb = ov.textbbox((0, 0), label, font=font)
+    tw = bb[2] - bb[0]
+    th = bb[3] - bb[1]
+
+    pad_x = 24
+    pad_y = 12
+    badge_w = tw + pad_x * 2
+    badge_h = th + pad_y * 2
+
+    margin_right = 35
+    margin_top = 8
+
+    x1 = img.width - margin_right
+    x0 = x1 - badge_w
+    y0 = margin_top
+    y1 = y0 + badge_h
+
+    # Transparent black background with subtle translucent border
+    ov.rounded_rectangle(
+        [x0, y0, x1, y1],
+        radius=12,
+        fill=(0, 0, 0, 205),
+        outline=(255, 255, 255, 75),
+        width=2,
+    )
+
+    # Crisp white text
+    ov.text((x0 + pad_x, y0 + pad_y - 2), label, fill=(255, 255, 255, 255), font=font)
+
+    return Image.alpha_composite(img, overlay)
+
+
+async def _render_snapshot_frame(
+    base_cpu: CPU,
+    snap: dict[str, Any],
+    color_mode: str,
+    spec: FrameSpec,
+    playing: bool,
+    play_direction: int,
+    rate_idx: int,
+    term_width: int,
+    term_height: int,
+    font: str = DEFAULT_FONT,
+) -> bytes:
+    """Render a single TUI frame with upper-right status label from a checkpoint snapshot."""
+    cpu = CPU()
+    cpu.program = base_cpu.program
+    cpu.labels = base_cpu.labels
+    cpu.pc_to_line = base_cpu.pc_to_line
+    cpu.source_lines = base_cpu.source_lines
+    cpu._predecoded = base_cpu._predecoded
+    cpu.regs = list(snap["regs"])
+    cpu.sreg = snap["sreg"]
+    cpu.sp = snap["sp"]
+    cpu.pc = snap["pc"]
+    cpu.step_count = snap["step"]
+    cpu.running = True
+    cpu.mem.ram = bytearray(snap["ram"])
+    cpu.mem.nonzero_ram = dict(snap["nonzero_ram"])
+
+    trace_entry = {
+        "step": snap["step"],
+        "pc": snap["pc"],
+        "instr": snap["instr"],
+        "regs": list(snap["regs"]),
+        "mem": dict(snap["nonzero_ram"]),
+        "sreg": snap["sreg"],
+        "sp": snap["sp"],
+        "source_line": snap["source_line"],
+    }
+    cpu.step_trace = [trace_entry]
+
+    app = Tiny8App(
+        cpu=cpu,
+        file_path="examples/diffusion_mnist8.asm",
+        precompute_cache=False,
+    )
+    app.traces = [trace_entry]
+    app.num_traces = 1
+    app.current_idx = 0
+    app.mem_start = spec.mem_start
+    app.speed_ms = 30
+    app.playback_rate_idx = rate_idx
+    app.batch_size = 5000
+    app.color_mode = color_mode
+    app.show_hex = spec.show_hex
+    app.playing = playing
+    app.play_direction = play_direction
+
+    async with app.run_test(size=(term_width, term_height)) as pilot:
+        app.color_mode = color_mode
+        app.show_hex = spec.show_hex
+        app.playing = playing
+        app.play_direction = play_direction
+        app.mem_start = spec.mem_start
+        try:
+            mem_w = app.query_one("#mem-view", MemoryWidget)
+            mem_w.start_addr = spec.mem_start
+            mem_w.show_hex = spec.show_hex
+            mem_w.color_mode = color_mode
+        except Exception:
+            pass
+
+        app.update_views()
+        await pilot.pause()
+        svg_content = app.export_screenshot(title="Tiny8")
+
+    # Replace font-family with Kitty-style monospace terminal font
+    if font:
+        svg_content = svg_content.replace(
+            "font-family: Fira Code, monospace;",
+            f"font-family: {font};",
+        )
+
+    png_bytes = resvg_py.svg_to_bytes(svg_content)
+    img = Image.open(io.BytesIO(png_bytes)).convert("RGBA")
+    bg = Image.new("RGB", img.size, (0, 0, 0))
+    bg.paste(img, mask=img.split()[3])
+
+    # Overlay simple top-right label (transparent black bg with white text)
+    labeled_img = _draw_top_right_label(
+        bg.convert("RGBA"),
+        label=spec.label,
+    )
+
+    out_buf = io.BytesIO()
+    labeled_img.convert("RGB").save(out_buf, format="PNG")
+    return out_buf.getvalue()
+
+
+async def generate_gif(
+    palette: str = "viridis",
+    specs: list[FrameSpec] | None = None,
+    with_reverse: bool = True,
+    output_path: str = "docs/_static/diffusion_mnist8.gif",
+    term_width: int = 160,
+    term_height: int = 42,
+    font: str = DEFAULT_FONT,
+    keep_frames: bool = False,
+) -> None:
+    """Simulate Tiny8 execution, render storytelling HEX -> PIXEL frames with top-right label, and compile into GIF."""
+    color_mode = "grayscale" if palette in ("grayscale", "gray", "grey") else "viridis"
+    frame_specs = specs or DEFAULT_FRAME_SPECS
+
+    print(
+        f"Generating diffusion GIF: palette={color_mode}, frames={len(frame_specs)}, "
+        f"with_reverse={with_reverse}, font={font}, size={term_width}x{term_height} -> {output_path}"
+    )
+
+    temp_dir = Path("scratch") / f"gif_frames_{color_mode}"
+    temp_dir.mkdir(parents=True, exist_ok=True)
+
+    asm_path = Path("examples/diffusion_mnist8.asm")
+    asm = assemble(asm_path.read_text(encoding="utf-8"))
+    halt_pc = asm.labels["halt_loop"]
+
+    base_cpu = CPU()
+    base_cpu.load_program(asm)
+    base_cpu.running = True
+
+    rate_5000_idx = PLAYBACK_RATES.index(5000) if 5000 in PLAYBACK_RATES else 6
+
+    # 1. Forward simulation: capture checkpoints for all required target steps
+    unique_steps = sorted(set(spec.target_step for spec in frame_specs))
+    print(f"Simulating CPU execution checkpoints ({len(unique_steps)} unique steps)...")
+    step_to_snapshot: dict[int, dict[str, Any]] = {}
+    for target_step in unique_steps:
+        while (
+            base_cpu.running
+            and base_cpu.step_count < target_step
+            and base_cpu.pc != halt_pc
+        ):
+            base_cpu.step(record_trace=False)
+
+        pre_pc = base_cpu.pc
+        instr_tuple = (
+            base_cpu.program[pre_pc]
+            if 0 <= pre_pc < len(base_cpu.program)
+            else ("NOP", ())
+        )
+        instr_name = instr_tuple[0]
+        instr_ops = instr_tuple[1] if len(instr_tuple) > 1 else ()
+
+        if base_cpu._predecoded and pre_pc < len(base_cpu._predecoded):
+            instr_text = base_cpu._predecoded[pre_pc][2]
+        else:
+            instr_text = f"{instr_name} {instr_ops}"
+
+        step_to_snapshot[target_step] = {
+            "step": max(1, base_cpu.step_count),
+            "pc": pre_pc,
+            "instr": instr_text,
+            "regs": list(base_cpu.regs),
+            "ram": bytes(base_cpu.mem.ram),
+            "nonzero_ram": dict(base_cpu.mem.nonzero_ram),
+            "sreg": base_cpu.sreg,
+            "sp": base_cpu.sp,
+            "source_line": asm.pc_to_line.get(pre_pc, -1),
+        }
+
+    frame_paths: list[Path] = []
+    durations_ms: list[int] = []
+    frame_counter = 0
+
+    # 2. Render Storytelling Frames (HEX weights/noise -> PIXEL denoising)
+    print("Rendering Diffusion Inference Frames with top-right label...")
+    for i, spec in enumerate(frame_specs):
+        snap = step_to_snapshot[spec.target_step]
+        is_first = i == 0
+        playing = not is_first
+        play_dir = 1
+
+        frame_bytes = await _render_snapshot_frame(
+            base_cpu=base_cpu,
+            snap=snap,
+            color_mode=color_mode,
+            spec=spec,
+            playing=playing,
+            play_direction=play_dir,
+            rate_idx=rate_5000_idx,
+            term_width=term_width,
+            term_height=term_height,
+            font=font,
+        )
+
+        png_path = temp_dir / f"frame_{frame_counter:03d}.png"
+        png_path.write_bytes(frame_bytes)
+        frame_paths.append(png_path)
+        frame_counter += 1
+        durations_ms.append(spec.duration_ms)
+
+        mode_str = "HEX" if spec.show_hex else "PIXEL"
+        print(f"  [{i + 1:2d}/{len(frame_specs)}] step {snap['step']:,} [{mode_str} @ 0x{spec.mem_start:04X}]: {spec.label}")
+
+    # 3. Optional Reverse Phase (back down to STEP 8 initial noise in PIXEL mode)
+    if with_reverse:
+        print("Rendering Reverse Phase back down to STEP 8 PIXEL noise...")
+        pixel_start_idx = -1
+        for idx, s in enumerate(frame_specs):
+            if s.target_step == 75149 and not s.show_hex:
+                pixel_start_idx = idx
+                break
+
+        if pixel_start_idx >= 0:
+            rev_specs = frame_specs[len(frame_specs) - 2 : pixel_start_idx - 1 : -1]
+        else:
+            rev_specs = list(reversed(frame_specs))
+
+        for j, spec in enumerate(rev_specs):
+            snap = step_to_snapshot[spec.target_step]
+            is_last = j == len(rev_specs) - 1
+            frame_bytes = await _render_snapshot_frame(
+                base_cpu=base_cpu,
+                snap=snap,
+                color_mode="grayscale",
+                spec=spec,
+                playing=True,
+                play_direction=-1,
+                rate_idx=rate_5000_idx,
+                term_width=term_width,
+                term_height=term_height,
+                font=font,
+            )
+            png_path = temp_dir / f"frame_{frame_counter:03d}.png"
+            png_path.write_bytes(frame_bytes)
+            frame_paths.append(png_path)
+            frame_counter += 1
+            durations_ms.append(spec.duration_ms if is_last else 160)
+            print(f"  [rev {j + 1:2d}/{len(rev_specs)}] step {snap['step']:,} [PIXEL @ 0x{spec.mem_start:04X}]: {spec.label}")
+
+    concat_txt = temp_dir / "input.txt"
+    with open(concat_txt, "w", encoding="utf-8") as f:
+        for p, dur_ms in zip(frame_paths, durations_ms):
+            f.write(f"file '{p.name}'\n")
+            f.write(f"duration {dur_ms / 1000.0:.3f}\n")
+        f.write(f"file '{frame_paths[-1].name}'\n")
+
+    out_file = Path(output_path)
+    out_file.parent.mkdir(parents=True, exist_ok=True)
+
+    if shutil.which("ffmpeg"):
+        cmd = [
+            "ffmpeg",
+            "-y",
+            "-f",
+            "concat",
+            "-safe",
+            "0",
+            "-i",
+            str(concat_txt.resolve()),
+            "-vf",
+            "scale=1280:-1:flags=lanczos,split[s0][s1];[s0]palettegen=max_colors=256:reserve_transparent=0[p];[s1][p]paletteuse=dither=bayer:bayer_scale=3",
+            "-loop",
+            "0",
+            str(out_file.resolve()),
+        ]
+        subprocess.run(cmd, check=True)
+    else:
+        # Fallback to Pillow
+        images = []
+        for p in frame_paths:
+            im = Image.open(p)
+            w, h = im.size
+            new_h = int(h * 1280 / w)
+            im_resized = im.resize((1280, new_h), Image.Resampling.LANCZOS)
+            images.append(im_resized)
+        images[0].save(
+            out_file,
+            save_all=True,
+            append_images=images[1:],
+            duration=durations_ms,
+            loop=0,
+            optimize=True,
+        )
+
+    print(f"Done! GIF saved to {out_file} ({out_file.stat().st_size:,} bytes)")
+
+    if not keep_frames:
+        shutil.rmtree(temp_dir, ignore_errors=True)
+
+
+def main() -> None:
+    parser = argparse.ArgumentParser(
+        description="Generate animated GIF of diffusion_mnist8.asm in Tiny8 TUI with upper-right status label."
+    )
+    parser.add_argument(
+        "--palette",
+        "-p",
+        choices=["grayscale", "gray", "grey", "viridis"],
+        default="viridis",
+        help="Color palette for memory heatmap (default: viridis)",
+    )
+    parser.add_argument(
+        "--font",
+        "-f",
+        default=DEFAULT_FONT,
+        help="Font family stack for TUI terminal rendering (default: Menlo / SF Mono / Kitty font)",
+    )
+    parser.add_argument(
+        "--no-reverse",
+        action="store_true",
+        help="Disable reverse playback phase (enabled by default down to STEP 8 initial noise)",
+    )
+    parser.add_argument(
+        "--output",
+        "-o",
+        default="docs/_static/diffusion_mnist8.gif",
+        help="Destination path for output GIF (default: docs/_static/diffusion_mnist8.gif)",
+    )
+    parser.add_argument(
+        "--width",
+        type=int,
+        default=160,
+        help="Terminal width in columns (default: 160)",
+    )
+    parser.add_argument(
+        "--height",
+        type=int,
+        default=42,
+        help="Terminal height in lines (default: 42)",
+    )
+
+    args = parser.parse_args()
+
+    asyncio.run(
+        generate_gif(
+            palette=args.palette,
+            with_reverse=not args.no_reverse,
+            output_path=args.output,
+            term_width=args.width,
+            term_height=args.height,
+            font=args.font,
+        )
+    )
+
+
+if __name__ == "__main__":
+    main()
diff --git a/scripts/train_diffusion.py b/scripts/train_diffusion.py
new file mode 100644
index 0000000..dddd2f5
--- /dev/null
+++ b/scripts/train_diffusion.py
@@ -0,0 +1,773 @@
+"""Train an ultra-compact Diffusion Model on MNIST digit 8 and export Tiny8 AVR assembly.
+
+Uses PyTorch and torchvision.datasets.MNIST to train a compact 8-step reverse diffusion
+model generating the digit 8 at native 28x28 resolution, quantizes the parameters, and exports a pure
+AVR assembly implementation (`examples/diffusion_mnist8.asm`) that runs directly on the Tiny8 8-bit CPU,
+rendering each denoising step into 32x32 VRAM (centered 28x28 canvas).
+"""
+
+from __future__ import annotations
+
+import argparse
+from pathlib import Path
+import numpy as np
+import torch
+import torch.nn as nn
+import torch.optim as optim
+from torch.utils.data import DataLoader, TensorDataset
+import torchvision
+import torchvision.transforms as transforms
+
+
+class TinyDiffusion8(nn.Module):
+    """Ultra-compact 8-step diffusion model for native 28x28 MNIST digit 8."""
+
+    def __init__(self, t_steps: int = 8, hidden_dim: int = 12) -> None:
+        super().__init__()
+        self.t_steps = t_steps
+        self.hidden_dim = hidden_dim
+
+        # Encoder: 784 pixels -> hidden_dim (bias=False since t_embed provides per-step bias)
+        self.enc = nn.Linear(784, hidden_dim, bias=False)
+        # Timestep embedding: t_steps -> hidden_dim
+        self.t_embed = nn.Embedding(t_steps, hidden_dim)
+        # Decoder: hidden_dim -> 784 pixels
+        self.dec = nn.Linear(hidden_dim, 784)
+
+    def forward(self, x: torch.Tensor, t: torch.Tensor) -> torch.Tensor:
+        # h = clamp(ReLU(enc(x) + t_embed(t)), max=127/64) matching AVR 7-bit ReLU range
+        h = torch.clamp(torch.relu(self.enc(x) + self.t_embed(t)), max=127.0 / 64.0)
+        # Logits prediction of clean x0
+        return self.dec(h)
+
+
+def train_model(
+    epochs: int = 15,
+    batch_size: int = 256,
+    lr: float = 0.01,
+    seed: int = 42,
+    data_dir: str | Path = "./data",
+) -> tuple[TinyDiffusion8, torch.Tensor, torch.Tensor, torch.Tensor]:
+    """Load MNIST digit 8 and train TinyDiffusion8 model."""
+    torch.manual_seed(seed)
+    np.random.seed(seed)
+
+    transform = transforms.Compose(
+        [
+            transforms.ToTensor(),
+        ]
+    )
+    mnist = torchvision.datasets.MNIST(
+        root=str(data_dir), train=True, download=True, transform=transform
+    )
+    eights = torch.stack([img.view(-1) for img, label in mnist if label == 8])
+    target_eights = (eights > 0.25).float()
+    print(f"Loaded {len(eights)} digit 8 samples from torchvision MNIST (28x28).")
+
+    t_steps = 8
+    betas = torch.linspace(0.1, 0.5, t_steps)
+    alphas = 1.0 - betas
+    alphas_bar = torch.cumprod(alphas, dim=0)
+
+    model = TinyDiffusion8(t_steps=t_steps, hidden_dim=12)
+    opt = optim.Adam(model.parameters(), lr=lr, weight_decay=1e-4)
+
+    dataset = TensorDataset(target_eights)
+    loader = DataLoader(dataset, batch_size=batch_size, shuffle=True, drop_last=False)
+
+    for ep in range(epochs):
+        epoch_loss = 0.0
+        num_batches = 0
+        for (x0,) in loader:
+            t = torch.randint(0, t_steps, (x0.size(0),))
+            a_bar = alphas_bar[t].unsqueeze(1)
+            noise = torch.randn_like(x0)
+            xt = torch.sqrt(a_bar) * x0 + torch.sqrt(1.0 - a_bar) * noise
+            logits = model(xt, t)
+            loss = nn.functional.binary_cross_entropy_with_logits(logits, x0)
+            opt.zero_grad()
+            loss.backward()
+            opt.step()
+
+            # Clamp weights to prevent 16-bit signed MAC overflow on 8-bit AVR CPU
+            with torch.no_grad():
+                model.enc.weight.clamp_(-0.5, 0.5)
+                model.t_embed.weight.clamp_(-0.99, 0.99)
+
+            epoch_loss += loss.item()
+            num_batches += 1
+
+        if (ep + 1) % 5 == 0 or ep == epochs - 1:
+            avg_loss = epoch_loss / max(1, num_batches)
+            print(f"Epoch {ep + 1}/{epochs}, Loss: {avg_loss:.4f}")
+
+    return model, betas, alphas, alphas_bar
+
+
+def generate_assembly(
+    model: TinyDiffusion8,
+    betas: torch.Tensor,
+    alphas: torch.Tensor,
+    alphas_bar: torch.Tensor,
+    out_path: Path,
+) -> None:
+    """Quantize model weights and generate Tiny8 AVR assembly code."""
+    w_enc = model.enc.weight.detach().numpy()  # (12, 784)
+    t_embed = model.t_embed.weight.detach().numpy()  # (8, 12)
+    if model.enc.bias is not None:
+        t_embed = t_embed + model.enc.bias.detach().numpy()[None, :]
+    w_dec = model.dec.weight.detach().numpy()  # (784, 12)
+    b_dec = model.dec.bias.detach().numpy()  # (784,)
+
+    # Fixed-point scale alignment:
+    # - img is in [0..255] (~256 = 2^8)
+    # - w_enc_int is scaled by scale_enc = 8 (2^3) -> w_enc_int * img has scale 2048 (2^11)
+    # - t_embed_int is scaled by scale_t = 128 (2^7) and shifted << 4 in ASM -> scale 2048 (2^11)
+    # - After >> 5 in ASM, hidden activations have scale 2048 >> 5 = 64 (2^6)
+    # - w_dec_int has scale_dec = 16 (2^4), b_dec_int16 has scale 16 * 64 = 1024 (2^10)
+    scale_enc = 8.0
+    scale_t = scale_enc * 16.0
+    scale_dec = 16.0
+
+    w_enc_int = np.clip(np.round(w_enc * scale_enc), -128, 127).astype(np.int8)
+    t_embed_int = np.clip(np.round(t_embed * scale_t), -128, 127).astype(np.int8)
+    w_dec_int = np.clip(np.round(w_dec * scale_dec), -128, 127).astype(np.int8)
+    b_dec_int16 = np.clip(np.round(b_dec * scale_dec * 64.0), -32768, 32767).astype(
+        np.int16
+    )
+
+    # Verify 16-bit signed accumulator bounds on uniform mid-gray / noise input (mean ~128)
+    mean_acc = np.abs(w_enc_int.astype(np.int32).sum(axis=1) * 128) + 128 * 16
+    if mean_acc.max() > 32767:
+        print(
+            f"Warning: encoder MAC mean accumulator {mean_acc.max()} "
+            "may exceed 16-bit signed bounds."
+        )
+
+    # Precompute blend weights for reverse steps
+    t_steps = 8
+    c1_list = []
+    c2_list = []
+    for s in range(t_steps):
+        if s > 0:
+            a_bar_prev = alphas_bar[s - 1].item()
+            a_bar_cur = alphas_bar[s].item()
+            beta = betas[s].item()
+            c1 = (np.sqrt(a_bar_prev) * beta) / (1 - a_bar_cur)
+            c2 = (np.sqrt(alphas[s].item()) * (1 - a_bar_prev)) / (1 - a_bar_cur)
+            c_sum = c1 + c2
+            c1_int = int(round(c1 / c_sum * 16))
+            c2_int = 16 - c1_int
+        else:
+            c1_int = 16
+            c2_int = 0
+        c1_list.append(c1_int)
+        c2_list.append(c2_int)
+
+    # Memory Map:
+    # 0x0060..0x006B: hidden activations (12 bytes)
+    # 0x0070..0x007F: temps (step_t, counters)
+    # 0x0200..0x05FF: 32x32 VRAM (1024 bytes)
+    # 0x0600..0x090F: img buffer (784 bytes, 28x28)
+    # 0x0A00..0x2EBF: w_enc (12 x 784 = 9408 bytes)
+    # 0x2EC0..0x2F1F: t_embed (8 x 12 = 96 bytes)
+    # 0x2F20..0x53DF: w_dec (784 x 12 = 9408 bytes)
+    # 0x53E0..0x59FF: b_dec (784 x 2 = 1568 bytes)
+    # 0x5D20..0x5D2F: blend coeffs (16 bytes)
+
+    lines = [
+        "; ==================================================================",
+        "; TINY8 NATIVE 28x28 DIFFUSION MODEL FOR MNIST DIGIT 8",
+        "; Trained on torchvision.datasets.MNIST (8 reverse steps)",
+        "; Direct 32x32 Heatmap VRAM: 0x0200..0x05FF (1024 bytes)",
+        "; Progressive Denoising Trajectory: t = 8 -> 7 -> ... -> 0",
+        "; ==================================================================",
+        "",
+        "; Memory Map in RAM (0x0000..0xFFFF, 64KB total):",
+        ";   0x0060..0x006B: hidden (12 bytes, activations 0..127)",
+        ";   0x0070..0x007F: temps (step_t, counters)",
+        ";   0x0200..0x05FF: 32x32 VRAM (1024 bytes heatmap monitor)",
+        ";   0x0600..0x090F: img (784 bytes, 28x28 pixel intensity 0..255)",
+        ";   0x0A00..0x2EBF: w_enc (12 x 784 = 9408 bytes, signed int8)",
+        ";   0x2EC0..0x2F1F: t_embed (8 x 12 = 96 bytes, signed int8)",
+        ";   0x2F20..0x53DF: w_dec (784 x 12 = 9408 bytes, signed int8)",
+        ";   0x53E0..0x59FF: b_dec (784 x 2 = 1568 bytes, signed int16)",
+        ";   0x5D20..0x5D2F: c1, c2 blend coefficients (8 + 8 bytes)",
+        "",
+        ".data_init:",
+    ]
+
+    # Emit weight tables initialization
+    def emit_array_init(base_addr: int, arr: np.ndarray, label: str):
+        lines.append(f"; Initialize {label} at 0x{base_addr:04X} ({len(arr)} bytes)")
+        lines.append(f"    LDI R30, {base_addr & 0xFF}")
+        lines.append(f"    LDI R31, {base_addr >> 8}")
+        for i, v in enumerate(arr):
+            lines.append(f"    LDI R16, {int(v) & 0xFF}")
+            lines.append("    ST R30, R16")
+            if i < len(arr) - 1:
+                lines.append("    ADIW R30, 1")
+        lines.append("    LDI R31, 0")
+        lines.append("")
+
+    # Flattened arrays
+    emit_array_init(0x0A00, w_enc_int.flatten(), "w_enc")
+    emit_array_init(0x2EC0, t_embed_int.flatten(), "t_embed")
+    emit_array_init(0x2F20, w_dec_int.flatten(), "w_dec")
+
+    # b_dec as 16-bit little-endian
+    b_dec_bytes = []
+    for b in b_dec_int16:
+        ub = int(b) & 0xFFFF
+        b_dec_bytes.append(ub & 0xFF)
+        b_dec_bytes.append((ub >> 8) & 0xFF)
+    emit_array_init(0x53E0, np.array(b_dec_bytes, dtype=np.uint8), "b_dec")
+
+    # Blend coefficients table at 0x5D20
+    lines.append("; Blend coefficients (c1: 8 bytes, c2: 8 bytes at 0x5D20)")
+    lines.append("    LDI R30, 0x20")
+    lines.append("    LDI R31, 0x5D")
+    for c in c1_list + c2_list:
+        lines.append(f"    LDI R16, {c}")
+        lines.append("    ST R30, R16")
+        lines.append("    ADIW R30, 1")
+    lines.append("    LDI R31, 0")
+    lines.append("")
+
+    # Main control flow
+    lines.extend(
+        [
+            "main:",
+            "    ; Generate initial pseudo-Gaussian noise (step 8) into img buffer (0x0600)",
+            "    ; 784 bytes = 4 outer * 196 inner, using 16-bit Galois LFSR + 2-byte average",
+            "    LDI R26, 0x00      ; X = &img[0] (0x0600)",
+            "    LDI R27, 0x06",
+            "    LDI R24, 0xE1      ; 16-bit LFSR seed low byte (0xACE1)",
+            "    LDI R25, 0xAC      ; 16-bit LFSR seed high byte",
+            "    LDI R18, 0xB4      ; LFSR polynomial tap mask",
+            "    LDI R22, 4",
+            "gen_noise_outer:",
+            "    LDI R23, 196",
+            "gen_noise_inner:",
+            "    LSR R25",
+            "    ROR R24",
+            "    BRCC no_xor",
+            "    EOR R25, R18",
+            "no_xor:",
+            "    MOV R20, R24",
+            "    ADD R20, R25",
+            "    ROR R20            ; average two uniform bytes -> bell-shaped 0..255",
+            "    ST X, R20",
+            "    ADIW R26, 1",
+            "    DEC R23",
+            "    BRNE gen_noise_inner",
+            "    DEC R22",
+            "    BRNE gen_noise_outer",
+            "",
+            "    ; Render Initial Step 8 (Pure Noise)",
+            "    LDI R16, 8",
+            "    STS 0x0070, R16    ; cur_step = 8",
+            "    RCALL render_vram",
+            "",
+            "    ; Denoising Loop: t = 7 down to 0",
+            "    LDI R19, 7         ; R19 = current step t",
+            "diffusion_step_loop:",
+            "    STS 0x0070, R19    ; save step t",
+            "",
+            "    ; ----------------------------------------------------------------",
+            "    ; Stage 1: Encoder - Compute 12 Hidden Activations",
+            "    ; h_k = ReLU( ((t_embed[t, k] << 4) + sum(w_enc[k, j] * img[j])) >> 5 )",
+            "    ; ----------------------------------------------------------------",
+            "    LDI R22, 0         ; k = 0",
+            "node_loop:",
+            "    ; Load t_embed[t, k] from 0x2EC0 + t * 12 + k",
+            "    LDS R16, 0x0070    ; R16 = t",
+            "    LDI R17, 12",
+            "    MUL R16, R17       ; R1:R0 = t * 12",
+            "    ADD R0, R22        ; + k",
+            "    LDI R30, 0xC0",
+            "    LDI R31, 0x2E",
+            "    ADD R30, R0",
+            "    ADC R31, R1",
+            "    LD R24, Z          ; R24 = t_embed[t, k] (signed 8-bit)",
+            "    LDI R25, 0",
+            "    SBRC R24, 7",
+            "    LDI R25, 255       ; sign extend",
+            "",
+            "    ; Shift left 4: R25:R24 << 4",
+            "    LDI R18, 4",
+            "t_shl_loop:",
+            "    LSL R24",
+            "    ROL R25",
+            "    DEC R18",
+            "    BRNE t_shl_loop",
+            "",
+            "    ; Base address for w_enc[k]: 0x0A00 + k * 784",
+            "    ; 784 = 256 * 3 + 16 (0x0310)",
+            "    LDI R16, 16",
+            "    MUL R22, R16       ; R1:R0 = k * 16",
+            "    MOV R20, R0",
+            "    MOV R21, R1",
+            "    LDI R16, 3",
+            "    MUL R22, R16       ; R1:R0 = k * 3",
+            "    ADD R21, R0        ; R21:R20 = k * 784",
+            "    LDI R30, 0x00",
+            "    LDI R31, 0x0A",
+            "    ADD R30, R20",
+            "    ADC R31, R21       ; Z = &w_enc[k, 0]",
+            "",
+            "    ; X = &img[0] (0x0600)",
+            "    LDI R26, 0x00",
+            "    LDI R27, 0x06",
+            "",
+            "    ; 784 MAC operations: 28 outer * 28 inner",
+            "    LDI R18, 28",
+            "enc_mac_outer:",
+            "    LDI R19, 28",
+            "enc_mac_inner:",
+            "    LD R16, Z          ; R16 = w_enc[k, j] (signed)",
+            "    LD R17, X          ; R17 = img[j] (unsigned)",
+            "    MULSU R16, R17     ; R1:R0 = w_enc * img (signed 16-bit)",
+            "    ADD R24, R0",
+            "    ADC R25, R1",
+            "    ADIW R30, 1",
+            "    ADIW R26, 1",
+            "    DEC R19",
+            "    BRNE enc_mac_inner",
+            "    DEC R18",
+            "    BRNE enc_mac_outer",
+            "",
+            "    ; Shift right 5 arithmetic: (R25:R24) >> 5",
+            "    LDI R18, 5",
+            "enc_shr_loop:",
+            "    ASR R25",
+            "    ROR R24",
+            "    DEC R18",
+            "    BRNE enc_shr_loop",
+            "",
+            "    ; ReLU: if sum < 0 then 0, clamp max 127",
+            "    SBRC R25, 7",
+            "    RJMP relu_zero",
+            "    CPI R25, 0",
+            "    BRNE relu_clamp_max",
+            "    CPI R24, 127",
+            "    BRCS relu_ok",
+            "relu_clamp_max:",
+            "    LDI R24, 127",
+            "    RJMP relu_ok",
+            "relu_zero:",
+            "    LDI R24, 0",
+            "relu_ok:",
+            "    ; Store into hidden[k] (at 0x0060 + k)",
+            "    LDI R30, 0x60",
+            "    LDI R31, 0x00",
+            "    ADD R30, R22",
+            "    ST R30, R24",
+            "",
+            "    INC R22            ; k++",
+            "    CPI R22, 12",
+            "    BRNE node_loop",
+            "",
+            "    ; Cache hidden activations into R2..R13 for high-throughput unrolled decoding",
+            "    LDS R2, 0x0060",
+            "    LDS R3, 0x0061",
+            "    LDS R4, 0x0062",
+            "    LDS R5, 0x0063",
+            "    LDS R6, 0x0064",
+            "    LDS R7, 0x0065",
+            "    LDS R8, 0x0066",
+            "    LDS R9, 0x0067",
+            "    LDS R10, 0x0068",
+            "    LDS R11, 0x0069",
+            "    LDS R12, 0x006A",
+            "    LDS R13, 0x006B",
+            "",
+            "    ; ----------------------------------------------------------------",
+            "    ; Stage 2: Decoder & Blend - Reconstruct and Update img (784 pixels)",
+            "    ; Sequential pointers: Y=&b_dec, Z=&w_dec, X=&img",
+            "    ; ----------------------------------------------------------------",
+            "    LDS R19, 0x0070    ; restore t",
+            "    ; Load c1 from 0x5D20 + t, c2 from 0x5D28 + t",
+            "    LDI R30, 0x20",
+            "    LDI R31, 0x5D",
+            "    ADD R30, R19",
+            "    LD R14, Z          ; R14 = c1",
+            "    LDI R30, 0x28",
+            "    LDI R31, 0x5D",
+            "    ADD R30, R19",
+            "    LD R15, Z          ; R15 = c2",
+            "",
+            "    ; Pointers for sequential pass:",
+            "    ; Y = &b_dec[0] (0x53E0)",
+            "    ; Z = &w_dec[0, 0] (0x2F20)",
+            "    ; X = &img[0] (0x0600)",
+            "    LDI R28, 0xE0",
+            "    LDI R29, 0x53",
+            "    LDI R30, 0x20",
+            "    LDI R31, 0x2F",
+            "    LDI R26, 0x00",
+            "    LDI R27, 0x06",
+            "",
+            "    ; 784 pixels: 28 outer * 28 inner",
+            "    LDI R22, 28        ; outer loop counter",
+            "pixel_dec_outer:",
+            "    LDI R23, 28        ; inner loop counter",
+            "pixel_dec_inner:",
+            "    ; Load 16-bit b_dec from Y",
+            "    LD R24, Y",
+            "    ADIW R28, 1",
+            "    LD R25, Y",
+            "    ADIW R28, 1",
+            "",
+            "    ; Unrolled 12-term MAC directly against cached hidden registers R2..R13",
+            "    LD R16, Z",
+            "    ADIW R30, 1",
+            "    MULS R16, R2",
+            "    ADD R24, R0",
+            "    ADC R25, R1",
+            "",
+            "    LD R16, Z",
+            "    ADIW R30, 1",
+            "    MULS R16, R3",
+            "    ADD R24, R0",
+            "    ADC R25, R1",
+            "",
+            "    LD R16, Z",
+            "    ADIW R30, 1",
+            "    MULS R16, R4",
+            "    ADD R24, R0",
+            "    ADC R25, R1",
+            "",
+            "    LD R16, Z",
+            "    ADIW R30, 1",
+            "    MULS R16, R5",
+            "    ADD R24, R0",
+            "    ADC R25, R1",
+            "",
+            "    LD R16, Z",
+            "    ADIW R30, 1",
+            "    MULS R16, R6",
+            "    ADD R24, R0",
+            "    ADC R25, R1",
+            "",
+            "    LD R16, Z",
+            "    ADIW R30, 1",
+            "    MULS R16, R7",
+            "    ADD R24, R0",
+            "    ADC R25, R1",
+            "",
+            "    LD R16, Z",
+            "    ADIW R30, 1",
+            "    MULS R16, R8",
+            "    ADD R24, R0",
+            "    ADC R25, R1",
+            "",
+            "    LD R16, Z",
+            "    ADIW R30, 1",
+            "    MULS R16, R9",
+            "    ADD R24, R0",
+            "    ADC R25, R1",
+            "",
+            "    LD R16, Z",
+            "    ADIW R30, 1",
+            "    MULS R16, R10",
+            "    ADD R24, R0",
+            "    ADC R25, R1",
+            "",
+            "    LD R16, Z",
+            "    ADIW R30, 1",
+            "    MULS R16, R11",
+            "    ADD R24, R0",
+            "    ADC R25, R1",
+            "",
+            "    LD R16, Z",
+            "    ADIW R30, 1",
+            "    MULS R16, R12",
+            "    ADD R24, R0",
+            "    ADC R25, R1",
+            "",
+            "    LD R16, Z",
+            "    ADIW R30, 1",
+            "    MULS R16, R13",
+            "    ADD R24, R0",
+            "    ADC R25, R1",
+            "",
+            "    ; Piecewise Linear Sigmoid: R25:R24 = (R25:R24) >> 2 + 128",
+            "    ASR R25",
+            "    ROR R24",
+            "    ASR R25",
+            "    ROR R24",
+            "    LDI R16, 128",
+            "    ADD R24, R16",
+            "    LDI R16, 0",
+            "    ADC R25, R16",
+            "",
+            "    ; Clamp to [0, 255] in R16",
+            "    SBRS R25, 7        ; if negative sign bit set -> clamp to 0",
+            "    RJMP check_pos_clamp",
+            "    LDI R16, 0",
+            "    RJMP clamp_done",
+            "check_pos_clamp:",
+            "    CPI R25, 0",
+            "    BREQ clamp_ok",
+            "    LDI R16, 255       ; clamp high",
+            "    RJMP clamp_done",
+            "clamp_ok:",
+            "    MOV R16, R24       ; x0_hat[i] is in R16",
+            "clamp_done:",
+            "",
+            "    ; Blend: res = (c1 * R16 + c2 * img[i]) / 16",
+            "    MUL R16, R14       ; c1 * x0_hat",
+            "    MOV R20, R0",
+            "    MOV R21, R1",
+            "",
+            "    LD R16, X          ; R16 = old img[i]",
+            "    MUL R16, R15       ; c2 * img[i]",
+            "    ADD R20, R0",
+            "    ADC R21, R1",
+            "",
+            "    ; Divide by 16: shift right 4",
+            "    LSR R21",
+            "    ROR R20",
+            "    LSR R21",
+            "    ROR R20",
+            "    LSR R21",
+            "    ROR R20",
+            "    LSR R21",
+            "    ROR R20",
+            "",
+            "    ; Store into img[i] and advance X",
+            "    ST X, R20",
+            "    ADIW R26, 1",
+            "",
+            "    DEC R23",
+            "    BRNE pixel_dec_inner",
+            "    DEC R22",
+            "    BRNE pixel_dec_outer",
+            "",
+            "    ; Render current step to VRAM",
+            "    RCALL render_vram",
+            "",
+            "    LDS R19, 0x0070    ; restore step t",
+            "    DEC R19",
+            "    CPI R19, 255       ; checks underflow below 0",
+            "    BREQ diffusion_done",
+            "    RJMP diffusion_step_loop",
+            "",
+            "diffusion_done:",
+            "    ; Infinite halt display loop",
+            "halt_loop:",
+            "    RJMP halt_loop",
+            "",
+            "; ==================================================================",
+            "; SUBROUTINE: render_vram",
+            "; 1:1 Direct copy of 28x28 img (0x0600) into 32x32 VRAM (0x0200)",
+            "; Center region: rows 2..29, cols 2..29",
+            "; Also writes Header row 0 and Footer row 31",
+            "; ==================================================================",
+            "render_vram:",
+            "    ; Clear Row 0",
+            "    LDI R30, 0x00",
+            "    LDI R31, 0x02",
+            "    LDI R16, 32        ; ' '",
+            "    LDI R18, 32",
+            "clr_hdr_loop:",
+            "    ST R30, R16",
+            "    ADIW R30, 1",
+            "    DEC R18",
+            "    BRNE clr_hdr_loop",
+            "",
+            "    ; Write Header Text at 0x0201: 'DIFFUSION MNIST:8'",
+            "    LDI R30, 0x01",
+            "    LDI R31, 0x02",
+            "    LDI R16, 68 ; 'D'",
+            "    ST R30, R16",
+            "    ADIW R30, 1",
+            "    LDI R16, 73 ; 'I'",
+            "    ST R30, R16",
+            "    ADIW R30, 1",
+            "    LDI R16, 70 ; 'F'",
+            "    ST R30, R16",
+            "    ADIW R30, 1",
+            "    LDI R16, 70 ; 'F'",
+            "    ST R30, R16",
+            "    ADIW R30, 1",
+            "    LDI R16, 85 ; 'U'",
+            "    ST R30, R16",
+            "    ADIW R30, 1",
+            "    LDI R16, 83 ; 'S'",
+            "    ST R30, R16",
+            "    ADIW R30, 1",
+            "    LDI R16, 73 ; 'I'",
+            "    ST R30, R16",
+            "    ADIW R30, 1",
+            "    LDI R16, 79 ; 'O'",
+            "    ST R30, R16",
+            "    ADIW R30, 1",
+            "    LDI R16, 78 ; 'N'",
+            "    ST R30, R16",
+            "    ADIW R30, 1",
+            "    LDI R16, 32 ; ' '",
+            "    ST R30, R16",
+            "    ADIW R30, 1",
+            "    LDI R16, 77 ; 'M'",
+            "    ST R30, R16",
+            "    ADIW R30, 1",
+            "    LDI R16, 78 ; 'N'",
+            "    ST R30, R16",
+            "    ADIW R30, 1",
+            "    LDI R16, 73 ; 'I'",
+            "    ST R30, R16",
+            "    ADIW R30, 1",
+            "    LDI R16, 83 ; 'S'",
+            "    ST R30, R16",
+            "    ADIW R30, 1",
+            "    LDI R16, 84 ; 'T'",
+            "    ST R30, R16",
+            "    ADIW R30, 1",
+            "    LDI R16, 58 ; ':'",
+            "    ST R30, R16",
+            "    ADIW R30, 1",
+            "    LDI R16, 56 ; '8'",
+            "    ST R30, R16",
+            "    ADIW R30, 1",
+            "",
+            "    ; Step indicator: 'STEP:[' t ']' at 0x0216",
+            "    LDI R30, 0x16",
+            "    LDI R31, 0x02",
+            "    LDI R16, 83 ; 'S'",
+            "    ST R30, R16",
+            "    ADIW R30, 1",
+            "    LDI R16, 84 ; 'T'",
+            "    ST R30, R16",
+            "    ADIW R30, 1",
+            "    LDI R16, 69 ; 'E'",
+            "    ST R30, R16",
+            "    ADIW R30, 1",
+            "    LDI R16, 80 ; 'P'",
+            "    ST R30, R16",
+            "    ADIW R30, 1",
+            "    LDI R16, 58 ; ':'",
+            "    ST R30, R16",
+            "    ADIW R30, 1",
+            "    LDI R16, 91 ; '['",
+            "    ST R30, R16",
+            "    ADIW R30, 1",
+            "    LDS R16, 0x0070    ; step t",
+            "    LDI R17, 48        ; '0'",
+            "    ADD R16, R17       ; ASCII digit",
+            "    ST R30, R16",
+            "    ADIW R30, 1",
+            "    LDI R16, 93 ; ']'",
+            "    ST R30, R16",
+            "",
+            "    ; Direct 1:1 copy of 28x28 img into centered 28x28 VRAM (rows 2..29, cols 2..29)",
+            "    ; X = &img[0] (0x0600)",
+            "    LDI R26, 0x00",
+            "    LDI R27, 0x06",
+            "    LDI R22, 0         ; r = 0..27",
+            "render_r_loop:",
+            "    ; VRAM row = 2 + r, col = 2",
+            "    ; VRAM row start: 0x0200 + (r + 2) * 32 + 2",
+            "    LDI R16, 2",
+            "    ADD R16, R22       ; R16 = r + 2",
+            "    LDI R17, 32",
+            "    MUL R16, R17       ; R1:R0 = (r + 2) * 32",
+            "    LDI R30, 0x02      ; col offset 2",
+            "    LDI R31, 0x02      ; base 0x0200",
+            "    ADD R30, R0",
+            "    ADC R31, R1        ; Z = &VRAM[r + 2, 2]",
+            "",
+            "    LDI R23, 28        ; 28 columns",
+            "render_c_loop:",
+            "    LD R16, X",
+            "    ST R30, R16",
+            "    ADIW R26, 1",
+            "    ADIW R30, 1",
+            "    DEC R23",
+            "    BRNE render_c_loop",
+            "",
+            "    INC R22",
+            "    CPI R22, 28",
+            "    BRNE render_r_loop",
+            "",
+            "    ; Clear Footer row 31 (0x05E0..0x05FF)",
+            "    LDI R30, 0xE0",
+            "    LDI R31, 0x05",
+            "    LDI R16, 32",
+            "    LDI R18, 32",
+            "clr_ftr_loop:",
+            "    ST R30, R16",
+            "    ADIW R30, 1",
+            "    DEC R18",
+            "    BRNE clr_ftr_loop",
+            "",
+            "    RET",
+            "",
+        ]
+    )
+
+    out_path.parent.mkdir(parents=True, exist_ok=True)
+    out_path.write_text("\n".join(lines) + "\n")
+    print(f"Exported Tiny8 AVR assembly model to {out_path} ({len(lines)} lines)")
+
+
+def main() -> None:
+    parser = argparse.ArgumentParser(
+        description="Train native 28x28 Tiny8 diffusion model on MNIST digit 8 and export AVR assembly."
+    )
+    parser.add_argument(
+        "--epochs",
+        "-e",
+        type=int,
+        default=15,
+        help="Number of full dataset training epochs (default: 15)",
+    )
+    parser.add_argument(
+        "--batch-size",
+        "-b",
+        type=int,
+        default=256,
+        help="Mini-batch size (default: 256)",
+    )
+    parser.add_argument(
+        "--lr",
+        type=float,
+        default=0.01,
+        help="Learning rate for Adam optimizer (default: 0.01)",
+    )
+    parser.add_argument(
+        "--seed",
+        type=int,
+        default=42,
+        help="Random seed for reproducibility (default: 42)",
+    )
+    parser.add_argument(
+        "--data-dir",
+        default="./data",
+        help="Directory for torchvision MNIST dataset (default: ./data)",
+    )
+    parser.add_argument(
+        "--output",
+        "-o",
+        default="examples/diffusion_mnist8.asm",
+        help="Output AVR assembly file path (default: examples/diffusion_mnist8.asm)",
+    )
+    args = parser.parse_args()
+
+    print("--- Training Native 28x28 Tiny8 Diffusion Model on MNIST Digit 8 ---")
+    model, betas, alphas, alphas_bar = train_model(
+        epochs=args.epochs,
+        batch_size=args.batch_size,
+        lr=args.lr,
+        seed=args.seed,
+        data_dir=args.data_dir,
+    )
+
+    asm_path = Path(args.output)
+    generate_assembly(model, betas, alphas, alphas_bar, asm_path)
+    print(f"Done! Ready to run on Tiny8 CPU via 'uv run tiny8 {asm_path}'")
+
+
+if __name__ == "__main__":
+    main()
diff --git a/src/tiny8/__init__.py b/src/tiny8/__init__.py
index a97f341..354abdc 100644
--- a/src/tiny8/__init__.py
+++ b/src/tiny8/__init__.py
@@ -1,21 +1,29 @@
-"""tiny8 - a tiny AVR-like 8-bit CPU simulator package.
+"""A tiny AVR-like 8-bit CPU simulator package.
 
-Provides a compact CPU implementation, assembler and visualization helpers
-for experimentation and teaching.
+Provides a compact CPU implementation, assembler, C compiler, and
+interactive Textual CLI for experimentation and teaching.
 """
 
 from .assembler import AsmResult, assemble, assemble_file
-from .cli import run_cli
+from .compiler import (
+    compile_c,
+    compile_c_file,
+    compile_c_file_with_symbols,
+    compile_c_with_symbols,
+)
 from .cpu import CPU
+from .tui import run_cli
 from .utils import ProgressBar
-from .visualizer import Visualizer
 
 __all__ = [
     "CPU",
     "AsmResult",
     "assemble",
     "assemble_file",
-    "Visualizer",
+    "compile_c",
+    "compile_c_file",
+    "compile_c_with_symbols",
+    "compile_c_file_with_symbols",
     "run_cli",
     "ProgressBar",
 ]
diff --git a/src/tiny8/assembler.py b/src/tiny8/assembler.py
index 96917d9..c2c3d52 100644
--- a/src/tiny8/assembler.py
+++ b/src/tiny8/assembler.py
@@ -1,22 +1,17 @@
-"""Simple assembler for tiny8 - converts assembly text into program tuples.
+"""Assembler for tiny8 converting assembly text into program listings."""
 
-This module provides a tiny assembler that tokenizes and parses a simple
-assembly syntax and returns a list of instructions and a label mapping.
-"""
-
-import re
 from dataclasses import dataclass, field
 
 
 @dataclass
 class AsmResult:
-    """Result of assembling source code.
+    """Result of assembling assembly source code.
 
     Attributes:
-        program: List of instruction tuples (mnemonic, operands).
-        labels: Mapping from label names to program counter addresses.
-        pc_to_line: Mapping from program counter to original source line number.
-        source_lines: Original source text split into lines for display.
+        program: List of instruction tuples in (mnemonic, operands) format.
+        labels: Mapping of label names to program counter addresses.
+        pc_to_line: Mapping of program counter to source line numbers.
+        source_lines: Original source lines for display and debugging.
     """
 
     program: list[tuple[str, tuple]] = field(default_factory=list)
@@ -26,143 +21,106 @@ class AsmResult:
 
 
 def _parse_number(token: str) -> int:
-    """Parse a numeric assembly token and return its integer value.
-
-    The function accepts tokens used by a simple assembler and supports
-    several notations:
+    """Parse numeric literal token into integer.
 
-    - Optional immediate marker '#' prefixes the token and is ignored.
-    - Hexadecimal with a leading '$' (e.g. '$FF') or Python-style '0x'
-      (e.g. '0xFF').
-    - Binary with a leading '0b' (e.g. '0b1010').
-    - Decimal integers, including negative values (e.g. '42', '-7').
+    Supports hexadecimal ($FF, 0xFF), binary (0b1010), and decimal values,
+    with an optional leading '#' immediate prefix.
 
     Args:
-        token: The input token to parse.
+        token: Numeric token string to parse.
 
     Returns:
-        The integer value represented by the token.
+        Parsed integer value.
 
     Raises:
-        ValueError: If the token cannot be interpreted as a numeric literal
-            (e.g. when it is a label or otherwise non-numeric).
+        ValueError: If token cannot be parsed as a number.
     """
-    t = token.strip()
-    # strip immediate marker
-    if t.startswith("#"):
-        t = t[1:]
-    # $nn as hex
-    if t.startswith("$"):
+    t = token.strip().removeprefix("#")
+    if not t:
+        raise ValueError(f"Unable to parse numeric token: {token}")
+    c0 = t[0]
+    if c0 == "$":
         return int(t[1:], 16)
-    if t.startswith("0x"):
+    if t.startswith(("0x", "0X")):
         return int(t, 16)
-    if t.startswith("0b"):
+    if t.startswith(("0b", "0B")):
         return int(t, 2)
-    if t.isdigit() or (t.startswith("-") and t[1:].isdigit()):
+    if c0.isdigit() or (c0 == "-" and len(t) > 1 and t[1:].isdigit()):
         return int(t)
-    # otherwise return as-is (label)
     raise ValueError(f"Unable to parse numeric token: {token}")
 
 
 def parse_asm(text: str) -> AsmResult:
-    """Parse assembly source text into a program listing and a label table.
-
-    The function scans the given assembly text line-by-line and produces
-    an AsmResult containing the parsed program, labels, source line
-    mapping, and original source text.
+    """Parse assembly source text into an AsmResult structure.
 
     Args:
-        text: Assembly source code as a single string. May contain comments,
-            blank lines and labels.
+        text: Assembly source text.
 
     Returns:
-        AsmResult object containing program, labels, pc_to_line mapping,
-        and source_lines.
-
-    Note:
-        - Comments begin with ';' and extend to the end of the line.
-        - Labels may appear on a line by themselves or before an instruction
-          with the form "label: instr ...".
-        - Registers are encoded as ("reg", N) where N is the register number.
-        - Numeric operands are parsed using _parse_number; non-numeric tokens
-          are preserved as strings (symbols) for later resolution.
+        AsmResult containing parsed program, labels, and line mappings.
     """
     result = AsmResult()
     pc = 0
     lines = text.splitlines()
     result.source_lines = lines.copy()
-    for line_num, line in enumerate(lines):
-        line = line.split(";", 1)[0].strip()
+
+    for line_num, raw_line in enumerate(lines):
+        line = raw_line.split(";", 1)[0].strip()
         if not line:
             continue
         if ":" in line:
             left, right = line.split(":", 1)
-            lbl = left.strip()
-            result.labels[lbl] = pc
+            result.labels[left.strip()] = pc
             line = right.strip()
             if not line:
                 continue
-        parts = [p for p in re.split(r"[\s,]+", line) if p != ""]
+
+        parts = line.replace(",", " ").split()
         instr = parts[0].upper()
         ops = []
         for p in parts[1:]:
-            pl = p.lower()
-            if pl.startswith("r") and pl[1:].isdigit():
-                ops.append(("reg", int(pl[1:])))
+            if (p[0] == "r" or p[0] == "R") and len(p) > 1 and p[1:].isdigit():
+                ops.append(("reg", int(p[1:])))
+            elif p.upper() in ("X", "Y", "Z"):
+                reg_map = {"X": 26, "Y": 28, "Z": 30}
+                ops.append(("reg", reg_map[p.upper()]))
             else:
                 try:
-                    n = _parse_number(p)
-                    ops.append(n)
+                    ops.append(_parse_number(p))
                 except ValueError:
                     ops.append(p)
+
         result.program.append((instr, tuple(ops)))
         result.pc_to_line[pc] = line_num
         pc += 1
+
     return result
 
 
 def assemble(text: str) -> AsmResult:
-    """Parse assembly source text and return parsed instructions and label map.
+    """Assemble source text into program instructions and label mappings.
 
     Args:
-        text: Assembly source code as a single string. May contain
-            multiple lines, labels and comments.
+        text: Assembly source code string.
 
     Returns:
-        AsmResult object containing program, labels, source line mapping,
-        and original source text.
-
-    Raises:
-        Exception: Propagates parsing errors from the underlying parser.
-
-    Example:
-        >>> src = "start: MOV R1, 5\\nJMP start"
-        >>> result = assemble(src)
-        >>> result.labels
-        {'start': 0}
+        AsmResult containing parsed program, labels, and line mappings.
     """
     return parse_asm(text)
 
 
 def assemble_file(path: str) -> AsmResult:
-    """Assemble the contents of a source file.
+    """Assemble source file into program instructions and label mappings.
 
     Args:
-        path: Path to the source file to assemble.
+        path: Path to the assembly source file.
 
     Returns:
-        The result produced by calling assemble(source_text).
+        AsmResult containing parsed program, labels, and line mappings.
 
     Raises:
-        FileNotFoundError: If the specified file does not exist.
-        OSError: For other I/O related errors when opening or reading the file.
-        Exception: Any exception raised by assemble(...) will be propagated.
-
-    Note:
-        The file is opened in text mode and read entirely into memory.
-
-    Example:
-        >>> result = assemble_file("program.asm")
+        FileNotFoundError: If the source file does not exist.
+        OSError: If reading the file fails.
     """
-    with open(path, "r") as f:
+    with open(path, "r", encoding="utf-8") as f:
         return assemble(f.read())
diff --git a/src/tiny8/cli.py b/src/tiny8/cli.py
index 165a138..2bf411c 100644
--- a/src/tiny8/cli.py
+++ b/src/tiny8/cli.py
@@ -1,1190 +1,6 @@
-"""Terminal-based visualizer for tiny8 CPU step traces.
+"""Backward-compatibility wrapper forwarding to tiny8.tui."""
 
-Simplified and enhanced CLI with Vim-style controls, marks, search, and more.
-"""
+from .tui import *  # noqa: F401, F403
+from .tui import main, run_cli
 
-from __future__ import annotations
-
-import argparse
-import curses
-import time
-from collections.abc import Callable
-from dataclasses import dataclass, field
-from typing import Any
-
-# Key handler registry
-_key_handlers: dict[int | str, Callable] = {}
-
-
-def key_handler(*keys: int | str):
-    """Decorator to register a function as a handler for specific key(s).
-
-    Args:
-        *keys: One or more keys (as int or string) to bind to this handler.
-
-    Example:
-        @key_handler(ord('q'), 27)  # q and ESC
-        def quit_handler(state, ...):
-            return True  # Signal to exit
-    """
-
-    def decorator(func: Callable) -> Callable:
-        for key in keys:
-            _key_handlers[key] = func
-        return func
-
-    return decorator
-
-
-@dataclass
-class ViewState:
-    """State container for the CLI visualizer.
-
-    Attributes:
-        step_idx: Current step index in trace.
-        scroll_offset: Vertical scroll offset for memory view.
-        playing: Whether auto-play is active.
-        last_advance_time: Timestamp of last auto-advance.
-        delay: Delay between auto-advance steps in seconds.
-        show_all_regs: Show all 32 registers vs only changed.
-        show_all_mem: Show non-zero memory vs all memory.
-        command_mode: Whether in command input mode.
-        command_buffer: Current command being typed.
-        marks: Dictionary of named position marks.
-        status_msg: Current status message to display.
-        status_time: Timestamp when status message was set.
-    """
-
-    step_idx: int = 0
-    scroll_offset: int = 0
-    playing: bool = False
-    last_advance_time: float = 0.0
-    delay: float = 0.15
-    show_all_regs: bool = True
-    show_all_mem: bool = False
-    command_mode: bool = False
-    command_buffer: str = ""
-    marks: dict[str, int] = field(default_factory=dict)
-    status_msg: str = ""
-    status_time: float = 0.0
-
-
-@dataclass
-class KeyContext:
-    """Context passed to key handlers."""
-
-    state: ViewState
-    scr: Any
-    traces: list
-    cpu: Any
-    mem_addr_start: int
-    mem_addr_end: int
-    source_lines: list[str] | None
-    n: int  # total steps
-
-    def redraw(self) -> int:
-        """Redraw screen and return height."""
-        return draw_step(
-            self.scr,
-            self.state,
-            self.traces,
-            self.cpu,
-            self.mem_addr_start,
-            self.mem_addr_end,
-            self.source_lines,
-        )
-
-    def set_status(self, msg: str) -> None:
-        """Set status message."""
-        self.state.status_msg = msg
-        self.state.status_time = time.time()
-
-
-def format_byte(value: int) -> str:
-    """Format byte value as two-digit hex string.
-
-    Args:
-        value: Byte value to format (0-255).
-
-    Returns:
-        Two-character uppercase hex string.
-    """
-    return f"{value:02X}"
-
-
-def safe_add(
-    scr, y: int, x: int, text: str, attr: int = 0, max_x: int | None = None
-) -> None:
-    """Safely add text to screen, handling boundary conditions.
-
-    Args:
-        scr: Curses screen object.
-        y: Y coordinate (row).
-        x: X coordinate (column).
-        text: Text to display.
-        attr: Display attributes (e.g., curses.A_BOLD).
-        max_x: Maximum x coordinate, or None to use screen width.
-    """
-    if max_x is None:
-        _, max_x = scr.getmaxyx()
-    if y < 0 or y >= scr.getmaxyx()[0]:
-        return
-    # Truncate text to fit within screen bounds
-    text = text[: max_x - x - 1] if x < max_x else ""
-    try:
-        scr.addstr(y, x, text, attr)
-    except curses.error:
-        pass
-
-
-def draw_step(
-    scr,
-    state: ViewState,
-    traces: list,
-    cpu,
-    mem_start: int,
-    mem_end: int,
-    source_lines: list[str] | None = None,
-) -> int:
-    """Draw the current execution step to screen.
-
-    Displays header, SREG flags, assembly source code, registers, and memory for the current step.
-    Highlights changes from previous step and the currently executing source line.
-
-    Args:
-        scr: Curses screen object.
-        state: Current view state.
-        traces: List of execution trace entries.
-        cpu: CPU instance (unused, for consistency).
-        mem_start: Start address for memory display.
-        mem_end: End address for memory display.
-        source_lines: Optional list of original assembly source lines for display.
-
-    Returns:
-        Total number of lines drawn (for scroll calculations).
-    """
-    max_y, max_x = scr.getmaxyx()
-    scr.erase()
-
-    idx, mem_scroll, n = state.step_idx, state.scroll_offset, len(traces)
-    entry = traces[idx]
-    prev = traces[idx - 1] if idx > 0 else None
-
-    pc, sp = entry.get("pc", 0), entry.get("sp", 0)
-    instr, sreg = entry.get("instr", ""), entry.get("sreg", 0)
-    prev_sreg = prev.get("sreg", 0) if prev else 0
-    regs, prev_regs = entry.get("regs", []), prev.get("regs", []) if prev else []
-    mem, prev_mem = entry.get("mem", {}), prev.get("mem", {}) if prev else {}
-
-    line = 0
-
-    # Header (fixed) - White bold for high visibility
-    safe_add(
-        scr,
-        line,
-        0,
-        f"Step {idx}/{n - 1}  PC:0x{pc:04X}  SP:0x{sp:04X}  {instr}",
-        curses.color_pair(3) | curses.A_BOLD,
-        max_x,
-    )
-    line += 2
-
-    # Assembly Source Code (if available)
-    if source_lines:
-        source_line_num = entry.get("source_line", -1)
-        safe_add(
-            scr,
-            line,
-            0,
-            "Assembly Source:",
-            curses.color_pair(3) | curses.A_BOLD,
-            max_x,
-        )
-        line += 1
-
-        context_lines = 5
-        start_line = max(0, source_line_num - context_lines)
-        end_line = min(len(source_lines), source_line_num + context_lines + 1)
-
-        lines_before = source_line_num - start_line
-        lines_after = end_line - source_line_num - 1
-
-        padding_before = max(0, context_lines - lines_before)
-        padding_after = max(0, context_lines - lines_after)
-
-        for _ in range(padding_before):
-            safe_add(scr, line, 2, "", 0, max_x)
-            line += 1
-
-        for src_idx in range(start_line, end_line):
-            if src_idx < len(source_lines):
-                prefix = ">>>" if src_idx == source_line_num else "   "
-                src_text = source_lines[src_idx].rstrip()
-                display_text = f"{prefix} {src_idx + 1:3d}: {src_text}"
-                if src_idx == source_line_num:
-                    attr = curses.color_pair(1) | curses.A_BOLD
-                else:
-                    attr = 0
-                safe_add(scr, line, 2, display_text, attr, max_x)
-                line += 1
-
-        for _ in range(padding_after):
-            safe_add(scr, line, 2, "", 0, max_x)
-            line += 1
-
-        line += 1
-
-    flags = ["I", "T", "H", "S", "V", "N", "Z", "C"]
-    safe_add(scr, line, 0, "SREG: ", curses.color_pair(3) | curses.A_BOLD, max_x)
-    x = 6
-    for i, name in enumerate(flags):
-        bit_pos = 7 - i
-        bit, pbit = (sreg >> bit_pos) & 1, (prev_sreg >> bit_pos) & 1
-        if bit != pbit and prev:
-            # Changed flag: green background
-            attr = curses.color_pair(1) | curses.A_BOLD
-        elif bit == 1:
-            # Set flag: green text to indicate active
-            attr = curses.color_pair(2) | curses.A_BOLD
-        else:
-            # Cleared flag: normal text
-            attr = 0
-        safe_add(scr, line, x, f"{name}:{bit} ", attr, max_x)
-        x += 4
-    safe_add(scr, line, x + 2, f"0x{sreg:02X}", curses.color_pair(2), max_x)
-    line += 2
-
-    # Registers (fixed)
-    safe_add(
-        scr,
-        line,
-        0,
-        f"Registers ({'all' if state.show_all_regs else 'changed'}):",
-        curses.color_pair(3) | curses.A_BOLD,
-        max_x,
-    )
-    line += 1
-
-    if state.show_all_regs:
-        for row in range(2):
-            base = row * 16
-            safe_add(
-                scr,
-                line,
-                2,
-                f"R{base:02d}-{base + 15:02d}: ",
-                curses.color_pair(3),
-                max_x,
-            )
-            for col in range(16):
-                r = base + col
-                if r >= 32:
-                    break
-                val = regs[r] if r < len(regs) else 0
-                pval = prev_regs[r] if r < len(prev_regs) else 0
-                if val != pval and prev:
-                    # Changed register: green background
-                    attr = curses.color_pair(1) | curses.A_BOLD
-                elif val != 0:
-                    # Non-zero register: green text
-                    attr = curses.color_pair(2)
-                else:
-                    # Zero register: normal text
-                    attr = 0
-                safe_add(scr, line, 12 + col * 3, format_byte(val), attr, max_x)
-            line += 1
-    else:
-        changed = [
-            (
-                r,
-                prev_regs[r] if r < len(prev_regs) else 0,
-                regs[r] if r < len(regs) else 0,
-            )
-            for r in range(32)
-            if (regs[r] if r < len(regs) else 0)
-            != (prev_regs[r] if r < len(prev_regs) else 0)
-            and prev
-        ]
-        if changed:
-            for r, old, new in changed:
-                safe_add(
-                    scr,
-                    line,
-                    2,
-                    f"R{r:02d}: {format_byte(old)} → {format_byte(new)}",
-                    curses.color_pair(1) | curses.A_BOLD,
-                    max_x,
-                )
-                line += 1
-        else:
-            safe_add(scr, line, 2, "(no changes)", 0, max_x)
-            line += 1
-    line += 1
-
-    # Memory header (fixed)
-    safe_add(
-        scr,
-        line,
-        0,
-        f"Memory {hex(mem_start)}..{hex(mem_end)} ({'non-zero' if state.show_all_mem else 'all'}):",
-        curses.color_pair(3) | curses.A_BOLD,
-        max_x,
-    )
-    line += 1
-
-    # Calculate memory viewport
-    mem_start_line = line
-    mem_available_lines = max_y - line - 1  # Reserve 1 line for status
-
-    # Build memory lines
-    mem_lines = []
-    if state.show_all_mem:
-        nz = [(a, v) for a, v in mem.items() if mem_start <= a <= mem_end]
-        nz.sort()
-        if nz:
-            for addr, val in nz:
-                pval = prev_mem.get(addr, 0)
-                if val != pval and prev:
-                    # Changed memory: green background
-                    attr = curses.color_pair(1) | curses.A_BOLD
-                else:
-                    # Non-zero memory: green text
-                    attr = curses.color_pair(2)
-                ch = chr(val) if 32 <= val <= 126 else "."
-                mem_lines.append((f"0x{addr:04X}: {format_byte(val)}  '{ch}'", attr))
-        else:
-            mem_lines.append(("(all zero)", 0))
-    else:
-        for row in range((mem_end - mem_start + 16) // 16):
-            row_addr = mem_start + row * 16
-            if row_addr > mem_end:
-                break
-            line_text = f"0x{row_addr:04X}: "
-            ascii_parts = []
-            highlights = []
-            for col in range(16):
-                addr = row_addr + col
-                if addr > mem_end:
-                    break
-                val, pval = mem.get(addr, 0), prev_mem.get(addr, 0) if prev else 0
-                if val != pval and prev:
-                    highlights.append((12 + col * 3, format_byte(val)))
-                ascii_parts.append(chr(val) if 32 <= val <= 126 else ".")
-            mem_lines.append((line_text, 0, highlights, ascii_parts))
-
-    # Render visible memory lines
-    total_mem_lines = len(mem_lines)
-    for i in range(mem_available_lines):
-        mem_line_idx = mem_scroll + i
-        if mem_line_idx >= total_mem_lines:
-            break
-        scr_line = mem_start_line + i
-        if scr_line >= max_y - 1:
-            break
-
-        mem_line_data = mem_lines[mem_line_idx]
-        if state.show_all_mem:
-            text, attr = mem_line_data
-            safe_add(scr, scr_line, 2, text, attr, max_x)
-        else:
-            line_text, attr, highlights, ascii_parts = mem_line_data
-            safe_add(scr, scr_line, 2, line_text, curses.color_pair(3), max_x)
-            # Draw hex bytes
-            row_addr = mem_start + mem_line_idx * 16
-            for col in range(16):
-                addr = row_addr + col
-                if addr > mem_end:
-                    break
-                val = mem.get(addr, 0)
-                pval = prev_mem.get(addr, 0) if prev else 0
-                if val != pval and prev:
-                    # Changed memory: green background
-                    attr = curses.color_pair(1) | curses.A_BOLD
-                elif val != 0:
-                    # Non-zero memory: green text
-                    attr = curses.color_pair(2)
-                else:
-                    # Zero memory: normal text
-                    attr = 0
-                safe_add(scr, scr_line, 12 + col * 3, format_byte(val), attr, max_x)
-            # Draw ASCII
-            safe_add(scr, scr_line, 12 + 48, "  " + "".join(ascii_parts), 0, max_x)
-
-    # Status/Command line
-    status_line = max_y - 1
-    scr.move(status_line, 0)
-    scr.clrtoeol()
-
-    if state.command_mode:
-        # Command mode: white bold for visibility
-        safe_add(
-            scr,
-            status_line,
-            0,
-            f":{state.command_buffer}",
-            curses.color_pair(3) | curses.A_BOLD,
-            max_x,
-        )
-    else:
-        # Normal mode: show temporary status message or footer
-        if state.status_msg and time.time() - state.status_time < 0.5:
-            # Status messages in green
-            safe_add(
-                scr,
-                status_line,
-                0,
-                state.status_msg,
-                curses.color_pair(2) | curses.A_BOLD,
-                max_x,
-            )
-        else:
-            play = "[PLAY]" if state.playing else "[PAUSE]"
-            info = f" Speed:{state.delay:.2f}s"
-            if mem_scroll > 0:
-                info += f" MemScroll:{mem_scroll}/{max(0, total_mem_lines - mem_available_lines)}"
-            info += " | / for help | q to quit"
-            # Play/pause in green when active, white otherwise
-            play_attr = (
-                curses.color_pair(2) | curses.A_BOLD
-                if state.playing
-                else curses.color_pair(3) | curses.A_BOLD
-            )
-            safe_add(scr, status_line, 0, play, play_attr, max_x)
-            safe_add(scr, status_line, len(play), info, 0, max_x)
-
-    scr.refresh()
-    return total_mem_lines
-
-
-def show_help(scr) -> None:
-    """Display help screen with all available commands and controls.
-
-    Shows comprehensive documentation of keyboard shortcuts, commands,
-    and features. Waits for user keypress before returning.
-
-    Args:
-        scr: Curses screen object.
-    """
-    scr.clear()
-    help_text = [
-        "Tiny8 CLI - Help",
-        "",
-        "Navigation:  l/h: next/prev  w/b: ±10  0/$: first/last  j/k: scroll",
-        "Playback:    Space: play/pause  [/]: slower/faster",
-        "Display:     r: toggle regs  M: toggle mem  =: step info",
-        "Marks:       ma: set mark  'a: goto mark",
-        "",
-        "Commands (press : to enter):",
-        "  123       - Jump to step 123",
-        "  +50, -20  - Relative jump forward/backward",
-        "  /add      - Search forward for instruction containing 'add'",
-        "  ?ldi      - Search backward for instruction",
-        "  @100      - Jump to PC address (decimal or 0x hex)",
-        "  r10       - Find next change to register R10",
-        "  r10=42    - Find where R10 equals 42 (decimal or 0x hex)",
-        "  m100      - Find next change to memory address 100",
-        "  m100=0xFF - Find where memory[100] equals 0xFF",
-        "  fZ        - Find next change to flag Z (I,T,H,S,V,N,Z,C)",
-        "  fC=1      - Find where flag C equals 1",
-        "  h, help   - Show command help",
-        "",
-        "Other:       /: this help  q: quit",
-        "",
-        "Press any key...",
-    ]
-    for i, line in enumerate(help_text):
-        try:
-            scr.addstr(i, 2, line)
-        except Exception:
-            pass
-    scr.refresh()
-    scr.nodelay(False)
-    scr.getch()
-    scr.nodelay(True)
-
-
-def show_info(scr, entry: dict, idx: int) -> None:
-    """Display detailed information about a specific step.
-
-    Shows PC, SP, instruction, SREG, and all non-zero registers and memory
-    for the given step. Waits for user keypress before returning.
-
-    Args:
-        scr: Curses screen object.
-        entry: Trace entry dictionary containing step data.
-        idx: Step index number.
-    """
-    scr.clear()
-    lines = [
-        f"Step {idx} Details",
-        "",
-        f"PC: 0x{entry.get('pc', 0):04X}  SP: 0x{entry.get('sp', 0):04X}",
-        f"Instruction: {entry.get('instr', 'N/A')}",
-        f"SREG: 0x{entry.get('sreg', 0):02X}",
-        "",
-        "Non-zero registers:",
-    ]
-    for i, v in enumerate(entry.get("regs", [])):
-        if v:
-            lines.append(f"  R{i:02d} = 0x{v:02X} ({v})")
-    lines.append("")
-    lines.append("Non-zero memory:")
-    for a in sorted(entry.get("mem", {}).keys()):
-        v = entry["mem"][a]
-        ch = chr(v) if 32 <= v <= 126 else "."
-        lines.append(f"  0x{a:04X} = 0x{v:02X} ({v}) '{ch}'")
-    lines.append("")
-    lines.append("Press any key...")
-
-    for i, line in enumerate(lines):
-        try:
-            scr.addstr(i, 2, line)
-        except Exception:
-            pass
-    scr.refresh()
-    scr.nodelay(False)
-    scr.getch()
-    scr.nodelay(True)
-
-
-def run_command(state: ViewState, traces: list[dict]) -> str:
-    """Execute a command and return status message.
-
-    Handles all command types including navigation, search, and tracking.
-    Updates state.step_idx and state.scroll_offset as needed.
-
-    Args:
-        state: Current ViewState object to modify.
-        traces: List of trace entry dictionaries.
-
-    Returns:
-        Status message string describing the result.
-
-    Command Types:
-        - Numeric (123): Jump to step 123
-        - Relative (±50): Jump forward/backward 50 steps
-        - Forward search (/add): Find instruction containing "add"
-        - Backward search (?ldi): Search backward for "ldi"
-        - PC jump (@100): Jump to PC address 0x64
-        - Register track (r10): Find next change to R10
-        - Register search (r10=42): Find where R10 equals 42
-        - Memory track (m100): Find next change to memory[100]
-        - Memory search (m100=0xFF): Find where memory[100] equals 0xFF
-        - Flag track (fZ): Find next change to flag Z
-        - Flag search (fC=1): Find where flag C equals 1
-        - Help (h, help): Show command documentation
-    """
-    cmd = state.command_buffer.strip()
-    n = len(traces)
-
-    # Jump to absolute step number
-    if cmd.isdigit():
-        t = int(cmd)
-        if 0 <= t < n:
-            state.step_idx, state.scroll_offset = t, 0
-            return f"→ step {t}"
-        return f"Invalid: {t}"
-
-    # Relative jump (+50, -20)
-    if cmd and cmd[0] in "+-" and cmd[1:].isdigit():
-        new_idx = state.step_idx + int(cmd)
-        if 0 <= new_idx < n:
-            state.step_idx, state.scroll_offset = new_idx, 0
-            return f"→ step {new_idx}"
-        return f"Invalid: {new_idx}"
-
-    # Search forward for instruction (/add, /ldi r16)
-    if cmd.startswith("/"):
-        search = cmd[1:].lower().strip()
-        if not search:
-            return "Empty search"
-        for i in range(state.step_idx + 1, n):
-            instr = traces[i].get("instr", "").lower()
-            if search in instr:
-                state.step_idx, state.scroll_offset = i, 0
-                return f"Found at step {i}: {traces[i].get('instr', '')}"
-        return f"Not found: {search}"
-
-    # Search backward (?add, ?ldi r16)
-    if cmd.startswith("?"):
-        search = cmd[1:].lower().strip()
-        if not search:
-            return "Empty search"
-        for i in range(state.step_idx - 1, -1, -1):
-            instr = traces[i].get("instr", "").lower()
-            if search in instr:
-                state.step_idx, state.scroll_offset = i, 0
-                return f"Found at step {i}: {traces[i].get('instr', '')}"
-        return f"Not found: {search}"
-
-    # Jump to PC address (@100, @0x64)
-    if cmd.startswith("@"):
-        try:
-            addr_str = cmd[1:].strip()
-            target_pc = (
-                int(addr_str, 16) if addr_str.startswith("0x") else int(addr_str)
-            )
-            for i in range(n):
-                if traces[i].get("pc", -1) == target_pc:
-                    state.step_idx, state.scroll_offset = i, 0
-                    return f"→ step {i} (PC=0x{target_pc:04X})"
-            return f"PC 0x{target_pc:04X} not found"
-        except ValueError:
-            return f"Invalid address: {cmd}"
-
-    # Find register change (r10, r16=42)
-    if cmd.startswith("r") and len(cmd) >= 2:
-        try:
-            parts = cmd[1:].split("=")
-            reg_num = int(parts[0])
-            if not (0 <= reg_num <= 31):
-                return f"Invalid register: R{reg_num}"
-
-            if len(parts) == 1:
-                # Find next change to this register
-                current_val = (
-                    traces[state.step_idx].get("regs", [])[reg_num]
-                    if reg_num < len(traces[state.step_idx].get("regs", []))
-                    else 0
-                )
-                for i in range(state.step_idx + 1, n):
-                    regs = traces[i].get("regs", [])
-                    if reg_num < len(regs) and regs[reg_num] != current_val:
-                        state.step_idx, state.scroll_offset = i, 0
-                        return f"R{reg_num} changed at step {i}: 0x{regs[reg_num]:02X}"
-                return f"R{reg_num} doesn't change"
-            else:
-                # Find where register equals value
-                target_val = (
-                    int(parts[1], 16) if parts[1].startswith("0x") else int(parts[1])
-                )
-                for i in range(state.step_idx + 1, n):
-                    regs = traces[i].get("regs", [])
-                    if reg_num < len(regs) and regs[reg_num] == target_val:
-                        state.step_idx, state.scroll_offset = i, 0
-                        return f"R{reg_num}=0x{target_val:02X} at step {i}"
-                return f"R{reg_num}=0x{target_val:02X} not found"
-        except (ValueError, IndexError):
-            return f"Invalid: {cmd}"
-
-    # Memory search (m100, m0x64=42)
-    if cmd.startswith("m") and len(cmd) >= 2:
-        try:
-            parts = cmd[1:].split("=")
-            addr = int(parts[0], 16) if parts[0].startswith("0x") else int(parts[0])
-
-            if len(parts) == 1:
-                # Find next change to this memory address
-                current_val = traces[state.step_idx].get("mem", {}).get(addr, 0)
-                for i in range(state.step_idx + 1, n):
-                    mem = traces[i].get("mem", {})
-                    new_val = mem.get(addr, 0)
-                    if new_val != current_val:
-                        state.step_idx, state.scroll_offset = i, 0
-                        return f"Mem[0x{addr:04X}] changed at step {i}: 0x{new_val:02X}"
-                return f"Mem[0x{addr:04X}] doesn't change"
-            else:
-                # Find where memory equals value
-                target_val = (
-                    int(parts[1], 16) if parts[1].startswith("0x") else int(parts[1])
-                )
-                for i in range(state.step_idx + 1, n):
-                    mem = traces[i].get("mem", {})
-                    if mem.get(addr, 0) == target_val:
-                        state.step_idx, state.scroll_offset = i, 0
-                        return f"Mem[0x{addr:04X}]=0x{target_val:02X} at step {i}"
-                return f"Mem[0x{addr:04X}]=0x{target_val:02X} not found"
-        except (ValueError, IndexError):
-            return f"Invalid: {cmd}"
-
-    # Flag search (fZ, fC=1)
-    if cmd.startswith("f") and len(cmd) >= 2:
-        flag_map = {"I": 7, "T": 6, "H": 5, "S": 4, "V": 3, "N": 2, "Z": 1, "C": 0}
-        try:
-            parts = cmd[1:].split("=")
-            flag_name = parts[0].upper()
-            if flag_name not in flag_map:
-                return f"Invalid flag: {flag_name}"
-
-            bit_pos = flag_map[flag_name]
-
-            if len(parts) == 1:
-                # Find next change to this flag
-                current_sreg = traces[state.step_idx].get("sreg", 0)
-                current_bit = (current_sreg >> bit_pos) & 1
-                for i in range(state.step_idx + 1, n):
-                    sreg = traces[i].get("sreg", 0)
-                    bit = (sreg >> bit_pos) & 1
-                    if bit != current_bit:
-                        state.step_idx, state.scroll_offset = i, 0
-                        return f"Flag {flag_name} changed at step {i}: {bit}"
-                return f"Flag {flag_name} doesn't change"
-            else:
-                # Find where flag equals value
-                target_val = int(parts[1])
-                if target_val not in [0, 1]:
-                    return "Flag value must be 0 or 1"
-                for i in range(state.step_idx + 1, n):
-                    sreg = traces[i].get("sreg", 0)
-                    bit = (sreg >> bit_pos) & 1
-                    if bit == target_val:
-                        state.step_idx, state.scroll_offset = i, 0
-                        return f"Flag {flag_name}={target_val} at step {i}"
-                return f"Flag {flag_name}={target_val} not found"
-        except (ValueError, KeyError):
-            return f"Invalid: {cmd}"
-
-    # Help command
-    if cmd in ["h", "help"]:
-        return "Commands: NUM, ±NUM, /instr, ?instr, @addr, rN[=val], mADDR[=val], fFLAG[=val]"
-
-    return f"Unknown: {cmd}"
-
-
-# Key handler functions using decorator pattern
-@key_handler(ord("q"), 27)  # q and ESC
-def handle_quit(ctx: KeyContext) -> bool:
-    """Quit the visualizer."""
-    return True  # Signal to exit
-
-
-@key_handler(ord(" "))
-def handle_play_pause(ctx: KeyContext) -> int:
-    """Toggle play/pause."""
-    ctx.state.playing = not ctx.state.playing
-    if ctx.state.playing:
-        ctx.state.last_advance_time = time.time()
-    return ctx.redraw()
-
-
-@key_handler(ord("l"), curses.KEY_RIGHT)
-def handle_step_forward(ctx: KeyContext) -> int:
-    """Step forward."""
-    ctx.state.step_idx = min(ctx.n - 1, ctx.state.step_idx + 1)
-    ctx.state.scroll_offset = 0
-    return ctx.redraw()
-
-
-@key_handler(ord("h"), curses.KEY_LEFT)
-def handle_step_backward(ctx: KeyContext) -> int:
-    """Step backward."""
-    ctx.state.step_idx = max(0, ctx.state.step_idx - 1)
-    ctx.state.scroll_offset = 0
-    return ctx.redraw()
-
-
-@key_handler(ord("w"))
-def handle_jump_forward(ctx: KeyContext) -> int:
-    """Jump forward 10 steps."""
-    ctx.state.step_idx = min(ctx.n - 1, ctx.state.step_idx + 10)
-    ctx.state.scroll_offset = 0
-    return ctx.redraw()
-
-
-@key_handler(ord("b"))
-def handle_jump_backward(ctx: KeyContext) -> int:
-    """Jump backward 10 steps."""
-    ctx.state.step_idx = max(0, ctx.state.step_idx - 10)
-    ctx.state.scroll_offset = 0
-    return ctx.redraw()
-
-
-@key_handler(ord("0"))
-def handle_goto_first(ctx: KeyContext) -> int:
-    """Go to first step."""
-    ctx.state.step_idx = 0
-    ctx.state.scroll_offset = 0
-    return ctx.redraw()
-
-
-@key_handler(ord("$"))
-def handle_goto_last(ctx: KeyContext) -> int:
-    """Go to last step."""
-    ctx.state.step_idx = ctx.n - 1
-    ctx.state.scroll_offset = 0
-    return ctx.redraw()
-
-
-@key_handler(ord("r"))
-def handle_toggle_regs(ctx: KeyContext) -> int:
-    """Toggle showing all registers."""
-    ctx.state.show_all_regs = not ctx.state.show_all_regs
-    return ctx.redraw()
-
-
-@key_handler(ord("M"))
-def handle_toggle_mem(ctx: KeyContext) -> int:
-    """Toggle showing all memory."""
-    ctx.state.show_all_mem = not ctx.state.show_all_mem
-    return ctx.redraw()
-
-
-@key_handler(ord("["))
-def handle_slower(ctx: KeyContext) -> int:
-    """Decrease playback speed."""
-    ctx.state.delay = min(2.0, ctx.state.delay + 0.05)
-    ctx.set_status(f"Speed: {ctx.state.delay:.2f}s")
-    return ctx.redraw()
-
-
-@key_handler(ord("]"))
-def handle_faster(ctx: KeyContext) -> int:
-    """Increase playback speed."""
-    ctx.state.delay = max(0.05, ctx.state.delay - 0.05)
-    ctx.set_status(f"Speed: {ctx.state.delay:.2f}s")
-    return ctx.redraw()
-
-
-@key_handler(ord("="))
-def handle_show_info(ctx: KeyContext) -> int:
-    """Show detailed step information."""
-    show_info(ctx.scr, ctx.traces[ctx.state.step_idx], ctx.state.step_idx)
-    return ctx.redraw()
-
-
-@key_handler(ord("/"))
-def handle_show_help(ctx: KeyContext) -> int:
-    """Show help screen."""
-    show_help(ctx.scr)
-    return ctx.redraw()
-
-
-@key_handler(ord("j"))
-def handle_scroll_down(ctx: KeyContext, h: int) -> int:
-    """Scroll memory view down."""
-    ctx.state.scroll_offset = min(max(0, h - 1), ctx.state.scroll_offset + 1)
-    return ctx.redraw()
-
-
-@key_handler(ord("k"))
-def handle_scroll_up(ctx: KeyContext, h: int) -> int:
-    """Scroll memory view up."""
-    ctx.state.scroll_offset = max(0, ctx.state.scroll_offset - 1)
-    return ctx.redraw()
-
-
-def run_cli(
-    cpu,
-    mem_addr_start: int = 0,
-    mem_addr_end: int = 31,
-    delay: float = 0.15,
-    source_lines: list[str] | None = None,
-) -> None:
-    """Run interactive CLI visualizer in terminal.
-
-    Displays CPU state, registers, memory, and assembly source in a curses-based interface
-    with keyboard navigation and playback controls.
-
-    Args:
-        cpu: CPU instance with step_trace attribute containing execution history.
-        mem_addr_start: Starting memory address to display (default: 0).
-        mem_addr_end: Ending memory address to display (default: 31).
-        delay: Initial playback delay in seconds (default: 0.15).
-        source_lines: Optional list of original assembly source lines for display.
-
-    Raises:
-        RuntimeError: If cpu.step_trace is empty or missing.
-    """
-    traces = getattr(cpu, "step_trace", None)
-    if not traces:
-        raise RuntimeError("cpu.step_trace empty")
-
-    n = len(traces)
-
-    def main(scr):
-        curses.curs_set(0)
-        scr.nodelay(True)
-
-        # Initialize color pairs for usability-focused design
-        curses.start_color()
-        curses.use_default_colors()
-        curses.init_pair(
-            1, curses.COLOR_BLACK, curses.COLOR_GREEN
-        )  # Black on green (highlights)
-        curses.init_pair(2, curses.COLOR_GREEN, -1)  # Green text (active/positive)
-        curses.init_pair(3, curses.COLOR_WHITE, -1)  # White text (important info)
-
-        state = ViewState(delay=delay)
-        ctx = KeyContext(
-            state=state,
-            scr=scr,
-            traces=traces,
-            cpu=cpu,
-            mem_addr_start=mem_addr_start,
-            mem_addr_end=mem_addr_end,
-            source_lines=source_lines,
-            n=n,
-        )
-        h = ctx.redraw()
-
-        while True:
-            ch = scr.getch()
-
-            if ch == curses.KEY_RESIZE:
-                h = ctx.redraw()
-                continue
-
-            if ch != -1:
-                # Handle command mode
-                if state.command_mode:
-                    if ch == 27:
-                        state.command_mode, state.command_buffer = False, ""
-                        h = ctx.redraw()
-                    elif ch in (curses.KEY_ENTER, 10, 13):
-                        state.status_msg = run_command(state, traces)
-                        state.status_time = time.time()
-                        state.command_mode, state.command_buffer = False, ""
-                        h = ctx.redraw()
-                    elif ch in (curses.KEY_BACKSPACE, 127, 8):
-                        state.command_buffer = state.command_buffer[:-1]
-                        my, mx = scr.getmaxyx()
-                        safe_add(
-                            scr, my - 1, 0, f":{state.command_buffer}" + " " * 20, 0, mx
-                        )
-                        scr.refresh()
-                    elif 32 <= ch <= 126:
-                        state.command_buffer += chr(ch)
-                        my, mx = scr.getmaxyx()
-                        safe_add(scr, my - 1, 0, f":{state.command_buffer}", 0, mx)
-                        scr.refresh()
-                    continue
-
-                # Handle : for command mode
-                if ch == ord(":"):
-                    state.command_mode, state.command_buffer, state.playing = (
-                        True,
-                        "",
-                        False,
-                    )
-                    h = ctx.redraw()
-                    continue
-
-                # Handle marks (m and ')
-                if ch == ord("m"):
-                    scr.nodelay(False)
-                    mc = scr.getch()
-                    scr.nodelay(True)
-                    if 97 <= mc <= 122:
-                        mn = chr(mc)
-                        state.marks[mn] = state.step_idx
-                        ctx.set_status(f"Mark '{mn}' set")
-                        h = ctx.redraw()
-                    continue
-
-                if ch == ord("'"):
-                    scr.nodelay(False)
-                    mc = scr.getch()
-                    scr.nodelay(True)
-                    if 97 <= mc <= 122:
-                        mn = chr(mc)
-                        if mn in state.marks:
-                            state.step_idx, state.scroll_offset = state.marks[mn], 0
-                            ctx.set_status(f"→ mark '{mn}'")
-                        else:
-                            ctx.set_status(f"Mark '{mn}' not set")
-                        h = ctx.redraw()
-                    continue
-
-                # Dispatch to registered key handlers
-                handler = _key_handlers.get(ch)
-                if handler:
-                    # Handle scroll handlers that need h parameter
-                    if ch in (ord("j"), ord("k")):
-                        result = handler(ctx, h)
-                    else:
-                        result = handler(ctx)
-
-                    if result is True:  # Quit signal
-                        break
-                    if isinstance(result, int):  # New height
-                        h = result
-
-            # Handle auto-play
-            if state.playing:
-                t = time.time()
-                if t - state.last_advance_time >= state.delay:
-                    if state.step_idx < n - 1:
-                        state.step_idx += 1
-                        h = ctx.redraw()
-                        state.last_advance_time = t
-                    else:
-                        state.playing = False
-                time.sleep(0.01)
-            else:
-                # Check if status message expired and needs redraw
-                if state.status_msg:
-                    elapsed = time.time() - state.status_time
-                    if elapsed >= 0.5:
-                        state.status_msg = ""
-                        h = ctx.redraw()
-                time.sleep(0.05)
-
-    curses.wrapper(main)
-
-
-def main() -> None:
-    """Entry point for CLI command-line interface.
-
-    Parses command-line arguments, assembles the input file, runs the CPU,
-    and launches either CLI or animation mode visualization.
-
-    The function supports two modes:
-    - CLI mode: Interactive terminal-based step-through debugger
-    - Animation mode: Generate video/GIF visualization of execution
-
-    Command-line arguments are organized into groups for better clarity:
-    - Execution options: Control CPU behavior (max-steps)
-    - Memory display: Configure memory address range (supports hex notation)
-    - CLI mode: Interactive playback settings
-    - Animation mode: Video generation parameters
-    """
-    from tiny8 import CPU, __version__, assemble_file
-
-    parser = argparse.ArgumentParser(
-        prog="tiny8",
-        description="Tiny8 8-bit CPU simulator with interactive CLI and visualization",
-        formatter_class=argparse.RawDescriptionHelpFormatter,
-        epilog="""
-Examples:
-  %(prog)s program.asm                          # Run in interactive CLI mode
-  %(prog)s program.asm -m ani -o output.mp4     # Generate animation video
-  %(prog)s program.asm --mem-start 0x100 --mem-end 0x11F  # Custom memory range
-  %(prog)s program.asm -d 0.5                   # Slower playback (0.5s per step)
-
-Interactive CLI Controls:
-  l/h or arrows  - Navigate forward/backward
-  w/b            - Jump ±10 steps
-  0/$            - Jump to first/last step
-  j/k            - Scroll memory view
-  Space          - Play/pause execution
-  [/]            - Adjust playback speed
-  r              - Toggle register display
-  M              - Toggle memory display mode
-  :123           - Jump to step 123
-  /add           - Search forward for instruction
-  q              - Quit
-        """,
-    )
-
-    # Version
-    parser.add_argument(
-        "--version",
-        "-v",
-        action="version",
-        version=f"%(prog)s {__version__}",
-    )
-
-    # Required arguments
-    parser.add_argument(
-        "asm_file",
-        metavar="FILE",
-        help="path to Tiny8 assembly file to execute",
-    )
-
-    # Mode selection
-    parser.add_argument(
-        "--mode",
-        "-m",
-        choices=["cli", "ani"],
-        default="cli",
-        help="visualization mode: 'cli' for interactive terminal (default), 'ani' for animation video",
-    )
-
-    # Execution options
-    exec_group = parser.add_argument_group("execution options")
-    exec_group.add_argument(
-        "--max-steps",
-        type=int,
-        default=15000,
-        metavar="N",
-        help="maximum number of CPU steps to execute (default: 15000)",
-    )
-
-    # Memory display options
-    mem_group = parser.add_argument_group("memory display options")
-    mem_group.add_argument(
-        "--mem-start",
-        "-ms",
-        type=lambda x: int(x, 0),  # Support 0x hex notation
-        default=0x00,
-        metavar="ADDR",
-        help="starting memory address to display (decimal or 0xHEX, default: 0x00)",
-    )
-    mem_group.add_argument(
-        "--mem-end",
-        "-me",
-        type=lambda x: int(x, 0),  # Support 0x hex notation
-        default=0xFF,
-        metavar="ADDR",
-        help="ending memory address to display (decimal or 0xHEX, default: 0xFF)",
-    )
-
-    # CLI mode options
-    cli_group = parser.add_argument_group("CLI mode options")
-    cli_group.add_argument(
-        "--delay",
-        "-d",
-        type=float,
-        default=0.15,
-        metavar="SEC",
-        help="initial playback delay between steps in seconds (default: 0.15)",
-    )
-
-    # Animation mode options
-    ani_group = parser.add_argument_group("animation mode options")
-    ani_group.add_argument(
-        "--interval",
-        "-i",
-        type=int,
-        default=1,
-        metavar="MS",
-        help="animation update interval in milliseconds (default: 1)",
-    )
-    ani_group.add_argument(
-        "--fps",
-        "-f",
-        type=int,
-        default=60,
-        metavar="FPS",
-        help="frames per second for animation output (default: 60)",
-    )
-    ani_group.add_argument(
-        "--plot-every",
-        "-pe",
-        type=int,
-        default=100,
-        metavar="N",
-        help="update plot every N steps for performance (default: 100)",
-    )
-    ani_group.add_argument(
-        "--output",
-        "-o",
-        metavar="FILE",
-        help="output filename for animation (e.g., output.mp4, output.gif)",
-    )
-
-    args = parser.parse_args()
-
-    asm = assemble_file(args.asm_file)
-    cpu = CPU()
-    cpu.load_program(asm)
-    cpu.run(max_steps=args.max_steps)
-
-    if args.mode == "cli":
-        run_cli(cpu, args.mem_start, args.mem_end, args.delay, asm.source_lines)
-    elif args.mode == "ani":
-        from tiny8 import Visualizer
-
-        viz = Visualizer(cpu)
-        viz.animate_execution(
-            interval=args.interval,
-            mem_addr_start=args.mem_start,
-            mem_addr_end=args.mem_end,
-            plot_every=args.plot_every,
-            filename=args.output,
-            fps=args.fps,
-        )
-
-
-if __name__ == "__main__":
-    main()
+__all__ = ["main", "run_cli"]
diff --git a/src/tiny8/compiler.py b/src/tiny8/compiler.py
new file mode 100644
index 0000000..da4656b
--- /dev/null
+++ b/src/tiny8/compiler.py
@@ -0,0 +1,1341 @@
+"""Simple C compiler for Tiny8 converting a subset of C into Tiny8 assembly.
+
+Features:
+- Variable declarations and assignments (int/char)
+- Arithmetic (+, -, *, /, %), bitwise (&, |, ^, ~), logical (!), and relational (<, <=, >, >=, ==, !=)
+- Control structures: if / else, while, return
+- Functions with register-based parameter passing (R16..R19) and return value in R16
+- Hardware builtins: peek(addr), poke(addr, val), in(port), out(port, val)
+"""
+
+from __future__ import annotations
+
+import re
+from dataclasses import dataclass
+from typing import Any
+
+
+@dataclass
+class Token:
+    """Lexical token."""
+
+    type: str
+    value: str
+    line: int
+
+
+class Lexer:
+    """Tokenize C source code."""
+
+    TOKEN_SPEC = [
+        ("COMMENT_LINE", r"//.*"),
+        ("COMMENT_BLOCK", r"/\*[\s\S]*?\*/"),
+        ("NUMBER", r"0x[0-9a-fA-F]+|\d+"),
+        ("CHAR", r"'(\\.|[^\\'])'"),
+        ("STRING", r'"([^"\\]|\\.)*"'),
+        (
+            "KEYWORD",
+            r"\b(int|char|void|if|else|while|for|break|return|peek|poke|in|out|vram_set|vram_get|vram_clear|vram_puts)\b",
+        ),
+        ("ID", r"[a-zA-Z_]\w*"),
+        ("OP", r"==|!=|<=|>=|&&|\|\||[+\-*/%&|^=!<>]"),
+        ("PUNCT", r"[;,\(\)\{\}\[\]]"),
+        ("WS", r"\s+"),
+    ]
+
+    def __init__(self, source: str) -> None:
+        self.source = source
+        self.regex = re.compile(
+            "|".join(f"(?P<{name}>{pattern})" for name, pattern in self.TOKEN_SPEC)
+        )
+
+    def tokenize(self) -> list[Token]:
+        """Convert input source into tokens, ignoring whitespace and comments."""
+        tokens: list[Token] = []
+        line_num = 1
+        for match in self.regex.finditer(self.source):
+            kind = match.lastgroup
+            val = match.group()
+            if kind in ("WS", "COMMENT_LINE", "COMMENT_BLOCK"):
+                line_num += val.count("\n")
+                continue
+            tokens.append(Token(kind or "UNKNOWN", val, line_num))
+        return tokens
+
+
+class ASTNode:
+    """Base AST node."""
+
+
+@dataclass
+class Program(ASTNode):
+    """Program root containing functions and global declarations."""
+
+    functions: list[FunctionDef]
+    globals: list[ASTNode]
+
+
+@dataclass
+class VarDecl(ASTNode):
+    """Variable declaration."""
+
+    var_type: str
+    name: str
+    init_expr: ASTNode | None = None
+
+
+@dataclass
+class ArrayDecl(ASTNode):
+    """Array variable declaration."""
+
+    var_type: str
+    name: str
+    size: int
+    init_values: list[ASTNode] | None = None
+
+
+@dataclass
+class ArrayAccess(ASTNode):
+    """Array indexing expression: name[index]."""
+
+    name: str
+    index: ASTNode
+
+
+@dataclass
+class ArrayAssign(ASTNode):
+    """Array element assignment: name[index] = expr."""
+
+    name: str
+    index: ASTNode
+    expr: ASTNode
+
+
+@dataclass
+class FunctionDef(ASTNode):
+    """Function definition."""
+
+    return_type: str
+    name: str
+    params: list[tuple[str, str]]
+    body: Block
+
+
+@dataclass
+class Block(ASTNode):
+    """Block of statements."""
+
+    statements: list[ASTNode]
+
+
+@dataclass
+class Assign(ASTNode):
+    """Assignment statement."""
+
+    name: str
+    expr: ASTNode
+
+
+@dataclass
+class IfStmt(ASTNode):
+    """If-else statement."""
+
+    condition: ASTNode
+    then_branch: Block
+    else_branch: Block | None = None
+
+
+@dataclass
+class WhileStmt(ASTNode):
+    """While loop."""
+
+    condition: ASTNode
+    body: Block
+
+
+@dataclass
+class ForStmt(ASTNode):
+    """For loop."""
+
+    init: ASTNode | None
+    condition: ASTNode
+    post: ASTNode | None
+    body: Block
+
+
+@dataclass
+class BreakStmt(ASTNode):
+    """Break statement."""
+
+
+@dataclass
+class ReturnStmt(ASTNode):
+    """Return statement."""
+
+    expr: ASTNode | None = None
+
+
+@dataclass
+class ExprStmt(ASTNode):
+    """Expression statement."""
+
+    expr: ASTNode
+
+
+@dataclass
+class BinaryOp(ASTNode):
+    """Binary expression."""
+
+    op: str
+    left: ASTNode
+    right: ASTNode
+
+
+@dataclass
+class UnaryOp(ASTNode):
+    """Unary expression."""
+
+    op: str
+    operand: ASTNode
+
+
+@dataclass
+class Literal(ASTNode):
+    """Literal integer value."""
+
+    value: int
+
+
+@dataclass
+class StringLiteral(ASTNode):
+    """String literal value."""
+
+    value: str
+
+
+@dataclass
+class Var(ASTNode):
+    """Variable reference."""
+
+    name: str
+
+
+@dataclass
+class Call(ASTNode):
+    """Function call expression."""
+
+    name: str
+    args: list[ASTNode]
+
+
+def _fold_binary(op: str, left: ASTNode, right: ASTNode) -> ASTNode:
+    """Fold binary operations on literals at compile time."""
+    if isinstance(left, Literal) and isinstance(right, Literal):
+        lv = left.value
+        rv = right.value
+        if op == "+":
+            return Literal((lv + rv) & 0xFF)
+        if op == "-":
+            return Literal((lv - rv) & 0xFF)
+        if op == "*":
+            return Literal((lv * rv) & 0xFF)
+        if op == "/" and rv != 0:
+            return Literal((lv // rv) & 0xFF)
+        if op == "%" and rv != 0:
+            return Literal((lv % rv) & 0xFF)
+        if op == "&":
+            return Literal((lv & rv) & 0xFF)
+        if op == "|":
+            return Literal((lv | rv) & 0xFF)
+        if op == "^":
+            return Literal((lv ^ rv) & 0xFF)
+        if op == "==":
+            return Literal(1 if lv == rv else 0)
+        if op == "!=":
+            return Literal(1 if lv != rv else 0)
+        if op == "<":
+            return Literal(1 if lv < rv else 0)
+        if op == "<=":
+            return Literal(1 if lv <= rv else 0)
+        if op == ">":
+            return Literal(1 if lv > rv else 0)
+        if op == ">=":
+            return Literal(1 if lv >= rv else 0)
+        if op == "&&":
+            return Literal(1 if (lv != 0 and rv != 0) else 0)
+        if op == "||":
+            return Literal(1 if (lv != 0 or rv != 0) else 0)
+    return BinaryOp(op, left, right)
+
+
+def _fold_unary(op: str, operand: ASTNode) -> ASTNode:
+    """Fold unary operations on literals at compile time."""
+    if isinstance(operand, Literal):
+        val = operand.value
+        if op == "-":
+            return Literal((-val) & 0xFF)
+        if op == "~":
+            return Literal((~val) & 0xFF)
+        if op == "!":
+            return Literal(1 if val == 0 else 0)
+    return UnaryOp(op, operand)
+
+
+class Parser:
+    """Recursive descent parser."""
+
+    def __init__(self, tokens: list[Token]) -> None:
+        self.tokens = tokens
+        self.pos = 0
+
+    def peek(self) -> Token | None:
+        return self.tokens[self.pos] if self.pos < len(self.tokens) else None
+
+    def consume(self, expected_val: str | None = None) -> Token:
+        tok = self.peek()
+        if tok is None:
+            raise SyntaxError("Unexpected end of input")
+        if expected_val and tok.value != expected_val:
+            raise SyntaxError(
+                f"Line {tok.line}: Expected '{expected_val}', got '{tok.value}'"
+            )
+        self.pos += 1
+        return tok
+
+    def match(self, val: str) -> bool:
+        tok = self.peek()
+        if tok and tok.value == val:
+            self.pos += 1
+            return True
+        return False
+
+    def parse(self) -> Program:
+        functions: list[FunctionDef] = []
+        globals_list: list[ASTNode] = []
+
+        while self.peek():
+            type_tok = self.consume()
+            name_tok = self.consume()
+
+            if self.match("("):
+                params: list[tuple[str, str]] = []
+                if not self.match(")"):
+                    while True:
+                        ptype = self.consume().value
+                        pname = self.consume().value
+                        params.append((ptype, pname))
+                        if not self.match(","):
+                            self.consume(")")
+                            break
+                body = self.parse_block()
+                functions.append(
+                    FunctionDef(type_tok.value, name_tok.value, params, body)
+                )
+            elif self.match("["):
+                size = None
+                if self.peek() and self.peek().value != "]":
+                    size_tok = self.consume()
+                    size = (
+                        int(size_tok.value, 16)
+                        if size_tok.value.startswith("0x")
+                        else int(size_tok.value)
+                    )
+                self.consume("]")
+                init_values = None
+                if self.match("="):
+                    self.consume("{")
+                    init_values = []
+                    while self.peek() and self.peek().value != "}":
+                        init_values.append(self.parse_expr())
+                        if self.match(","):
+                            continue
+                        break
+                    self.consume("}")
+                self.consume(";")
+                if size is None:
+                    if init_values is not None:
+                        size = len(init_values)
+                    else:
+                        raise SyntaxError("Array size missing")
+                globals_list.append(
+                    ArrayDecl(type_tok.value, name_tok.value, size, init_values)
+                )
+            else:
+                init = None
+                if self.match("="):
+                    init = self.parse_expr()
+                self.consume(";")
+                globals_list.append(VarDecl(type_tok.value, name_tok.value, init))
+
+        return Program(functions, globals_list)
+
+    def parse_block(self) -> Block:
+        self.consume("{")
+        stmts: list[ASTNode] = []
+        while self.peek() and self.peek().value != "}":
+            stmts.append(self.parse_stmt())
+        self.consume("}")
+        return Block(stmts)
+
+    def parse_inline_stmt(self) -> ASTNode:
+        tok = self.peek()
+        if tok and tok.value in ("int", "char"):
+            vtype = self.consume().value
+            vname = self.consume().value
+            init = None
+            if self.match("="):
+                init = self.parse_expr()
+            self.consume(";")
+            return VarDecl(vtype, vname, init)
+        if tok and tok.type == "ID":
+            next_tok = (
+                self.tokens[self.pos + 1] if self.pos + 1 < len(self.tokens) else None
+            )
+            if next_tok and next_tok.value == "=":
+                name = self.consume().value
+                self.consume("=")
+                expr = self.parse_expr()
+                self.consume(";")
+                return Assign(name, expr)
+        expr = self.parse_expr()
+        self.consume(";")
+        return ExprStmt(expr)
+
+    def parse_inline_post(self) -> ASTNode:
+        tok = self.peek()
+        if tok and tok.type == "ID":
+            next_tok = (
+                self.tokens[self.pos + 1] if self.pos + 1 < len(self.tokens) else None
+            )
+            if next_tok and next_tok.value == "=":
+                name = self.consume().value
+                self.consume("=")
+                expr = self.parse_expr()
+                return Assign(name, expr)
+        return self.parse_expr()
+
+    def parse_stmt(self) -> ASTNode:
+        tok = self.peek()
+        if not tok:
+            raise SyntaxError("Unexpected end of statement")
+
+        if tok.value in ("int", "char"):
+            vtype = self.consume().value
+            vname = self.consume().value
+            if self.match("["):
+                size = None
+                if self.peek() and self.peek().value != "]":
+                    size_tok = self.consume()
+                    size = (
+                        int(size_tok.value, 16)
+                        if size_tok.value.startswith("0x")
+                        else int(size_tok.value)
+                    )
+                self.consume("]")
+                init_values = None
+                if self.match("="):
+                    self.consume("{")
+                    init_values = []
+                    while self.peek() and self.peek().value != "}":
+                        init_values.append(self.parse_expr())
+                        if self.match(","):
+                            continue
+                        break
+                    self.consume("}")
+                self.consume(";")
+                if size is None:
+                    if init_values is not None:
+                        size = len(init_values)
+                    else:
+                        raise SyntaxError("Array size missing")
+                return ArrayDecl(vtype, vname, size, init_values)
+            init = None
+            if self.match("="):
+                init = self.parse_expr()
+            self.consume(";")
+            return VarDecl(vtype, vname, init)
+
+        if tok.value == "break":
+            self.consume("break")
+            self.consume(";")
+            return BreakStmt()
+
+        if tok.value == "for":
+            self.consume("for")
+            self.consume("(")
+            init = None
+            if self.peek() and self.peek().value != ";":
+                init = self.parse_inline_stmt()
+            else:
+                self.consume(";")
+            cond = (
+                self.parse_expr()
+                if self.peek() and self.peek().value != ";"
+                else Literal(1)
+            )
+            self.consume(";")
+            post = None
+            if self.peek() and self.peek().value != ")":
+                post = self.parse_inline_post()
+            self.consume(")")
+            body = (
+                self.parse_block()
+                if self.peek() and self.peek().value == "{"
+                else Block([self.parse_stmt()])
+            )
+            return ForStmt(init, cond, post, body)
+
+        if tok.value == "if":
+            self.consume("if")
+            self.consume("(")
+            cond = self.parse_expr()
+            self.consume(")")
+            then_b = (
+                self.parse_block()
+                if self.peek() and self.peek().value == "{"
+                else Block([self.parse_stmt()])
+            )
+            else_b = None
+            if self.match("else"):
+                else_b = (
+                    self.parse_block()
+                    if self.peek() and self.peek().value == "{"
+                    else Block([self.parse_stmt()])
+                )
+            return IfStmt(cond, then_b, else_b)
+
+        if tok.value == "while":
+            self.consume("while")
+            self.consume("(")
+            cond = self.parse_expr()
+            self.consume(")")
+            body = (
+                self.parse_block()
+                if self.peek() and self.peek().value == "{"
+                else Block([self.parse_stmt()])
+            )
+            return WhileStmt(cond, body)
+
+        if tok.value == "return":
+            self.consume("return")
+            expr = None
+            if self.peek() and self.peek().value != ";":
+                expr = self.parse_expr()
+            self.consume(";")
+            return ReturnStmt(expr)
+
+        if tok.type == "ID":
+            next_tok = (
+                self.tokens[self.pos + 1] if self.pos + 1 < len(self.tokens) else None
+            )
+            if next_tok and next_tok.value == "[":
+                name = self.consume().value
+                self.consume("[")
+                idx_expr = self.parse_expr()
+                self.consume("]")
+                self.consume("=")
+                expr = self.parse_expr()
+                self.consume(";")
+                return ArrayAssign(name, idx_expr, expr)
+            if next_tok and next_tok.value == "=":
+                name = self.consume().value
+                self.consume("=")
+                expr = self.parse_expr()
+                self.consume(";")
+                return Assign(name, expr)
+
+        expr = self.parse_expr()
+        self.consume(";")
+        return ExprStmt(expr)
+
+    def parse_expr(self) -> ASTNode:
+        return self.parse_logic_or()
+
+    def parse_logic_or(self) -> ASTNode:
+        node = self.parse_logic_and()
+        while self.match("||"):
+            node = _fold_binary("||", node, self.parse_logic_and())
+        return node
+
+    def parse_logic_and(self) -> ASTNode:
+        node = self.parse_bitwise()
+        while self.match("&&"):
+            node = _fold_binary("&&", node, self.parse_bitwise())
+        return node
+
+    def parse_bitwise(self) -> ASTNode:
+        node = self.parse_equality()
+        while True:
+            if self.match("|"):
+                node = _fold_binary("|", node, self.parse_equality())
+            elif self.match("^"):
+                node = _fold_binary("^", node, self.parse_equality())
+            elif self.match("&"):
+                node = _fold_binary("&", node, self.parse_equality())
+            else:
+                break
+        return node
+
+    def parse_equality(self) -> ASTNode:
+        node = self.parse_relational()
+        while True:
+            if self.match("=="):
+                node = _fold_binary("==", node, self.parse_relational())
+            elif self.match("!="):
+                node = _fold_binary("!=", node, self.parse_relational())
+            else:
+                break
+        return node
+
+    def parse_relational(self) -> ASTNode:
+        node = self.parse_additive()
+        while True:
+            if self.match("<"):
+                node = _fold_binary("<", node, self.parse_additive())
+            elif self.match("<="):
+                node = _fold_binary("<=", node, self.parse_additive())
+            elif self.match(">"):
+                node = _fold_binary(">", node, self.parse_additive())
+            elif self.match(">="):
+                node = _fold_binary(">=", node, self.parse_additive())
+            else:
+                break
+        return node
+
+    def parse_additive(self) -> ASTNode:
+        node = self.parse_multiplicative()
+        while True:
+            if self.match("+"):
+                node = _fold_binary("+", node, self.parse_multiplicative())
+            elif self.match("-"):
+                node = _fold_binary("-", node, self.parse_multiplicative())
+            else:
+                break
+        return node
+
+    def parse_multiplicative(self) -> ASTNode:
+        node = self.parse_unary()
+        while True:
+            if self.match("*"):
+                node = _fold_binary("*", node, self.parse_unary())
+            elif self.match("/"):
+                node = _fold_binary("/", node, self.parse_unary())
+            elif self.match("%"):
+                node = _fold_binary("%", node, self.parse_unary())
+            else:
+                break
+        return node
+
+    def parse_unary(self) -> ASTNode:
+        tok = self.peek()
+        if tok and tok.value in ("-", "!", "~"):
+            op = self.consume().value
+            return _fold_unary(op, self.parse_unary())
+        return self.parse_primary()
+
+    def parse_primary(self) -> ASTNode:
+        tok = self.consume()
+        if tok.type == "NUMBER":
+            val = int(tok.value, 16) if tok.value.startswith("0x") else int(tok.value)
+            return Literal(val & 0xFF)
+        if tok.type == "CHAR":
+            raw = tok.value[1:-1]
+            if raw == r"\n":
+                val = 10
+            elif raw == r"\t":
+                val = 9
+            elif raw == r"\0":
+                val = 0
+            elif raw == r"\\":
+                val = ord("\\")
+            elif raw == r"\'":
+                val = ord("'")
+            elif len(raw) == 1:
+                val = ord(raw)
+            else:
+                val = ord(raw[0])
+            return Literal(val & 0xFF)
+        if tok.type == "STRING":
+            raw = tok.value[1:-1]
+            return StringLiteral(raw)
+        if tok.type in ("ID", "KEYWORD"):
+            if self.match("["):
+                idx_expr = self.parse_expr()
+                self.consume("]")
+                return ArrayAccess(tok.value, idx_expr)
+            if self.match("("):
+                args: list[ASTNode] = []
+                if not self.match(")"):
+                    while True:
+                        args.append(self.parse_expr())
+                        if not self.match(","):
+                            self.consume(")")
+                            break
+                return Call(tok.value, args)
+            return Var(tok.value)
+        if tok.value == "(":
+            expr = self.parse_expr()
+            self.consume(")")
+            return expr
+        raise SyntaxError(f"Line {tok.line}: Unexpected token '{tok.value}'")
+
+
+def optimize_assembly(lines: list[str]) -> list[str]:
+    """Perform peephole optimizations on generated assembly lines.
+
+    Optimizations include:
+    - Removing redundant self register moves (MOV Rx, Rx)
+    - Simplifying PUSH Rx followed immediately by POP Ry into MOV Ry, Rx (or eliminating if Rx == Ry)
+    - Removing redundant LD R16, R30 immediately after ST R30, R16
+    - Removing JMP <label> when the next line is <label>:
+    """
+    current_lines = list(lines)
+    for _ in range(5):
+        new_lines: list[str] = []
+        changed = False
+        i = 0
+        n = len(current_lines)
+        while i < n:
+            curr = current_lines[i]
+            s_curr = curr.strip()
+
+            # Rule 1: MOV Rx, Rx
+            if s_curr.upper().startswith("MOV "):
+                parts = s_curr.replace(",", " ").split()
+                if len(parts) == 3 and parts[1].upper() == parts[2].upper():
+                    changed = True
+                    i += 1
+                    continue
+
+            # Check 2-instruction peepholes
+            if i + 1 < n:
+                nxt = current_lines[i + 1]
+                s_nxt = nxt.strip()
+
+                # Rule 2: PUSH Rx followed by POP Ry
+                if s_curr.upper().startswith("PUSH ") and s_nxt.upper().startswith(
+                    "POP "
+                ):
+                    p_curr = s_curr.split()
+                    p_nxt = s_nxt.split()
+                    if len(p_curr) == 2 and len(p_nxt) == 2:
+                        rx = p_curr[1].upper()
+                        ry = p_nxt[1].upper()
+                        if rx == ry:
+                            changed = True
+                            i += 2
+                            continue
+                        new_lines.append(f"    MOV {ry}, {rx}")
+                        changed = True
+                        i += 2
+                        continue
+
+                # Rule 3: ST R30, R16 followed by LD R16, R30
+                if s_curr.upper() == "ST R30, R16" and s_nxt.upper() == "LD R16, R30":
+                    new_lines.append(curr)
+                    changed = True
+                    i += 2
+                    continue
+
+                # Rule 4: ST R30, R16 followed by redundant LDI R30, X; LD R16, R30
+                if (
+                    s_curr.upper() == "ST R30, R16"
+                    and i + 2 < n
+                    and current_lines[i + 2].strip().upper() == "LD R16, R30"
+                    and i > 0
+                    and current_lines[i - 1].strip().upper()
+                    == current_lines[i + 1].strip().upper()
+                ):
+                    new_lines.append(curr)
+                    changed = True
+                    i += 3
+                    continue
+
+                # Rule 5: Consecutive duplicate LDI
+                if s_curr.upper().startswith("LDI ") and s_nxt.upper().startswith(
+                    "LDI "
+                ):
+                    if s_curr.upper() == s_nxt.upper():
+                        changed = True
+                        i += 1
+                        continue
+
+                # Rule 6: JMP <label> followed by <label>:
+                if s_curr.upper().startswith("JMP "):
+                    parts = s_curr.split()
+                    if len(parts) == 2 and s_nxt == f"{parts[1]}:":
+                        new_lines.append(nxt)
+                        changed = True
+                        i += 2
+                        continue
+
+            new_lines.append(curr)
+            i += 1
+
+        current_lines = new_lines
+        if not changed:
+            break
+
+    return current_lines
+
+
+class CodeGenerator:
+    """Generate Tiny8 assembly from AST using register & stack model."""
+
+    PARAM_REGS = [16, 17, 18, 19]
+
+    def __init__(self) -> None:
+        self.asm: list[str] = []
+        self.label_counter = 0
+        self.var_addresses: dict[str, int] = {}
+        self.symbols: dict[str, dict[str, Any]] = {}
+        self.next_ram = 0x60
+        self.current_func = ""
+        self.loop_end_stack: list[str] = []
+
+    def new_label(self, prefix: str = "L") -> str:
+        self.label_counter += 1
+        return f"{prefix}_{self.label_counter}"
+
+    def emit(self, instr: str) -> None:
+        self.asm.append(f"    {instr}")
+
+    def emit_label(self, label: str) -> None:
+        self.asm.append(f"{label}:")
+
+    def allocate_var(self, name: str, var_type: str = "int") -> int:
+        if name not in self.var_addresses:
+            if 0x0200 <= self.next_ram <= 0x05FF:
+                self.next_ram = 0x0600
+            self.var_addresses[name] = self.next_ram
+            self.symbols[name] = {
+                "addr": self.next_ram,
+                "type": var_type,
+                "func": self.current_func,
+            }
+            self.next_ram += 1
+        return self.var_addresses[name]
+
+    def allocate_array(self, name: str, size: int, var_type: str = "int") -> int:
+        if name not in self.var_addresses:
+            if self.next_ram < 0x0600 and (self.next_ram + size) > 0x0200:
+                self.next_ram = 0x0600
+            self.var_addresses[name] = self.next_ram
+            self.symbols[name] = {
+                "addr": self.next_ram,
+                "type": f"{var_type}[{size}]",
+                "func": self.current_func,
+            }
+            self.next_ram += size
+        return self.var_addresses[name]
+
+    def generate(self, program: Program, optimize: bool = True) -> str:
+        self.asm = []
+        self.label_counter = 0
+        self.var_addresses = {}
+        self.symbols = {}
+        self.next_ram = 0x60
+        self.loop_end_stack = []
+
+        for g in program.globals:
+            if isinstance(g, ArrayDecl):
+                addr = self.allocate_array(g.name, g.size, g.var_type)
+                if g.init_values:
+                    self.emit(f"LDI R30, {addr & 0xFF}")
+                    if addr >= 256:
+                        self.emit(f"LDI R31, {addr >> 8}")
+                    for i, expr in enumerate(g.init_values):
+                        self.gen_expr(expr)
+                        self.emit("ST R30, R16")
+                        if i < len(g.init_values) - 1:
+                            self.emit("ADIW R30, 1")
+                    if (addr + len(g.init_values)) >= 256:
+                        self.emit("LDI R31, 0")
+            elif isinstance(g, VarDecl):
+                addr = self.allocate_var(g.name, g.var_type)
+                if g.init_expr:
+                    self.gen_expr(g.init_expr)
+                    self.emit(f"LDI R30, {addr & 0xFF}")
+                    if addr >= 256:
+                        self.emit(f"LDI R31, {addr >> 8}")
+                    self.emit("ST R30, R16")
+                    if addr >= 256:
+                        self.emit("LDI R31, 0")
+
+        self.emit("JMP main")
+
+        for f in program.functions:
+            self.gen_function(f)
+
+        if optimize:
+            self.asm = optimize_assembly(self.asm)
+
+        return "\n".join(self.asm)
+
+    def gen_function(self, func: FunctionDef) -> None:
+        self.current_func = func.name
+        self.emit_label(func.name)
+
+        for i, (ptype, pname) in enumerate(func.params):
+            addr = self.allocate_var(pname, ptype)
+            reg = self.PARAM_REGS[i]
+            self.emit(f"LDI R30, {addr & 0xFF}")
+            if addr >= 256:
+                self.emit(f"LDI R31, {addr >> 8}")
+            self.emit(f"ST R30, R{reg}")
+            if addr >= 256:
+                self.emit("LDI R31, 0")
+
+        for stmt in func.body.statements:
+            self.gen_stmt(stmt)
+
+        if func.name == "main":
+            self.emit("halt: JMP halt")
+        else:
+            self.emit("RET")
+
+    def gen_stmt(self, stmt: ASTNode) -> None:
+        if isinstance(stmt, ArrayDecl):
+            addr = self.allocate_array(stmt.name, stmt.size, stmt.var_type)
+            if stmt.init_values:
+                for i, expr in enumerate(stmt.init_values):
+                    self.gen_expr(expr)
+                    elem_addr = addr + i
+                    self.emit(f"LDI R30, {elem_addr & 0xFF}")
+                    if elem_addr >= 256:
+                        self.emit(f"LDI R31, {elem_addr >> 8}")
+                    self.emit("ST R30, R16")
+                    if elem_addr >= 256:
+                        self.emit("LDI R31, 0")
+
+        elif isinstance(stmt, VarDecl):
+            addr = self.allocate_var(stmt.name, stmt.var_type)
+            if stmt.init_expr:
+                self.gen_expr(stmt.init_expr)
+                self.emit(f"LDI R30, {addr & 0xFF}")
+                if addr >= 256:
+                    self.emit(f"LDI R31, {addr >> 8}")
+                self.emit("ST R30, R16")
+                if addr >= 256:
+                    self.emit("LDI R31, 0")
+
+        elif isinstance(stmt, ArrayAssign):
+            base_addr = self.allocate_var(stmt.name)
+            self.gen_expr(stmt.index)
+            self.emit(f"LDI R30, {base_addr & 0xFF}")
+            self.emit(f"LDI R31, {base_addr >> 8}")
+            self.emit("ADD R30, R16")
+            self.emit("LDI R17, 0")
+            self.emit("ADC R31, R17")
+            self.emit("PUSH R30")
+            self.emit("PUSH R31")
+            self.gen_expr(stmt.expr)
+            self.emit("MOV R17, R16")
+            self.emit("POP R31")
+            self.emit("POP R30")
+            self.emit("ST R30, R17")
+            if base_addr >= 256 or (base_addr + 256) >= 256:
+                self.emit("LDI R31, 0")
+
+        elif isinstance(stmt, Assign):
+            addr = self.allocate_var(stmt.name)
+            self.gen_expr(stmt.expr)
+            self.emit(f"LDI R30, {addr & 0xFF}")
+            if addr >= 256:
+                self.emit(f"LDI R31, {addr >> 8}")
+            self.emit("ST R30, R16")
+
+        elif isinstance(stmt, ForStmt):
+            if stmt.init:
+                self.gen_stmt(stmt.init)
+            lbl_start = self.new_label("for_start")
+            lbl_end = self.new_label("for_end")
+            self.loop_end_stack.append(lbl_end)
+            self.emit_label(lbl_start)
+            self.gen_expr(stmt.condition)
+            self.emit("CPI R16, 0")
+            self.emit(f"BREQ {lbl_end}")
+            self.gen_block(stmt.body)
+            if stmt.post:
+                self.gen_stmt(stmt.post)
+            self.emit(f"JMP {lbl_start}")
+            self.emit_label(lbl_end)
+            self.loop_end_stack.pop()
+
+        elif isinstance(stmt, BreakStmt):
+            if self.loop_end_stack:
+                self.emit(f"JMP {self.loop_end_stack[-1]}")
+
+        elif isinstance(stmt, IfStmt):
+            else_lbl = self.new_label("else")
+            end_lbl = self.new_label("endif")
+            self.gen_expr(stmt.condition)
+            self.emit("CPI R16, 0")
+            self.emit(f"BREQ {else_lbl if stmt.else_branch else end_lbl}")
+
+            for s in stmt.then_branch.statements:
+                self.gen_stmt(s)
+
+            if stmt.else_branch:
+                self.emit(f"JMP {end_lbl}")
+                self.emit_label(else_lbl)
+                for s in stmt.else_branch.statements:
+                    self.gen_stmt(s)
+
+            self.emit_label(end_lbl)
+
+        elif isinstance(stmt, WhileStmt):
+            loop_lbl = self.new_label("while_start")
+            end_lbl = self.new_label("while_end")
+            self.loop_end_stack.append(end_lbl)
+            self.emit_label(loop_lbl)
+            self.gen_expr(stmt.condition)
+            self.emit("CPI R16, 0")
+            self.emit(f"BREQ {end_lbl}")
+
+            for s in stmt.body.statements:
+                self.gen_stmt(s)
+
+            self.emit(f"JMP {loop_lbl}")
+            self.emit_label(end_lbl)
+            self.loop_end_stack.pop()
+
+        elif isinstance(stmt, ReturnStmt):
+            if stmt.expr:
+                self.gen_expr(stmt.expr)
+            if self.current_func == "main":
+                self.emit("halt_ret: JMP halt_ret")
+            else:
+                self.emit("RET")
+
+        elif isinstance(stmt, ExprStmt):
+            self.gen_expr(stmt.expr)
+
+    def gen_block(self, block: Block) -> None:
+        for s in block.statements:
+            self.gen_stmt(s)
+
+    def gen_expr(self, expr: ASTNode) -> None:
+        """Evaluate expression, leaving the 8-bit result in R16."""
+        if isinstance(expr, Literal):
+            self.emit(f"LDI R16, {expr.value}")
+
+        elif isinstance(expr, ArrayAccess):
+            base_addr = self.allocate_var(expr.name)
+            self.gen_expr(expr.index)
+            self.emit(f"LDI R30, {base_addr & 0xFF}")
+            self.emit(f"LDI R31, {base_addr >> 8}")
+            self.emit("ADD R30, R16")
+            self.emit("LDI R17, 0")
+            self.emit("ADC R31, R17")
+            self.emit("LD R16, R30")
+            if base_addr >= 256 or (base_addr + 256) >= 256:
+                self.emit("LDI R31, 0")
+
+        elif isinstance(expr, Var):
+            addr = self.allocate_var(expr.name)
+            self.emit(f"LDI R30, {addr & 0xFF}")
+            if addr >= 256:
+                self.emit(f"LDI R31, {addr >> 8}")
+            self.emit("LD R16, R30")
+            if addr >= 256:
+                self.emit("LDI R31, 0")
+
+        elif isinstance(expr, UnaryOp):
+            self.gen_expr(expr.operand)
+            if expr.op == "-":
+                self.emit("NEG R16")
+            elif expr.op == "~":
+                self.emit("COM R16")
+            elif expr.op == "!":
+                lbl_true = self.new_label("not_true")
+                lbl_end = self.new_label("not_end")
+                self.emit("CPI R16, 0")
+                self.emit(f"BREQ {lbl_true}")
+                self.emit("LDI R16, 0")
+                self.emit(f"JMP {lbl_end}")
+                self.emit_label(lbl_true)
+                self.emit("LDI R16, 1")
+                self.emit_label(lbl_end)
+
+        elif isinstance(expr, BinaryOp):
+            self.gen_expr(expr.left)
+            self.emit("PUSH R16")
+            self.gen_expr(expr.right)
+            self.emit("MOV R17, R16")
+            self.emit("POP R16")
+
+            if expr.op == "+":
+                self.emit("ADD R16, R17")
+            elif expr.op == "-":
+                self.emit("SUB R16, R17")
+            elif expr.op == "*":
+                self.emit("MUL R16, R17")
+                self.emit("MOV R16, R0")
+            elif expr.op == "/":
+                lbl_loop = self.new_label("div_loop")
+                lbl_end = self.new_label("div_end")
+                self.emit("CLR R18")
+                self.emit_label(lbl_loop)
+                self.emit("CP R16, R17")
+                self.emit(f"BRLO {lbl_end}")
+                self.emit("SUB R16, R17")
+                self.emit("INC R18")
+                self.emit(f"JMP {lbl_loop}")
+                self.emit_label(lbl_end)
+                self.emit("MOV R16, R18")
+            elif expr.op == "%":
+                lbl_loop = self.new_label("mod_loop")
+                lbl_end = self.new_label("mod_end")
+                self.emit_label(lbl_loop)
+                self.emit("CP R16, R17")
+                self.emit(f"BRLO {lbl_end}")
+                self.emit("SUB R16, R17")
+                self.emit(f"JMP {lbl_loop}")
+                self.emit_label(lbl_end)
+            elif expr.op == "&":
+                self.emit("AND R16, R17")
+            elif expr.op == "|":
+                self.emit("OR R16, R17")
+            elif expr.op == "^":
+                self.emit("EOR R16, R17")
+            elif expr.op == "&&":
+                lbl_false = self.new_label("and_false")
+                lbl_end = self.new_label("and_end")
+                self.emit("CPI R16, 0")
+                self.emit(f"BREQ {lbl_false}")
+                self.emit("CPI R17, 0")
+                self.emit(f"BREQ {lbl_false}")
+                self.emit("LDI R16, 1")
+                self.emit(f"JMP {lbl_end}")
+                self.emit_label(lbl_false)
+                self.emit("LDI R16, 0")
+                self.emit_label(lbl_end)
+            elif expr.op == "||":
+                lbl_true = self.new_label("or_true")
+                lbl_end = self.new_label("or_end")
+                self.emit("CPI R16, 0")
+                self.emit(f"BRNE {lbl_true}")
+                self.emit("CPI R17, 0")
+                self.emit(f"BRNE {lbl_true}")
+                self.emit("LDI R16, 0")
+                self.emit(f"JMP {lbl_end}")
+                self.emit_label(lbl_true)
+                self.emit("LDI R16, 1")
+                self.emit_label(lbl_end)
+            elif expr.op in ("==", "!=", "<", "<=", ">", ">="):
+                lbl_true = self.new_label("cmp_true")
+                lbl_end = self.new_label("cmp_end")
+                if expr.op in (">", ">="):
+                    self.emit("CP R17, R16")
+                else:
+                    self.emit("CP R16, R17")
+
+                if expr.op in ("==",):
+                    self.emit(f"BREQ {lbl_true}")
+                elif expr.op in ("!=",):
+                    self.emit(f"BRNE {lbl_true}")
+                elif expr.op in ("<", ">"):
+                    self.emit(f"BRLT {lbl_true}")
+                elif expr.op in ("<=", ">="):
+                    self.emit(f"BRLT {lbl_true}")
+                    self.emit(f"BREQ {lbl_true}")
+
+                self.emit("LDI R16, 0")
+                self.emit(f"JMP {lbl_end}")
+                self.emit_label(lbl_true)
+                self.emit("LDI R16, 1")
+                self.emit_label(lbl_end)
+
+        elif isinstance(expr, Call):
+            if expr.name == "peek":
+                self.gen_expr(expr.args[0])
+                self.emit("MOV R30, R16")
+                self.emit("LD R16, R30")
+            elif expr.name == "poke":
+                self.gen_expr(expr.args[0])
+                self.emit("PUSH R16")
+                self.gen_expr(expr.args[1])
+                self.emit("MOV R17, R16")
+                self.emit("POP R30")
+                self.emit("ST R30, R17")
+                self.emit("MOV R16, R17")
+            elif expr.name == "vram_set":
+                self.gen_expr(expr.args[1])
+                self.emit("MOV R30, R16")
+                self.emit("LDI R17, 32")
+                self.emit("MUL R30, R17")
+                self.emit("PUSH R0")
+                self.emit("PUSH R1")
+                self.emit("LDI R31, 0")
+                self.gen_expr(expr.args[0])
+                self.emit("MOV R17, R16")
+                self.emit("POP R31")
+                self.emit("POP R30")
+                self.emit("ADD R30, R17")
+                self.emit("LDI R17, 0")
+                self.emit("ADC R31, R17")
+                self.emit("LDI R17, 2")
+                self.emit("ADD R31, R17")
+                self.emit("PUSH R30")
+                self.emit("PUSH R31")
+                self.emit("LDI R31, 0")
+                self.gen_expr(expr.args[2])
+                self.emit("MOV R17, R16")
+                self.emit("POP R31")
+                self.emit("POP R30")
+                self.emit("ST R30, R17")
+                self.emit("LDI R31, 0")
+                self.emit("MOV R16, R17")
+            elif expr.name == "vram_get":
+                self.gen_expr(expr.args[1])
+                self.emit("MOV R30, R16")
+                self.emit("LDI R17, 32")
+                self.emit("MUL R30, R17")
+                self.emit("PUSH R0")
+                self.emit("PUSH R1")
+                self.emit("LDI R31, 0")
+                self.gen_expr(expr.args[0])
+                self.emit("MOV R17, R16")
+                self.emit("POP R31")
+                self.emit("POP R30")
+                self.emit("ADD R30, R17")
+                self.emit("LDI R17, 0")
+                self.emit("ADC R31, R17")
+                self.emit("LDI R17, 2")
+                self.emit("ADD R31, R17")
+                self.emit("LD R16, R30")
+                self.emit("LDI R31, 0")
+            elif expr.name == "vram_clear":
+                lbl_loop = self.new_label("vclr_loop")
+                self.emit("LDI R30, 0x00")
+                self.emit("LDI R31, 0x02")
+                self.emit("LDI R16, 32")
+                self.emit_label(lbl_loop)
+                self.emit("ST R30, R16")
+                self.emit("ADIW R30, 1")
+                self.emit("CPI R30, 0x00")
+                self.emit(f"BRNE {lbl_loop}")
+                self.emit("CPI R31, 0x06")
+                self.emit(f"BRNE {lbl_loop}")
+                self.emit("LDI R31, 0")
+            elif expr.name == "vram_puts":
+                str_val = (
+                    expr.args[2].value
+                    if isinstance(expr.args[2], StringLiteral)
+                    else ""
+                )
+                if str_val:
+                    self.gen_expr(expr.args[1])
+                    self.emit("MOV R30, R16")
+                    self.emit("LDI R17, 32")
+                    self.emit("MUL R30, R17")
+                    self.emit("PUSH R0")
+                    self.emit("PUSH R1")
+                    self.emit("LDI R31, 0")
+                    self.gen_expr(expr.args[0])
+                    self.emit("MOV R17, R16")
+                    self.emit("POP R31")
+                    self.emit("POP R30")
+                    self.emit("ADD R30, R17")
+                    self.emit("LDI R17, 0")
+                    self.emit("ADC R31, R17")
+                    self.emit("LDI R17, 2")
+                    self.emit("ADD R31, R17")
+                    for i, ch in enumerate(str_val):
+                        self.emit(f"LDI R17, {ord(ch)}")
+                        self.emit("ST R30, R17")
+                        if i < len(str_val) - 1:
+                            self.emit("ADIW R30, 1")
+                    self.emit("LDI R31, 0")
+            elif expr.name == "in":
+                self.gen_expr(expr.args[0])
+                self.emit("MOV R30, R16")
+                self.emit("IN R16, R30")
+            elif expr.name == "out":
+                self.gen_expr(expr.args[0])
+                self.emit("PUSH R16")
+                self.gen_expr(expr.args[1])
+                self.emit("MOV R17, R16")
+                self.emit("POP R30")
+                self.emit("OUT R30, R17")
+                self.emit("MOV R16, R17")
+            else:
+                for arg in expr.args:
+                    self.gen_expr(arg)
+                    self.emit("PUSH R16")
+                for i in range(len(expr.args) - 1, -1, -1):
+                    if i < len(self.PARAM_REGS):
+                        self.emit(f"POP R{self.PARAM_REGS[i]}")
+                    else:
+                        self.emit("POP R0")
+                self.emit(f"RCALL {expr.name}")
+
+
+def compile_c(source: str, optimize: bool = True) -> str:
+    """Compile C source code string into Tiny8 assembly.
+
+    Args:
+        source: C language source code text.
+        optimize: Whether to apply peephole optimization. Defaults to True.
+
+    Returns:
+        Generated Tiny8 assembly source string.
+    """
+    lexer = Lexer(source)
+    tokens = lexer.tokenize()
+    parser = Parser(tokens)
+    ast = parser.parse()
+    generator = CodeGenerator()
+    return generator.generate(ast, optimize=optimize)
+
+
+def compile_c_file(path: str, optimize: bool = True) -> str:
+    """Read and compile C source file into Tiny8 assembly.
+
+    Args:
+        path: Path to C source file.
+        optimize: Whether to apply peephole optimization. Defaults to True.
+
+    Returns:
+        Generated Tiny8 assembly source string.
+    """
+    with open(path, "r", encoding="utf-8") as f:
+        return compile_c(f.read(), optimize=optimize)
+
+
+def compile_c_with_symbols(
+    source: str, optimize: bool = True
+) -> tuple[str, dict[str, dict[str, Any]]]:
+    """Compile C source into Tiny8 assembly alongside variable symbol table.
+
+    Args:
+        source: C language source code text.
+        optimize: Whether to apply peephole optimization. Defaults to True.
+
+    Returns:
+        Tuple of (assembly_source_string, symbols_dict).
+    """
+    lexer = Lexer(source)
+    tokens = lexer.tokenize()
+    parser = Parser(tokens)
+    ast = parser.parse()
+    generator = CodeGenerator()
+    asm = generator.generate(ast, optimize=optimize)
+    return asm, generator.symbols
+
+
+def compile_c_file_with_symbols(
+    path: str, optimize: bool = True
+) -> tuple[str, dict[str, dict[str, Any]]]:
+    """Read and compile C source file into Tiny8 assembly with symbol table.
+
+    Args:
+        path: Path to C source file.
+        optimize: Whether to apply peephole optimization. Defaults to True.
+
+    Returns:
+        Tuple of (assembly_source_string, symbols_dict).
+    """
+    with open(path, "r", encoding="utf-8") as f:
+        return compile_c_with_symbols(f.read(), optimize=optimize)
diff --git a/src/tiny8/cpu.py b/src/tiny8/cpu.py
index 447752c..bc876da 100644
--- a/src/tiny8/cpu.py
+++ b/src/tiny8/cpu.py
@@ -1,12 +1,7 @@
-"""A simplified AVR-like 8-bit CPU simulator.
+"""Simplified AVR-like 8-bit CPU simulator."""
 
-This module provides a lightweight CPU model inspired by the ATmega family.
-The :class:`CPU` class is the primary export and implements a small, extensible instruction-dispatch model.
-The implementation favors readability over step-accurate emulation. Add
-instruction handlers by defining methods named ``op_<mnemonic>`` on ``CPU``.
-"""
-
-from typing import TYPE_CHECKING, Optional
+from collections import deque
+from typing import TYPE_CHECKING, Any
 
 if TYPE_CHECKING:
     from .assembler import AsmResult
@@ -14,68 +9,152 @@
 from .memory import Memory
 from .utils import ProgressBar
 
-# SREG flag bit positions and short descriptions.
-SREG_I = 7  # Global Interrupt Enable
-SREG_T = 6  # Bit copy storage (temporary)
-SREG_H = 5  # Half Carry
-SREG_S = 4  # Sign (N ^ V)
-SREG_V = 3  # Two's complement overflow
-SREG_N = 2  # Negative
-SREG_Z = 1  # Zero
-SREG_C = 0  # Carry
+SREG_I = 7
+SREG_T = 6
+SREG_H = 5
+SREG_S = 4
+SREG_V = 3
+SREG_N = 2
+SREG_Z = 1
+SREG_C = 0
+
+
+def _make_invoker(handler, decoded_ops: tuple):
+    """Create a specialized zero-overhead callable for instruction execution."""
+    if handler is None:
+        return None
+    n = len(decoded_ops)
+    if n == 2:
+        a, b = decoded_ops[0], decoded_ops[1]
+
+        def inv2() -> None:
+            handler(a, b)
+
+        return inv2
+    if n == 1:
+        a = decoded_ops[0]
+
+        def inv1() -> None:
+            handler(a)
+
+        return inv1
+    if n == 0:
+        return handler
+
+    def inv_n() -> None:
+        handler(*decoded_ops)
+
+    return inv_n
 
 
 class CPU:
-    """In-memory 8-bit AVR-like CPU model.
+    """Lightweight 8-bit AVR CPU emulator compliant with Microchip DS40002198A.
 
-    The CPU implements a compact instruction-dispatch model. Handlers are
-    methods named ``op_<mnemonic>`` and are invoked by :meth:`step` for the
-    currently-loaded program.
+    Args:
+        memory: Optional Memory instance. Defaults to a new Memory instance.
 
     Attributes:
-        regs (list[int]): 32 8-bit general purpose registers (R0..R31).
-        pc (int): Program counter (index into ``program``).
-        sp (int): Stack pointer (index into RAM in the associated
-            :class:`tiny8.memory.Memory`).
-        sreg (int): Status register bits stored in a single integer (I, T,
-            H, S, V, N, Z, C).
-        step_count (int): Instruction execution counter.
-        reg_trace (list[tuple[int, int, int]]): Per-step register change
-            trace entries of the form ``(step, reg, new_value)``.
-        mem_trace (list[tuple[int, int, int]]): Per-step memory change
-            trace entries of the form ``(step, addr, new_value)``.
-        step_trace (list[dict]): Full per-step snapshots useful for
-            visualization and debugging.
-
-    Note:
-        This implementation simplifies many AVR specifics (flag semantics,
-        exact step counts, IO mapping) in favor of clarity. Extend or
-        replace individual ``op_`` handlers to increase fidelity.
+        mem: Attached Memory instance.
+        regs: List of 32 8-bit general purpose registers (R0..R31).
+        pc: Current program counter address.
+        sp: Stack pointer pointing to current top of stack in RAM.
+        sreg: Status register integer containing I, T, H, S, V, N, Z, C flags.
+        step_count: Number of instructions executed so far.
+        interrupts: Mapping of interrupt vector addresses to enabled flags.
+        reg_trace: Change history of registers as (step, reg_idx, new_val) tuples.
+        mem_trace: Change history of RAM as (step, addr, new_val) tuples.
+        step_trace: Full per-step snapshots for tracing and visualization.
+        program: List of instruction tuples in (mnemonic, operands) format.
+        labels: Mapping of symbolic labels to program counter addresses.
+        pc_to_line: Mapping of program counter to source line numbers.
+        source_lines: Original assembly source text lines.
+        running: Flag indicating whether execution loop is active.
     """
 
-    def __init__(self, memory: Optional[Memory] = None):
+    __slots__ = (
+        "mem",
+        "max_trace_steps",
+        "max_trace_history",
+        "trace_enabled",
+        "regs",
+        "pc",
+        "sp",
+        "sreg",
+        "step_count",
+        "interrupts",
+        "reg_trace",
+        "mem_trace",
+        "step_trace",
+        "program",
+        "labels",
+        "pc_to_line",
+        "source_lines",
+        "running",
+        "_predecoded",
+    )
+
+    def __init__(
+        self,
+        memory: Memory | None = None,
+        max_trace_steps: int = 1000,
+        max_trace_history: int = 2000,
+        trace_enabled: bool = True,
+    ) -> None:
         self.mem = memory or Memory()
+        self.max_trace_steps = max_trace_steps
+        self.max_trace_history = max_trace_history
+        self.trace_enabled = trace_enabled
         self.regs: list[int] = [0] * 32
         self.pc: int = 0
         self.sp: int = self.mem.ram_size - 1
         self.sreg: int = 0
         self.step_count: int = 0
         self.interrupts: dict[int, bool] = {}
-        self.reg_trace: list[tuple[int, int, int]] = []
-        self.mem_trace: list[tuple[int, int, int]] = []
-        self.step_trace: list[dict] = []
+        self.reg_trace: deque[tuple[int, int, int]] = deque(maxlen=max_trace_history)
+        self.mem_trace: deque[tuple[int, int, int]] = deque(maxlen=max_trace_history)
+        self.step_trace: deque[dict] = deque(maxlen=max_trace_steps)
         self.program: list[tuple[str, tuple]] = []
         self.labels: dict[str, int] = {}
         self.pc_to_line: dict[int, int] = {}
         self.source_lines: list[str] = []
-        self.running = False
+        self.running: bool = False
+        self._predecoded: list[tuple] = []
+
+    def clear_traces(self) -> None:
+        """Clear execution traces and history to free memory."""
+        self.step_trace.clear()
+        self.reg_trace.clear()
+        self.mem_trace.clear()
+        self.mem.clear_changes()
+
+    def snapshot(self) -> dict[str, Any]:
+        """Capture complete CPU and memory execution state snapshot."""
+        return {
+            "step": self.step_count,
+            "pc": self.pc,
+            "sp": self.sp,
+            "sreg": self.sreg,
+            "regs": list(self.regs),
+            "mem": dict(self.mem.nonzero_ram),
+            "running": self.running,
+        }
+
+    def restore_snapshot(self, snap: dict[str, Any]) -> None:
+        """Restore CPU and memory execution state from a snapshot."""
+        self.step_count = snap["step"]
+        self.pc = snap["pc"]
+        self.sp = snap["sp"]
+        self.sreg = snap["sreg"]
+        self.regs = list(snap["regs"])
+        self.running = snap.get("running", True)
+        self.mem.restore_ram(snap["mem"])
 
     def set_flag(self, bit: int, value: bool) -> None:
-        """Set or clear a specific SREG flag bit.
+        """Set or clear a status register flag bit.
 
         Args:
-            bit: Integer bit index (0..7) representing the flag position.
-            value: True to set the bit, False to clear it.
+            bit: SREG bit index (0..7).
+            value: True to set flag, False to clear.
         """
         if value:
             self.sreg |= 1 << bit
@@ -83,104 +162,101 @@ def set_flag(self, bit: int, value: bool) -> None:
             self.sreg &= ~(1 << bit)
 
     def get_flag(self, bit: int) -> bool:
-        """Return the boolean value of a specific SREG flag bit.
+        """Return boolean status of a specific SREG bit.
 
         Args:
-            bit: Integer bit index (0..7).
+            bit: SREG bit index (0..7).
 
         Returns:
-            True if the bit is set, False otherwise.
+            True if bit is set, False otherwise.
         """
         return bool((self.sreg >> bit) & 1)
 
-    # --- AVR-like flag helpers (Z, C, N, V, S, H) ---
     def _set_flags_add(self, a: int, b: int, carry_in: int, result: int) -> None:
-        """Set flags for ADD/ADC (AVR semantics).
+        """Set SREG flags for addition operations (ADD, ADC).
 
         Args:
             a: First operand (0..255).
             b: Second operand (0..255).
-            carry_in: Carry input (0 or 1).
-            result: Integer sum result.
+            carry_in: Carry-in bit (0 or 1).
+            result: Sum result before 8-bit truncation.
         """
         r = result & 0xFF
         c = (result >> 8) & 1
         h = (((a & 0x0F) + (b & 0x0F) + carry_in) >> 4) & 1
         n = (r >> 7) & 1
-        v = 1 if (((~(a ^ b) & 0xFF) & (a ^ r) & 0x80) != 0) else 0
+        v = 1 if ((~(a ^ b) & (a ^ r)) & 0x80) else 0
         s = n ^ v
         z = 1 if r == 0 else 0
-
-        self.set_flag(SREG_C, bool(c))
-        self.set_flag(SREG_H, bool(h))
-        self.set_flag(SREG_N, bool(n))
-        self.set_flag(SREG_V, bool(v))
-        self.set_flag(SREG_S, bool(s))
-        self.set_flag(SREG_Z, bool(z))
+        self.sreg = (
+            (self.sreg & 0xC0)
+            | (h << 5)
+            | (s << 4)
+            | (v << 3)
+            | (n << 2)
+            | (z << 1)
+            | c
+        )
 
     def _set_flags_sub(self, a: int, b: int, borrow_in: int, result: int) -> None:
-        """Set flags for SUB/CP/CPI (AVR semantics).
+        """Set SREG flags for subtraction operations (SUB, SBC, CP, CPI).
 
         Args:
             a: Minuend (0..255).
             b: Subtrahend (0..255).
-            borrow_in: Borrow input (0 or 1).
-            result: Signed difference (a - b - borrow_in).
+            borrow_in: Borrow-in bit (0 or 1).
+            result: Difference result before 8-bit truncation.
         """
         r = result & 0xFF
         c = 1 if (a - b - borrow_in) < 0 else 0
         h = 1 if ((a & 0x0F) - (b & 0x0F) - borrow_in) < 0 else 0
         n = (r >> 7) & 1
-        v = 1 if ((((a ^ b) & (a ^ r)) & 0x80) != 0) else 0
+        v = 1 if (((a ^ b) & (a ^ r)) & 0x80) else 0
         s = n ^ v
         z = 1 if r == 0 else 0
-
-        self.set_flag(SREG_C, bool(c))
-        self.set_flag(SREG_H, bool(h))
-        self.set_flag(SREG_N, bool(n))
-        self.set_flag(SREG_V, bool(v))
-        self.set_flag(SREG_S, bool(s))
-        self.set_flag(SREG_Z, bool(z))
+        self.sreg = (
+            (self.sreg & 0xC0)
+            | (h << 5)
+            | (s << 4)
+            | (v << 3)
+            | (n << 2)
+            | (z << 1)
+            | c
+        )
 
     def _set_flags_logical(self, result: int) -> None:
-        """Set flags for logical operations (AND, OR, EOR) per AVR semantics.
+        """Set SREG flags for logical operations (AND, OR, EOR).
+
+        Status Register (SREG) per AVR Instruction Set Manual DS40002198A:
+            S: N ⊕ V (For signed tests)
+            V: 0 (Cleared)
+            N: R7 (Set if MSB of result is set; cleared otherwise)
+            Z: Set if result is $00; cleared otherwise
+            H, C, T, I: Unaffected (-)
 
         Args:
             result: Operation result.
-
-        Note:
-            Logical ops clear C and V, set N and Z, S = N ^ V, and clear H.
         """
         r = result & 0xFF
         n = (r >> 7) & 1
         z = 1 if r == 0 else 0
-        s = n  # v is 0, so s = n ^ 0 = n
-
-        self.set_flag(SREG_C, False)
-        self.set_flag(SREG_V, False)
-        self.set_flag(SREG_N, bool(n))
-        self.set_flag(SREG_S, bool(s))
-        self.set_flag(SREG_Z, bool(z))
-        self.set_flag(SREG_H, False)
+        self.sreg = (self.sreg & 0xE1) | (n << 4) | (n << 2) | (z << 1)
 
     def _set_flags_inc(self, old: int, new: int) -> None:
-        """Set flags for INC (affects V, N, Z, S). Does not affect C or H.
+        """Set SREG flags for increment operation (INC).
 
         Args:
-            old: Value before increment.
-            new: Value after increment.
+            old: Register value before increment.
+            new: Register value after increment.
         """
         n = (new >> 7) & 1
         v = 1 if old == 0x7F else 0
-        z = 1 if new == 0 else 0
         s = n ^ v
-        self.set_flag(SREG_N, bool(n))
-        self.set_flag(SREG_V, bool(v))
-        self.set_flag(SREG_S, bool(s))
-        self.set_flag(SREG_Z, bool(z))
+        z = 1 if new == 0 else 0
+        self.sreg = (self.sreg & 0xE1) | (s << 4) | (v << 3) | (n << 2) | (z << 1)
 
     def _set_flags_add16(self, a: int, b: int, carry_in: int, result: int) -> None:
-        """Set flags for 16-bit add (ADIW semantics approximation).
+        """Set SREG flags for 16-bit addition (ADIW).
 
         Args:
             a: First operand (0..0xFFFF).
@@ -194,277 +270,269 @@ def _set_flags_add16(self, a: int, b: int, carry_in: int, result: int) -> None:
         v = 1 if (((~(a ^ b) & 0xFFFF) & (a ^ r) & 0x8000) != 0) else 0
         s = n ^ v
         z = 1 if r == 0 else 0
-
-        self.set_flag(SREG_C, bool(c))
-        self.set_flag(SREG_N, bool(n))
-        self.set_flag(SREG_V, bool(v))
-        self.set_flag(SREG_S, bool(s))
-        self.set_flag(SREG_Z, bool(z))
-        self.set_flag(SREG_H, False)
+        self.sreg = (self.sreg & 0xE0) | (s << 4) | (v << 3) | (n << 2) | (z << 1) | c
 
     def _set_flags_sub16(self, a: int, b: int, borrow_in: int, result: int) -> None:
-        """Set flags for 16-bit subtraction (SBIW semantics approximation).
+        """Set SREG flags for 16-bit subtraction (SBIW).
 
         Args:
             a: Minuend (0..0xFFFF).
             b: Subtrahend (0..0xFFFF).
             borrow_in: Borrow input (0 or 1).
-            result: Integer difference a - b - borrow_in.
+            result: Integer difference.
         """
         r = result & 0xFFFF
         c = 1 if (a - b - borrow_in) < 0 else 0
         n = (r >> 15) & 1
-        v = 1 if ((((a ^ b) & (a ^ r)) & 0x8000) != 0) else 0
+        v = 1 if (((a ^ b) & (a ^ r)) & 0x8000) != 0 else 0
         s = n ^ v
         z = 1 if r == 0 else 0
-
-        self.set_flag(SREG_C, bool(c))
-        self.set_flag(SREG_N, bool(n))
-        self.set_flag(SREG_V, bool(v))
-        self.set_flag(SREG_S, bool(s))
-        self.set_flag(SREG_Z, bool(z))
-        self.set_flag(SREG_H, False)
+        self.sreg = (self.sreg & 0xE0) | (s << 4) | (v << 3) | (n << 2) | (z << 1) | c
 
     def _set_flags_dec(self, old: int, new: int) -> None:
-        """Set flags for DEC (affects V, N, Z, S). Does not affect C or H.
+        """Set SREG flags for decrement operation (DEC).
 
         Args:
-            old: Value before decrement.
-            new: Value after decrement.
+            old: Register value before decrement.
+            new: Register value after decrement.
         """
         n = (new >> 7) & 1
         v = 1 if old == 0x80 else 0
-        z = 1 if new == 0 else 0
         s = n ^ v
-        self.set_flag(SREG_N, bool(n))
-        self.set_flag(SREG_V, bool(v))
-        self.set_flag(SREG_S, bool(s))
-        self.set_flag(SREG_Z, bool(z))
+        z = 1 if new == 0 else 0
+        self.sreg = (self.sreg & 0xE1) | (s << 4) | (v << 3) | (n << 2) | (z << 1)
 
-    # Register access
     def read_reg(self, r: int) -> int:
-        """Return the 8-bit value from register ``r``.
+        """Return 8-bit value from register r.
 
         Args:
             r: Register index (0..31).
 
         Returns:
-            The 8-bit value (0..255) stored in the register.
+            8-bit unsigned integer value.
         """
-        return self.regs[r] & 0xFF
+        return self.regs[r]
 
     def write_reg(self, r: int, val: int) -> None:
-        """Write an 8-bit value to register ``r`` and record the change.
+        """Write 8-bit value to register r and trace changes.
 
         Args:
             r: Register index (0..31).
-            val: Value to write; will be truncated to 8 bits.
-
-        Note:
-            A trace entry is appended only when the register value actually
-            changes to avoid noisy traces.
+            val: Integer value to store (masked to 8-bit).
         """
         newv = val & 0xFF
-        if self.regs[r] != newv:
+        if self.trace_enabled:
+            if self.regs[r] != newv:
+                self.regs[r] = newv
+                self.reg_trace.append((self.step_count, r, newv))
+        else:
             self.regs[r] = newv
-            self.reg_trace.append((self.step_count, r, newv))
 
-    # Memory access wrappers
     def read_ram(self, addr: int) -> int:
-        """Read a byte from RAM at the given address.
+        """Read byte from RAM address.
 
         Args:
-            addr: RAM address to read.
+            addr: Memory address.
 
         Returns:
-            Byte value stored at ``addr`` (0..255).
+            Byte value stored at address.
         """
         return self.mem.read_ram(addr)
 
     def write_ram(self, addr: int, val: int) -> None:
-        """Write an 8-bit value to RAM at ``addr`` and record the trace.
+        """Write byte to RAM address and record memory trace.
 
         Args:
-            addr: RAM address to write.
-            val: Value to write; will be truncated to 8 bits.
-
-        Note:
-            The underlying :class:`Memory` object stores the value; a
-            ``(step, addr, val)`` tuple is appended to ``mem_trace`` for
-            visualizers/tests.
+            addr: Target RAM address.
+            val: Byte value to write.
         """
         self.mem.write_ram(addr, val, self.step_count)
-        self.mem_trace.append((self.step_count, addr, val & 0xFF))
+        if self.trace_enabled:
+            self.mem_trace.append((self.step_count, addr, val & 0xFF))
 
-    # Program loading
     def load_program(
         self,
         program: "list[tuple[str, tuple]] | AsmResult",
-        labels: Optional[dict[str, int]] = None,
-        pc_to_line: Optional[dict[int, int]] = None,
-        source_lines: Optional[list[str]] = None,
-    ):
-        """Load an assembled program into the CPU.
-
-        Args:
-            program: Either a list of ``(mnemonic, operands)`` tuples or an
-                AsmResult object. If AsmResult, other params are ignored.
-            labels: Mapping of label strings to instruction indices (ignored if
-                program is AsmResult).
-            pc_to_line: Optional mapping from PC to source line number for tracing
-                (ignored if program is AsmResult).
-            source_lines: Optional original assembly source lines for display
-                (ignored if program is AsmResult).
-
-        Note:
-            After loading the program, the program counter is reset to zero.
-        """
-        # Check if program is an AsmResult
+        labels: dict[str, int] | None = None,
+        pc_to_line: dict[int, int] | None = None,
+        source_lines: list[str] | None = None,
+    ) -> None:
+        """Load assembled program instructions into CPU.
+
+        Args:
+            program: AsmResult object or list of (mnemonic, operands) tuples.
+            labels: Label mapping if program is a raw list.
+            pc_to_line: PC to line mapping if program is a raw list.
+            source_lines: Source text lines if program is a raw list.
+        """
         if hasattr(program, "program") and hasattr(program, "labels"):
-            # It's an AsmResult
-            asm = program
-            self.program = asm.program
-            self.labels = asm.labels
-            self.pc_to_line = asm.pc_to_line
-            self.source_lines = asm.source_lines
+            self.program = program.program
+            self.labels = program.labels
+            self.pc_to_line = program.pc_to_line
+            self.source_lines = program.source_lines
         else:
-            # Legacy tuple-based format
             self.program = program
             self.labels = labels or {}
             self.pc_to_line = pc_to_line or {}
             self.source_lines = source_lines or []
         self.pc = 0
+        self._build_predecoded()
+
+    def _build_predecoded(self) -> None:
+        """Pre-decode program instructions for maximum execution throughput."""
+        self._predecoded = []
+        for instr, operands in self.program:
+            handler = getattr(self, f"op_{instr.lower()}", None)
+            decoded_ops = []
+            for o in operands:
+                if isinstance(o, tuple) and len(o) == 2 and o[0] == "reg":
+                    decoded_ops.append(int(o[1]))
+                else:
+                    decoded_ops.append(o)
+
+            def fmt_op(o) -> str:
+                if isinstance(o, tuple) and len(o) == 2 and o[0] == "reg":
+                    return f"R{o[1]}"
+                return str(o)
 
-    # Instruction execution
-    def step(self) -> bool:
-        """Execute a single instruction at the current program counter.
+            try:
+                ops_text = ", ".join(fmt_op(o) for o in operands)
+            except Exception:
+                ops_text = ""
+            instr_text = f"{instr.upper()} {ops_text}".strip()
 
-        Performs one fetch-decode-execute step. A pre-step snapshot of
-        registers and non-zero RAM is recorded, the instruction handler
-        (``op_<mnemonic>``) is invoked, and a post-step trace entry is
-        appended to ``step_trace``.
+            ops_tuple = tuple(decoded_ops)
+            invoker = _make_invoker(handler, ops_tuple)
+            self._predecoded.append((handler, ops_tuple, instr_text, invoker))
+
+    def step(self, record_trace: bool | None = None) -> bool:
+        """Execute next single instruction at current program counter.
+
+        Args:
+            record_trace: Optional override to enable or disable trace recording for this step.
 
         Returns:
-            True if an instruction was executed; False if the PC is out of
-            range and execution should stop.
-        """
+            True if instruction executed successfully, False if PC is out of range.
 
-        if self.pc < 0 or self.pc >= len(self.program):
+        Raises:
+            NotImplementedError: If instruction mnemonic has no handler.
+        """
+        if not (0 <= self.pc < len(self.program)):
             self.running = False
             return False
 
         pre_exec_pc = self.pc
-        instr, operands = self.program[self.pc]
-
-        # Build textual form of the instruction for tracing (uppercase mnemonic
-        # and register names like R0..R31). Operands decoded for display only.
-        def fmt_op(o):
-            if isinstance(o, tuple) and len(o) == 2 and o[0] == "reg":
-                return f"R{o[1]}"
-            return str(o)
+        if not self._predecoded or len(self._predecoded) != len(self.program):
+            self._build_predecoded()
 
-        try:
-            ops_text = ", ".join(fmt_op(o) for o in operands)
-        except Exception:
-            ops_text = ""
-        instr_text = f"{instr.upper()} {ops_text}".strip()
-
-        # record pre-step snapshot
-        regs_snapshot = list(self.regs)
-        # memory snapshot: capture all non-zero RAM addresses (helps visualization of higher addresses)
-        mem_snapshot = {}
-        for i in range(0, self.mem.ram_size):
-            v = self.read_ram(i)
-            if v != 0:
-                mem_snapshot[i] = v
-
-        # Convert register operand markers back to raw ints for handlers, and
-        # call the appropriate handler (handlers are named op_<mnemonic> and
-        # expect plain ints/strings as originally implemented).
-        handler = getattr(self, f"op_{instr.lower()}", None)
-        if handler is None:
+        handler, decoded_ops, instr_text, invoker = self._predecoded[pre_exec_pc]
+        if invoker is None:
+            instr, _ = self.program[pre_exec_pc]
             raise NotImplementedError(f"Instruction {instr} not implemented")
 
-        # decode operands for handler call
-        decoded_ops = []
-        for o in operands:
-            if isinstance(o, tuple) and len(o) == 2 and o[0] == "reg":
-                decoded_ops.append(int(o[1]))
-            else:
-                decoded_ops.append(o)
+        should_trace = self.trace_enabled if record_trace is None else record_trace
 
-        handler(*tuple(decoded_ops))
+        if should_trace:
+            regs_snapshot = list(self.regs)
+            mem_snapshot = dict(self.mem.nonzero_ram)
 
-        # record step trace after execution (post-state)
-        self.step_count += 1
+        invoker()
 
-        source_line = self.pc_to_line.get(pre_exec_pc, -1)
-        self.step_trace.append(
-            {
-                "step": self.step_count,
-                "pc": pre_exec_pc,
-                "instr": instr_text,
-                "regs": regs_snapshot,
-                "mem": mem_snapshot,
-                "sreg": self.sreg,
-                "sp": self.sp,
-                "source_line": source_line,
-            }
-        )
+        self.step_count += 1
+        if should_trace:
+            source_line = self.pc_to_line.get(pre_exec_pc, -1)
+            self.step_trace.append(
+                {
+                    "step": self.step_count,
+                    "pc": pre_exec_pc,
+                    "instr": instr_text,
+                    "regs": regs_snapshot,
+                    "mem": mem_snapshot,
+                    "sreg": self.sreg,
+                    "sp": self.sp,
+                    "source_line": source_line,
+                }
+            )
         self.pc += 1
         return True
 
     def run(self, max_steps: int = 100000, show_progress: bool = True) -> None:
-        """Run instructions until program end or ``max_steps`` is reached.
+        """Run instructions until completion or max_steps limit is reached.
 
         Args:
-            max_steps: Maximum number of instruction steps to execute
-                (default 100000).
-            show_progress: If True, display a progress bar during execution
-                (default True).
-
-        Note:
-            This repeatedly calls :meth:`step` until it returns False or the
-            maximum step count is reached.
+            max_steps: Maximum instruction step executions allowed.
+            show_progress: Whether to show progress bar in terminal.
         """
         self.running = True
-        steps = 0
 
-        if show_progress:
-            pb = ProgressBar(total=max_steps, desc="CPU execution")
+        if not show_progress and not self.trace_enabled:
+            # Fast-path execution for batch and headless runs
+            if not self._predecoded or len(self._predecoded) != len(self.program):
+                self._build_predecoded()
+            predec = self._predecoded
+            prog_len = len(predec)
+            steps = 0
+            while self.running and steps < max_steps:
+                curr_pc = self.pc
+                if not (0 <= curr_pc < prog_len):
+                    self.running = False
+                    break
+                item = predec[curr_pc]
+                invoker = item[3]
+                if invoker is None:
+                    instr, _ = self.program[curr_pc]
+                    raise NotImplementedError(f"Instruction {instr} not implemented")
+                invoker()
+                self.step_count += 1
+                self.pc += 1
+                steps += 1
+            return
+
+        steps = 0
+        pb = (
+            ProgressBar(total=max_steps, desc="CPU execution")
+            if show_progress
+            else None
+        )
 
         try:
             while self.running and steps < max_steps:
-                ok = self.step()
-                if not ok:
+                if not self.step():
                     break
                 steps += 1
-
-                if show_progress:
+                if pb:
                     pb.update(1)
         finally:
-            if show_progress:
+            if pb:
                 pb.close()
 
-    def op_nop(self):
-        """No-operation: does nothing for one step."""
-        pass
+    def op_nop(self) -> None:
+        """No Operation (NOP).
 
-    def op_ldi(self, reg_idx: int, imm: int):
-        """Load an immediate value into a register.
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: No operation.
+            Status Register (SREG): None.
+        """
 
-        Args:
-            reg_idx: Destination register index.
-            imm: Immediate value to load.
+    def op_ldi(self, reg_idx: int, imm: int) -> None:
+        """Load Immediate (LDI).
 
-        Note:
-            The AVR LDI instruction is normally restricted to R16..R31; this
-            simplified implementation accepts any register index.
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: Rd <- K (16 <= d <= 31, 0 <= K <= 255)
+            Status Register (SREG): None.
+
+        Args:
+            reg_idx: Destination register index (16..31).
+            imm: Immediate byte value.
         """
         self.write_reg(reg_idx, imm)
 
-    def op_mov(self, rd: int, rr: int):
-        """Copy the value from register ``rr`` into ``rd``.
+    def op_mov(self, rd: int, rr: int) -> None:
+        """Copy Register (MOV).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: Rd <- Rr (0 <= d, r <= 31)
+            Status Register (SREG): None.
 
         Args:
             rd: Destination register index.
@@ -472,15 +540,16 @@ def op_mov(self, rd: int, rr: int):
         """
         self.write_reg(rd, self.read_reg(rr))
 
-    def op_add(self, rd: int, rr: int):
-        """Add register ``rr`` to ``rd`` (Rd := Rd + Rr) and update flags.
+    def op_add(self, rd: int, rr: int) -> None:
+        """Add without Carry (ADD).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: Rd <- Rd + Rr
+            Status Register (SREG): H, S, V, N, Z, C
 
         Args:
             rd: Destination register index.
             rr: Source register index.
-
-        Note:
-            Sets C, H, N, V, S, Z per AVR semantics.
         """
         a = self.read_reg(rd)
         b = self.read_reg(rr)
@@ -488,8 +557,12 @@ def op_add(self, rd: int, rr: int):
         self.write_reg(rd, res & 0xFF)
         self._set_flags_add(a, b, 0, res)
 
-    def op_and(self, rd: int, rr: int):
-        """Logical AND (Rd := Rd & Rr) — updates N, Z, V=0, C=0, H=0, S.
+    def op_and(self, rd: int, rr: int) -> None:
+        """Logical AND (AND).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: Rd <- Rd • Rr
+            Status Register (SREG): S, V=0, N, Z (H, C unaffected)
 
         Args:
             rd: Destination register index.
@@ -499,8 +572,12 @@ def op_and(self, rd: int, rr: int):
         self.write_reg(rd, res)
         self._set_flags_logical(res)
 
-    def op_or(self, rd: int, rr: int):
-        """Logical OR (Rd := Rd | Rr) — updates N, Z, V=0, C=0, H=0, S.
+    def op_or(self, rd: int, rr: int) -> None:
+        """Logical OR (OR).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: Rd <- Rd v Rr
+            Status Register (SREG): S, V=0, N, Z (H, C unaffected)
 
         Args:
             rd: Destination register index.
@@ -510,8 +587,12 @@ def op_or(self, rd: int, rr: int):
         self.write_reg(rd, res)
         self._set_flags_logical(res)
 
-    def op_eor(self, rd: int, rr: int):
-        """Exclusive OR (Rd := Rd ^ Rr) — updates N, Z, V=0, C=0, H=0, S.
+    def op_eor(self, rd: int, rr: int) -> None:
+        """Exclusive OR (EOR).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: Rd <- Rd ⊕ Rr
+            Status Register (SREG): S, V=0, N, Z (H, C unaffected)
 
         Args:
             rd: Destination register index.
@@ -521,8 +602,12 @@ def op_eor(self, rd: int, rr: int):
         self.write_reg(rd, res)
         self._set_flags_logical(res)
 
-    def op_sub(self, rd: int, rr: int):
-        """Subtract (Rd := Rd - Rr) and set flags C,H,N,V,S,Z.
+    def op_sub(self, rd: int, rr: int) -> None:
+        """Subtract without Carry (SUB).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: Rd <- Rd - Rr
+            Status Register (SREG): H, S, V, N, Z, C
 
         Args:
             rd: Destination register index.
@@ -534,8 +619,12 @@ def op_sub(self, rd: int, rr: int):
         self.write_reg(rd, res_full & 0xFF)
         self._set_flags_sub(a, b, 0, res_full)
 
-    def op_inc(self, rd: int):
-        """Increment (Rd := Rd + 1) — updates V,N,S,Z; does not change C/H.
+    def op_inc(self, rd: int) -> None:
+        """Increment (INC).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: Rd <- Rd + 1
+            Status Register (SREG): S, V, N, Z (C unaffected)
 
         Args:
             rd: Destination register index.
@@ -545,8 +634,12 @@ def op_inc(self, rd: int):
         self.write_reg(rd, new)
         self._set_flags_inc(old, new)
 
-    def op_dec(self, rd: int):
-        """Decrement (Rd := Rd - 1) — updates V,N,S,Z; does not change C/H.
+    def op_dec(self, rd: int) -> None:
+        """Decrement (DEC).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: Rd <- Rd - 1
+            Status Register (SREG): S, V, N, Z (C unaffected)
 
         Args:
             rd: Destination register index.
@@ -556,30 +649,77 @@ def op_dec(self, rd: int):
         self.write_reg(rd, new)
         self._set_flags_dec(old, new)
 
-    def op_mul(self, rd: int, rr: int):
-        """Multiply 8x8 -> 16: store low in Rd, high in Rd+1.
+    def op_mul(self, rd: int, rr: int) -> None:
+        """Multiply Unsigned (MUL).
 
-        Args:
-            rd: Destination register index for low byte.
-            rr: Source register index.
+        AVR Instruction Set Manual DS40002198A:
+        R1:R0 <- Rd * Rr (unsigned).
+        SREG C: Set if bit 15 of result is set; cleared otherwise.
+        SREG Z: Set if result is $0000; cleared otherwise.
 
-        Note:
-            Updates Z and C flags. Z set if product == 0; C set if high != 0.
+        Args:
+            rd: Multiplicand register index (0..31).
+            rr: Multiplier register index (0..31).
         """
         a = self.read_reg(rd)
         b = self.read_reg(rr)
         prod = a * b
-        low = prod & 0xFF
-        high = (prod >> 8) & 0xFF
-        self.write_reg(rd, low)
-        if rd + 1 < 32:
-            self.write_reg(rd + 1, high)
-        self.set_flag(SREG_Z, prod == 0)
-        self.set_flag(SREG_C, high != 0)
-        self.set_flag(SREG_H, False)
+        self.write_reg(0, prod & 0xFF)
+        self.write_reg(1, (prod >> 8) & 0xFF)
+        self.set_flag(SREG_Z, (prod & 0xFFFF) == 0)
+        self.set_flag(SREG_C, bool((prod >> 15) & 1))
+
+    def op_muls(self, rd: int, rr: int) -> None:
+        """Multiply Signed (MULS).
+
+        AVR Instruction Set Manual DS40002198A:
+        R1:R0 <- Rd * Rr (signed).
+        SREG C: Set if bit 15 of result is set; cleared otherwise.
+        SREG Z: Set if result is $0000; cleared otherwise.
+
+        Args:
+            rd: Multiplicand signed register index (0..31).
+            rr: Multiplier signed register index (0..31).
+        """
+        a = self.read_reg(rd)
+        b = self.read_reg(rr)
+        sa = a - 256 if a >= 128 else a
+        sb = b - 256 if b >= 128 else b
+        prod = sa * sb
+        prod_u16 = prod & 0xFFFF
+        self.write_reg(0, prod_u16 & 0xFF)
+        self.write_reg(1, (prod_u16 >> 8) & 0xFF)
+        self.set_flag(SREG_Z, prod_u16 == 0)
+        self.set_flag(SREG_C, bool((prod_u16 >> 15) & 1))
+
+    def op_mulsu(self, rd: int, rr: int) -> None:
+        """Multiply Signed with Unsigned (MULSU).
 
-    def op_adc(self, rd: int, rr: int):
-        """Add with carry (Rd := Rd + Rr + C) and update flags.
+        AVR Instruction Set Manual DS40002198A:
+        R1:R0 <- Rd * Rr (Rd signed, Rr unsigned).
+        SREG C: Set if bit 15 of result is set; cleared otherwise.
+        SREG Z: Set if result is $0000; cleared otherwise.
+
+        Args:
+            rd: Multiplicand signed register index (0..31).
+            rr: Multiplier unsigned register index (0..31).
+        """
+        a = self.read_reg(rd)
+        b = self.read_reg(rr)
+        sa = a - 256 if a >= 128 else a
+        prod = sa * b
+        prod_u16 = prod & 0xFFFF
+        self.write_reg(0, prod_u16 & 0xFF)
+        self.write_reg(1, (prod_u16 >> 8) & 0xFF)
+        self.set_flag(SREG_Z, prod_u16 == 0)
+        self.set_flag(SREG_C, bool((prod_u16 >> 15) & 1))
+
+    def op_adc(self, rd: int, rr: int) -> None:
+        """Add with Carry (ADC).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: Rd <- Rd + Rr + C
+            Status Register (SREG): H, S, V, N, Z, C
 
         Args:
             rd: Destination register index.
@@ -587,119 +727,106 @@ def op_adc(self, rd: int, rr: int):
         """
         a = self.read_reg(rd)
         b = self.read_reg(rr)
-        carry_in = 1 if self.get_flag(SREG_C) else 0
+        carry_in = int(self.get_flag(SREG_C))
         res = a + b + carry_in
         self.write_reg(rd, res & 0xFF)
         self._set_flags_add(a, b, carry_in, res)
 
-    def op_clr(self, rd: int):
-        """Clear register (Rd := 0). Behaves like EOR Rd,Rd for flags.
+    def op_clr(self, rd: int) -> None:
+        """Clear Register: Rd <- Rd ⊕ Rd = $00 (EOR Rd, Rd).
+
+        Status Register (SREG) per AVR Manual DS40002198A:
+            S: 0, V: 0, N: 0, Z: 1; H, C, T, I unaffected.
+            Alternative name to the EOR Rd, Rd instruction.
 
         Args:
             rd: Destination register index.
         """
-        self.write_reg(rd, 0)
-        self.set_flag(SREG_N, False)
-        self.set_flag(SREG_V, False)
-        self.set_flag(SREG_S, False)
-        self.set_flag(SREG_Z, True)
-        self.set_flag(SREG_C, False)
-        self.set_flag(SREG_H, False)
+        self.op_eor(rd, rd)
+
+    def op_ser(self, rd: int) -> None:
+        """Set Register: Rd <- $FF (LDI Rd, $FF).
 
-    def op_ser(self, rd: int):
-        """Set register all ones (Rd := 0xFF). Update flags conservatively.
+        Status Register (SREG) per AVR Manual DS40002198A:
+            None affected. Alternative name to the LDI Rd, $FF instruction.
 
         Args:
             rd: Destination register index.
         """
         self.write_reg(rd, 0xFF)
-        self.set_flag(SREG_N, True)
-        self.set_flag(SREG_V, False)
-        self.set_flag(SREG_S, True)
-        self.set_flag(SREG_Z, False)
-        self.set_flag(SREG_C, False)
-        self.set_flag(SREG_H, False)
 
-    def op_div(self, rd: int, rr: int):
-        """Unsigned divide convenience instruction: quotient -> Rd, remainder -> Rd+1.
+    def op_in(self, rd: int, port: int) -> None:
+        """Load an I/O Location to Register (IN).
 
-        Args:
-            rd: Destination register index for quotient.
-            rr: Divisor register index.
-
-        Note:
-            If divisor is zero, sets C and Z flags to indicate error.
-        """
-        a = self.read_reg(rd)
-        b = self.read_reg(rr)
-        if b == 0:
-            self.write_reg(rd, 0)
-            self.set_flag(SREG_C, True)
-            self.set_flag(SREG_Z, True)
-            return
-        q = a // b
-        r = a % b
-        self.write_reg(rd, q)
-        if rd + 1 < 32:
-            self.write_reg(rd + 1, r)
-        self.set_flag(SREG_Z, q == 0)
-        self.set_flag(SREG_C, False)
-        self.set_flag(SREG_H, False)
-        self.set_flag(SREG_V, False)
-
-    def op_in(self, rd: int, port: int):
-        """Read from I/O port into register.
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: Rd <- P
+            Status Register (SREG): None.
 
         Args:
             rd: Destination register index.
-            port: Port address to read from.
+            port: Port/memory address to read from.
         """
-        val = self.read_ram(port)
-        self.write_reg(rd, val)
+        self.write_reg(rd, self.read_ram(port))
 
-    def op_out(self, port: int, rr: int):
-        """Write register value to I/O port.
+    def op_out(self, port: int, rr: int) -> None:
+        """Store Register to an I/O Location (OUT).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: P <- Rr
+            Status Register (SREG): None.
 
         Args:
-            port: Port address to write to.
+            port: Port/memory address to write to.
             rr: Source register index.
         """
-        val = self.read_reg(rr)
-        self.write_ram(port, val)
+        self.write_ram(port, self.read_reg(rr))
+
+    def op_jmp(self, label: str | int) -> None:
+        """Jump (JMP).
 
-    def op_jmp(self, label: str | int):
-        """Jump to a given label or numeric address by updating the program counter.
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: PC <- k
+            Status Register (SREG): None.
 
         Args:
-            label: The jump target. If a string, it is treated as a symbolic label
-                and looked up in self.labels. If an int, it is used directly as the
-                numeric address.
+            label: Target label name or instruction address.
 
-        Note:
-            Sets PC to target - 1 because the instruction dispatcher will
-            increment PC after the current instruction completes.
+        Raises:
+            KeyError: If target label string is not found.
         """
-        if isinstance(label, str):
-            if label not in self.labels:
-                raise KeyError(f"Label {label} not found")
-            self.pc = self.labels[label] - 1
+        if isinstance(label, int):
+            self.pc = label - 1
         else:
-            self.pc = int(label) - 1
+            target = self.labels.get(label)
+            if target is not None:
+                self.pc = target - 1
+            else:
+                try:
+                    self.pc = int(label) - 1
+                except (ValueError, TypeError):
+                    raise KeyError(f"Label {label} not found")
+
+    def op_cpi(self, rd: int, imm: int) -> None:
+        """Compare with Immediate (CPI).
 
-    def op_cpi(self, rd: int, imm: int):
-        """Compare register with immediate (sets flags but doesn't modify register).
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: Rd - K (16 <= d <= 31, 0 <= K <= 255)
+            Status Register (SREG): H, S, V, N, Z, C
 
         Args:
-            rd: Register index to compare.
-            imm: Immediate value to compare against.
+            rd: Register index to compare (16..31).
+            imm: Immediate byte value.
         """
         a = self.read_reg(rd)
         b = imm & 0xFF
-        res = a - b
-        self._set_flags_sub(a, b, 0, res)
+        self._set_flags_sub(a, b, 0, a - b)
 
-    def op_cp(self, rd: int, rr: int):
-        """Compare two registers (sets flags but doesn't modify registers).
+    def op_cp(self, rd: int, rr: int) -> None:
+        """Compare (CP).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: Rd - Rr
+            Status Register (SREG): H, S, V, N, Z, C
 
         Args:
             rd: First register index.
@@ -707,30 +834,26 @@ def op_cp(self, rd: int, rr: int):
         """
         a = self.read_reg(rd)
         b = self.read_reg(rr)
-        res = a - b
-        self._set_flags_sub(a, b, 0, res)
+        self._set_flags_sub(a, b, 0, a - b)
+
+    def op_lsl(self, rd: int) -> None:
+        """Logical Shift Left: C <- Rd7, Rd(n+1) <- Rd(n), Rd0 <- 0.
 
-    def op_lsl(self, rd: int):
-        """Logical shift left (Rd := Rd << 1).
+        Status Register (SREG) per AVR Manual DS40002198A:
+            H: Rd3, S: N ⊕ V, V: N ⊕ C, N: R7, Z: Set if result is $00, C: Rd7
+            Alternative name to the ADD Rd, Rd instruction.
 
         Args:
             rd: Destination register index.
         """
-        v = self.read_reg(rd)
-        carry = (v >> 7) & 1
-        nv = (v << 1) & 0xFF
-        self.write_reg(rd, nv)
-        self.set_flag(SREG_C, bool(carry))
-        n = (nv >> 7) & 1
-        vflag = n ^ carry
-        self.set_flag(SREG_N, bool(n))
-        self.set_flag(SREG_V, bool(vflag))
-        self.set_flag(SREG_S, bool(n ^ vflag))
-        self.set_flag(SREG_Z, nv == 0)
-        self.set_flag(SREG_H, False)
+        self.op_add(rd, rd)
+
+    def op_lsr(self, rd: int) -> None:
+        """Logical Shift Right: 0 -> Rd7 -> ... -> Rd0 -> C.
 
-    def op_lsr(self, rd: int):
-        """Logical shift right (Rd := Rd >> 1).
+        Status Register (SREG) per AVR Manual DS40002198A:
+            S: N ⊕ V, V: C, N: 0, Z: Set if result is $00, C: Rd0
+            H, T, I unaffected (-).
 
         Args:
             rd: Destination register index.
@@ -739,51 +862,78 @@ def op_lsr(self, rd: int):
         carry = v & 1
         nv = (v >> 1) & 0xFF
         self.write_reg(rd, nv)
-        self.set_flag(SREG_C, bool(carry))
-        self.set_flag(SREG_N, False)
-        self.set_flag(SREG_V, bool(carry))
-        self.set_flag(SREG_S, bool(carry))
-        self.set_flag(SREG_Z, nv == 0)
-        self.set_flag(SREG_H, False)
+        c = carry
+        vflag = c
+        s = c
+        z = 1 if nv == 0 else 0
+        self.sreg = (self.sreg & 0xE0) | (s << 4) | (vflag << 3) | (z << 1) | c
 
-    def op_rol(self, rd: int):
-        """Rotate left through carry.
+    def op_asr(self, rd: int) -> None:
+        """Arithmetic Shift Right: Rd7 -> Rd7 -> ... -> Rd0 -> C.
+
+        Status Register (SREG) per AVR Manual DS40002198A:
+            S: N ⊕ V, V: N ⊕ C, N: R7, Z: Set if result is $00, C: Rd0
+            H, T, I unaffected (-).
 
         Args:
             rd: Destination register index.
         """
         v = self.read_reg(rd)
-        carry_in = 1 if self.get_flag(SREG_C) else 0
-        carry_out = (v >> 7) & 1
-        nv = ((v << 1) & 0xFF) | carry_in
+        carry = v & 1
+        sign = v & 0x80
+        nv = (v >> 1) | sign
         self.write_reg(rd, nv)
-        self.set_flag(SREG_C, bool(carry_out))
-        self.set_flag(SREG_N, bool((nv >> 7) & 1))
-        self.set_flag(SREG_Z, nv == 0)
-        self.set_flag(SREG_V, False)
-        self.set_flag(SREG_S, bool((nv >> 7) & 1))
-        self.set_flag(SREG_H, False)
+        n = (nv >> 7) & 1
+        c = carry
+        vflag = n ^ c
+        s = n ^ vflag
+        z = 1 if nv == 0 else 0
+        self.sreg = (
+            (self.sreg & 0xE0) | (s << 4) | (vflag << 3) | (n << 2) | (z << 1) | c
+        )
+
+    def op_rol(self, rd: int) -> None:
+        """Rotate Left Through Carry: C <- Rd7, Rd(n+1) <- Rd(n), Rd0 <- C.
+
+        Status Register (SREG) per AVR Manual DS40002198A:
+            H: Rd3, S: N ⊕ V, V: N ⊕ C, N: R7, Z: Set if result is $00, C: Rd7
+            Alternative name to the ADC Rd, Rd instruction.
+
+        Args:
+            rd: Destination register index.
+        """
+        self.op_adc(rd, rd)
+
+    def op_ror(self, rd: int) -> None:
+        """Rotate Right Through Carry: Rd7 <- C, Rd(n) <- Rd(n+1), C <- Rd0.
 
-    def op_ror(self, rd: int):
-        """Rotate right through carry.
+        Status Register (SREG) per AVR Manual DS40002198A:
+            S: N ⊕ V, V: N ⊕ C, N: R7, Z: Set if result is $00, C: Rd0
+            H, T, I unaffected (-).
 
         Args:
             rd: Destination register index.
         """
         v = self.read_reg(rd)
-        carry_in = 1 if self.get_flag(SREG_C) else 0
+        carry_in = int(self.get_flag(SREG_C))
         carry_out = v & 1
         nv = (v >> 1) | (carry_in << 7)
         self.write_reg(rd, nv)
-        self.set_flag(SREG_C, bool(carry_out))
-        self.set_flag(SREG_N, bool((nv >> 7) & 1))
-        self.set_flag(SREG_Z, nv == 0)
-        self.set_flag(SREG_V, False)
-        self.set_flag(SREG_S, bool((nv >> 7) & 1))
-        self.set_flag(SREG_H, False)
+        n = (nv >> 7) & 1
+        c = carry_out
+        vflag = n ^ c
+        s = n ^ vflag
+        z = 1 if nv == 0 else 0
+        self.sreg = (
+            (self.sreg & 0xE0) | (s << 4) | (vflag << 3) | (n << 2) | (z << 1) | c
+        )
 
-    def op_com(self, rd: int):
-        """One's complement: Rd := ~Rd. Updates N,V,S,Z,C per AVR-ish semantics.
+    def op_com(self, rd: int) -> None:
+        """One's Complement: Rd <- $FF - Rd.
+
+        Status Register (SREG) per AVR Manual DS40002198A:
+            S: N ⊕ V, V: 0, N: R7, Z: Set if result is $00, C: 1
+            H, T, I unaffected (-).
 
         Args:
             rd: Destination register index.
@@ -792,15 +942,14 @@ def op_com(self, rd: int):
         nv = (~v) & 0xFF
         self.write_reg(rd, nv)
         n = (nv >> 7) & 1
-        self.set_flag(SREG_N, bool(n))
-        self.set_flag(SREG_V, False)
-        self.set_flag(SREG_S, bool(n))
-        self.set_flag(SREG_Z, nv == 0)
-        self.set_flag(SREG_C, True)
-        self.set_flag(SREG_H, False)
+        z = 1 if nv == 0 else 0
+        self.sreg = (self.sreg & 0xE0) | (n << 4) | (n << 2) | (z << 1) | 1
+
+    def op_neg(self, rd: int) -> None:
+        """Two's Complement: Rd <- $00 - Rd.
 
-    def op_neg(self, rd: int):
-        """Two's complement (negate): Rd := 0 - Rd. Flags as subtraction from 0.
+        Status Register (SREG) per AVR Manual DS40002198A:
+            H: R3 + ~Rd3, S: N ⊕ V, V: Rd == $80, N: R7, Z: Set if result is $00, C: Rd != $00
 
         Args:
             rd: Destination register index.
@@ -810,64 +959,69 @@ def op_neg(self, rd: int):
         self.write_reg(rd, res_full & 0xFF)
         self._set_flags_sub(0, a, 0, res_full)
 
-    def op_swap(self, rd: int):
-        """Swap nibbles in register: Rd[7:4] <-> Rd[3:0]. Does not affect SREG.
+    def op_swap(self, rd: int) -> None:
+        """Swap Nibbles: Rd(7..4) <-> Rd(3..0).
+
+        Status Register (SREG) per AVR Manual DS40002198A:
+            None affected.
 
         Args:
             rd: Destination register index.
         """
         v = self.read_reg(rd)
-        nv = ((v & 0x0F) << 4) | ((v >> 4) & 0x0F)
-        self.write_reg(rd, nv)
+        self.write_reg(rd, ((v & 0x0F) << 4) | ((v >> 4) & 0x0F))
+
+    def op_tst(self, rd: int) -> None:
+        """Test for Zero or Minus: Rd & Rd.
 
-    def op_tst(self, rd: int):
-        """Test: perform AND Rd,Rd and update flags but do not store result.
+        Status Register (SREG) per AVR Manual DS40002198A:
+            S: N ⊕ V, V: 0, N: R7, Z: Set if Rd is $00
+            Alternative name to the AND Rd, Rd instruction.
 
         Args:
             rd: Register index to test.
         """
-        v = self.read_reg(rd)
-        res = v & v
-        self._set_flags_logical(res)
+        self.op_and(rd, rd)
+
+    def op_andi(self, rd: int, imm: int) -> None:
+        """Logical AND with Immediate (ANDI).
 
-    def op_andi(self, rd: int, imm: int):
-        """Logical AND with immediate (Rd := Rd & K).
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: Rd <- Rd • K (16 <= d <= 31, 0 <= K <= 255)
+            Status Register (SREG): S, V=0, N, Z (H, C unaffected)
 
         Args:
-            rd: Destination register index.
+            rd: Destination register index (16..31).
             imm: Immediate value.
         """
         res = self.read_reg(rd) & (imm & 0xFF)
         self.write_reg(rd, res)
         self._set_flags_logical(res)
 
-    def op_ori(self, rd: int, imm: int):
-        """Logical OR with immediate (Rd := Rd | K).
+    def op_ori(self, rd: int, imm: int) -> None:
+        """Logical OR with Immediate (ORI).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: Rd <- Rd v K (16 <= d <= 31, 0 <= K <= 255)
+            Status Register (SREG): S, V=0, N, Z (H, C unaffected)
 
         Args:
-            rd: Destination register index.
+            rd: Destination register index (16..31).
             imm: Immediate value.
         """
         res = self.read_reg(rd) | (imm & 0xFF)
         self.write_reg(rd, res)
         self._set_flags_logical(res)
 
-    def op_eori(self, rd: int, imm: int):
-        """Logical EOR with immediate (Rd := Rd ^ K).
+    def op_subi(self, rd: int, imm: int) -> None:
+        """Subtract Immediate (SUBI).
 
-        Args:
-            rd: Destination register index.
-            imm: Immediate value.
-        """
-        res = self.read_reg(rd) ^ (imm & 0xFF)
-        self.write_reg(rd, res)
-        self._set_flags_logical(res)
-
-    def op_subi(self, rd: int, imm: int):
-        """Subtract immediate (Rd := Rd - K).
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: Rd <- Rd - K (16 <= d <= 31, 0 <= K <= 255)
+            Status Register (SREG): H, S, V, N, Z, C
 
         Args:
-            rd: Destination register index.
+            rd: Destination register index (16..31).
             imm: Immediate value.
         """
         a = self.read_reg(rd)
@@ -876,8 +1030,12 @@ def op_subi(self, rd: int, imm: int):
         self.write_reg(rd, res_full & 0xFF)
         self._set_flags_sub(a, b, 0, res_full)
 
-    def op_sbc(self, rd: int, rr: int):
-        """Subtract with carry (Rd := Rd - Rr - C).
+    def op_sbc(self, rd: int, rr: int) -> None:
+        """Subtract with Carry (SBC).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: Rd <- Rd - Rr - C
+            Status Register (SREG): H, S, V, N, Z, C
 
         Args:
             rd: Destination register index.
@@ -885,35 +1043,53 @@ def op_sbc(self, rd: int, rr: int):
         """
         a = self.read_reg(rd)
         b = self.read_reg(rr)
-        borrow_in = 1 if self.get_flag(SREG_C) else 0
+        borrow_in = int(self.get_flag(SREG_C))
         res_full = a - b - borrow_in
         self.write_reg(rd, res_full & 0xFF)
         self._set_flags_sub(a, b, borrow_in, res_full)
 
-    def op_sbci(self, rd: int, imm: int):
-        """Subtract immediate with carry: Rd := Rd - K - C.
+    def op_sbci(self, rd: int, imm: int) -> None:
+        """Subtract Immediate with Carry (SBCI).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: Rd <- Rd - K - C (16 <= d <= 31, 0 <= K <= 255)
+            Status Register (SREG): H, S, V, N, Z, C
 
         Args:
-            rd: Destination register index.
+            rd: Destination register index (16..31).
             imm: Immediate value.
         """
         a = self.read_reg(rd)
         b = imm & 0xFF
-        borrow_in = 1 if self.get_flag(SREG_C) else 0
+        borrow_in = int(self.get_flag(SREG_C))
         res_full = a - b - borrow_in
         self.write_reg(rd, res_full & 0xFF)
         self._set_flags_sub(a, b, borrow_in, res_full)
 
-    def op_sei(self):
-        """Set Global Interrupt Enable (I bit)."""
+    def op_sei(self) -> None:
+        """Set Global Interrupt Flag (SEI).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: I <- 1
+            Status Register (SREG): I
+        """
         self.set_flag(SREG_I, True)
 
-    def op_cli(self):
-        """Clear Global Interrupt Enable (I bit)."""
+    def op_cli(self) -> None:
+        """Clear Global Interrupt Flag (CLI).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: I <- 0
+            Status Register (SREG): I
+        """
         self.set_flag(SREG_I, False)
 
-    def op_cpse(self, rd: int, rr: int):
-        """Compare and Skip if Equal: compare Rd,Rr; if equal, skip next instruction.
+    def op_cpse(self, rd: int, rr: int) -> None:
+        """Compare Skip if Equal (CPSE).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: If Rd = Rr then PC <- PC + 2 (or 3)
+            Status Register (SREG): None (all flags unaffected)
 
         Args:
             rd: First register index.
@@ -921,106 +1097,129 @@ def op_cpse(self, rd: int, rr: int):
         """
         a = self.read_reg(rd)
         b = self.read_reg(rr)
-        self._set_flags_sub(a, b, 0, a - b)
         if a == b:
             self.pc += 1
 
-    def op_sbrs(self, rd: int, bit: int):
-        """Skip next if bit in register is set.
+    def op_sbrs(self, rd: int, bit: int) -> None:
+        """Skip if Bit in Register is Set (SBRS).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: If Rd(b) = 1 then PC <- PC + 2 (or 3)
+            Status Register (SREG): None.
 
         Args:
             rd: Register index.
-            bit: Bit position to test.
+            bit: Bit index (0..7).
         """
-        v = self.read_reg(rd)
-        if ((v >> (bit & 7)) & 1) == 1:
+        if ((self.read_reg(rd) >> (bit & 7)) & 1) == 1:
             self.pc += 1
 
-    def op_sbrc(self, rd: int, bit: int):
-        """Skip next if bit in register is clear.
+    def op_sbrc(self, rd: int, bit: int) -> None:
+        """Skip if Bit in Register is Cleared (SBRC).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: If Rd(b) = 0 then PC <- PC + 2 (or 3)
+            Status Register (SREG): None.
 
         Args:
             rd: Register index.
-            bit: Bit position to test.
+            bit: Bit index (0..7).
         """
-        v = self.read_reg(rd)
-        if ((v >> (bit & 7)) & 1) == 0:
+        if ((self.read_reg(rd) >> (bit & 7)) & 1) == 0:
             self.pc += 1
 
-    def op_sbis(self, io_addr: int, bit: int):
-        """Skip if bit in IO/RAM-mapped address is set.
+    def op_sbis(self, io_addr: int, bit: int) -> None:
+        """Skip if Bit in I/O Register is Set (SBIS).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: If P(b) = 1 then PC <- PC + 2 (or 3)
+            Status Register (SREG): None.
 
         Args:
             io_addr: I/O or RAM address.
-            bit: Bit position to test.
+            bit: Bit index (0..7).
         """
-        v = self.read_ram(io_addr)
-        if ((v >> (bit & 7)) & 1) == 1:
+        if ((self.read_ram(io_addr) >> (bit & 7)) & 1) == 1:
             self.pc += 1
 
-    def op_sbic(self, io_addr: int, bit: int):
-        """Skip if bit in IO/RAM-mapped address is clear.
+    def op_sbic(self, io_addr: int, bit: int) -> None:
+        """Skip if Bit in I/O Register is Cleared (SBIC).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: If P(b) = 0 then PC <- PC + 2 (or 3)
+            Status Register (SREG): None.
 
         Args:
             io_addr: I/O or RAM address.
-            bit: Bit position to test.
+            bit: Bit index (0..7).
         """
-        v = self.read_ram(io_addr)
-        if ((v >> (bit & 7)) & 1) == 0:
+        if ((self.read_ram(io_addr) >> (bit & 7)) & 1) == 0:
             self.pc += 1
 
-    def op_sbiw(self, rd_word_low: int, imm_word: int):
-        """Subtract immediate from word register pair (Rd:Rd+1) — simplified.
+    def op_sbiw(self, rd_word_low: int, imm_word: int) -> None:
+        """Subtract Immediate from Word (SBIW).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: Rd+1:Rd <- Rd+1:Rd - K (d in {24, 26, 28, 30}, 0 <= K <= 63)
+            Status Register (SREG): S, V, N, Z, C
 
         Args:
-            rd_word_low: Low register of the pair (even register index).
-            imm_word: 16-bit immediate to subtract.
+            rd_word_low: Low register index of register pair (e.g. 24, 26, 28, 30).
+            imm_word: Immediate value to subtract.
         """
         lo = self.read_reg(rd_word_low)
         hi = self.read_reg(rd_word_low + 1) if (rd_word_low + 1) < 32 else 0
         word = (hi << 8) | lo
         new = (word - (imm_word & 0xFFFF)) & 0xFFFF
-        new_lo = new & 0xFF
-        new_hi = (new >> 8) & 0xFF
-        self.write_reg(rd_word_low, new_lo)
+        self.write_reg(rd_word_low, new & 0xFF)
         if rd_word_low + 1 < 32:
-            self.write_reg(rd_word_low + 1, new_hi)
+            self.write_reg(rd_word_low + 1, (new >> 8) & 0xFF)
         self._set_flags_sub16(word, imm_word & 0xFFFF, 0, word - (imm_word & 0xFFFF))
 
-    def op_adiw(self, rd_word_low: int, imm_word: int):
-        """Add immediate to word register pair (Rd:Rd+1) - simplified.
+    def op_adiw(self, rd_word_low: int, imm_word: int) -> None:
+        """Add Immediate to Word (ADIW).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: Rd+1:Rd <- Rd+1:Rd + K (d in {24, 26, 28, 30}, 0 <= K <= 63)
+            Status Register (SREG): S, V, N, Z, C
 
         Args:
-            rd_word_low: Low register of the pair (even register index).
-            imm_word: 16-bit immediate to add.
+            rd_word_low: Low register index of register pair (e.g. 24, 26, 28, 30).
+            imm_word: Immediate value to add.
         """
         lo = self.read_reg(rd_word_low)
         hi = self.read_reg(rd_word_low + 1) if (rd_word_low + 1) < 32 else 0
         word = (hi << 8) | lo
         new = (word + (imm_word & 0xFFFF)) & 0xFFFF
-        new_lo = new & 0xFF
-        new_hi = (new >> 8) & 0xFF
-        self.write_reg(rd_word_low, new_lo)
+        self.write_reg(rd_word_low, new & 0xFF)
         if rd_word_low + 1 < 32:
-            self.write_reg(rd_word_low + 1, new_hi)
+            self.write_reg(rd_word_low + 1, (new >> 8) & 0xFF)
         self._set_flags_add16(word, imm_word & 0xFFFF, 0, word + (imm_word & 0xFFFF))
 
-    def op_rjmp(self, label: str):
-        """Relative jump — label may be an int or string label.
+    def op_rjmp(self, label: str | int) -> None:
+        """Relative Jump (RJMP).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: PC <- PC + k + 1
+            Status Register (SREG): None.
 
         Args:
-            label: Jump target (label name or relative offset).
+            label: Jump target offset or symbolic label.
         """
         if isinstance(label, int):
-            self.pc = self.pc + int(label)
+            self.pc += label
         else:
             self.op_jmp(label)
 
-    def op_rcall(self, label: str):
-        """Relative call — push return address and jump relatively or to label.
+    def op_rcall(self, label: str | int) -> None:
+        """Relative Call to Subroutine (RCALL).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: PC <- PC + k + 1, STACK <- PC + 1
+            Status Register (SREG): None.
 
         Args:
-            label: Call target (label name or relative offset).
+            label: Call target offset or symbolic label.
         """
         ret = self.pc + 1
         self.write_ram(self.sp, (ret >> 8) & 0xFF)
@@ -1028,175 +1227,263 @@ def op_rcall(self, label: str):
         self.write_ram(self.sp, ret & 0xFF)
         self.sp -= 1
         if isinstance(label, int):
-            target = self.pc + int(label)
-            self.pc = int(target) - 1
+            self.pc = self.pc + label - 1
         else:
             self.op_jmp(label)
 
-    def op_sbi(self, io_addr: int, bit: int):
-        """Set a bit in an I/O/memory-mapped address (use RAM area).
+    def op_sbi(self, io_addr: int, bit: int) -> None:
+        """Set Bit in I/O Register (SBI).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: I/O(P, b) <- 1
+            Status Register (SREG): None.
+
+        Args:
+            io_addr: Memory address.
+            bit: Bit index (0..7).
+        """
+        self.write_ram(io_addr, self.read_ram(io_addr) | (1 << (bit & 7)))
+
+    def op_cbi(self, io_addr: int, bit: int) -> None:
+        """Clear Bit in I/O Register (CBI).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: I/O(P, b) <- 0
+            Status Register (SREG): None.
+
+        Args:
+            io_addr: Memory address.
+            bit: Bit index (0..7).
+        """
+        self.write_ram(io_addr, self.read_ram(io_addr) & ~(1 << (bit & 7)))
+
+    def op_ld(self, rd: int, addr_reg: int) -> None:
+        """Load Indirect from Data Space to Register (LD).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: Rd <- (X / Y / Z)
+            Status Register (SREG): None.
+
+        Supports 16-bit pointer pairs (X=R27:R26, Y=R29:R28, Z=R31:R30) when high byte is set.
 
         Args:
-            io_addr: I/O or RAM address to modify.
-            bit: Bit index to set (0..7).
+            rd: Destination register index.
+            addr_reg: Pointer register index.
         """
-        # set bit in I/O location (use RAM address space)
-        val = self.read_ram(io_addr)
-        nval = val | (1 << (bit & 7))
-        self.write_ram(io_addr, nval)
+        high = self.read_reg(addr_reg + 1) if addr_reg in (26, 28, 30) else 0
+        low = self.read_reg(addr_reg)
+        addr = (high << 8) | low if high > 0 else low
+        self.write_reg(rd, self.read_ram(addr))
+
+    def op_st(self, addr_reg: int, rr: int) -> None:
+        """Store Indirect from Register to Data Space (ST).
 
-    def op_cbi(self, io_addr: int, bit: int):
-        """Clear a bit in an I/O/memory-mapped address (use RAM area).
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: (X / Y / Z) <- Rr
+            Status Register (SREG): None.
+
+        Supports 16-bit pointer pairs (X=R27:R26, Y=R29:R28, Z=R31:R30) when high byte is set.
 
         Args:
-            io_addr: I/O or RAM address to modify.
-            bit: Bit index to clear (0..7).
+            addr_reg: Pointer register index.
+            rr: Source register index.
         """
-        val = self.read_ram(io_addr)
-        nval = val & ~(1 << (bit & 7))
-        self.write_ram(io_addr, nval)
+        high = self.read_reg(addr_reg + 1) if addr_reg in (26, 28, 30) else 0
+        low = self.read_reg(addr_reg)
+        addr = (high << 8) | low if high > 0 else low
+        self.write_ram(addr, self.read_reg(rr))
+
+    def op_lds(self, rd: int, addr: int) -> None:
+        """Load Direct from Data Space (LDS).
 
-    def op_ld(self, rd: int, addr_reg: int):
-        """Load from RAM at address contained in register ``addr_reg`` into
-        ``rd``.
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: Rd <- (k)
+            Status Register (SREG): None.
 
         Args:
             rd: Destination register index.
-            addr_reg: Register index containing the RAM address to load from.
+            addr: Memory address (0..ram_size-1).
         """
-        addr = self.read_reg(addr_reg)
-        val = self.read_ram(addr)
-        self.write_reg(rd, val)
+        self.write_reg(rd, self.read_ram(addr))
 
-    def op_st(self, addr_reg: int, rr: int):
-        """Store register ``rr`` into RAM at address contained in register
-        ``addr_reg``.
+    def op_sts(self, addr: int, rr: int) -> None:
+        """Store Direct to Data Space (STS).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: (k) <- Rr
+            Status Register (SREG): None.
 
         Args:
-            addr_reg: Register index containing the RAM address to write to.
-            rr: Source register index to store.
+            addr: Memory address (0..ram_size-1).
+            rr: Source register index.
         """
-        addr = self.read_reg(addr_reg)
-        val = self.read_reg(rr)
-        self.write_ram(addr, val)
+        self.write_ram(addr, self.read_reg(rr))
+
+    def op_brne(self, label: str | int) -> None:
+        """Branch if Not Equal (BRNE).
 
-    def op_brne(self, label: str):
-        """Branch to label if Zero flag is not set (BRNE).
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: If Z = 0 then PC <- PC + k + 1
+            Status Register (SREG): None.
 
         Args:
-            label: Destination label to jump to if Z flag is not set.
+            label: Jump target label or numeric address.
         """
-        z = self.get_flag(SREG_Z)
-        if not z:
+        if not (self.sreg & 0x02):
             self.op_jmp(label)
 
-    def op_breq(self, label: str):
-        """Branch to label if Zero flag is set (BREQ).
+    def op_breq(self, label: str | int) -> None:
+        """Branch if Equal (BREQ).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: If Z = 1 then PC <- PC + k + 1
+            Status Register (SREG): None.
 
         Args:
-            label: Destination label to jump to if Z flag is set.
+            label: Jump target label or numeric address.
         """
-        z = self.get_flag(SREG_Z)
-        if z:
+        if self.sreg & 0x02:
             self.op_jmp(label)
 
-    def op_brcs(self, label: str):
-        """Branch to a label if the carry flag is set.
+    def op_brcs(self, label: str | int) -> None:
+        """Branch if Carry Set (BRCS).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: If C = 1 then PC <- PC + k + 1
+            Status Register (SREG): None.
 
         Args:
-            label (str): Destination label to jump to if the carry flag is set.
+            label: Jump target label or numeric address.
         """
-        c = self.get_flag(SREG_C)
-        if c:
+        if self.sreg & 0x01:
             self.op_jmp(label)
 
-    def op_brcc(self, label: str):
-        """Branch to a label if the carry flag is clear.
+    def op_brcc(self, label: str | int) -> None:
+        """Branch if Carry Cleared (BRCC).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: If C = 0 then PC <- PC + k + 1
+            Status Register (SREG): None.
 
         Args:
-            label (str): Destination label to jump to if the carry flag is clear.
+            label: Jump target label or numeric address.
         """
-        c = self.get_flag(SREG_C)
-        if not c:
+        if not (self.sreg & 0x01):
             self.op_jmp(label)
 
-    def op_brge(self, label: str | int):
-        """Branch if Greater or Equal (Signed).
+    def op_brlo(self, label: str | int) -> None:
+        """Branch if Lower Unsigned (BRLO).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: If C = 1 then PC <- PC + k + 1 (alias for BRCS)
+            Status Register (SREG): None.
 
         Args:
-            label: Destination label or address to jump to if the condition is met.
+            label: Jump target label or numeric address.
         """
-        s = self.get_flag(SREG_S)
-        if not s:
+        if self.sreg & 0x01:
             self.op_jmp(label)
 
-    def op_brlt(self, label: str | int):
-        """Branch if Less Than (Signed).
+    def op_brsh(self, label: str | int) -> None:
+        """Branch if Same or Higher Unsigned (BRSH).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: If C = 0 then PC <- PC + k + 1 (alias for BRCC)
+            Status Register (SREG): None.
 
         Args:
-            label: Destination label or address to jump to if the condition is met.
+            label: Jump target label or numeric address.
         """
-        s = self.get_flag(SREG_S)
-        if s:
+        if not (self.sreg & 0x01):
             self.op_jmp(label)
 
-    def op_brmi(self, label: str | int):
-        """Branch if Minus (Negative flag set).
+    def op_brge(self, label: str | int) -> None:
+        """Branch if Greater or Equal Signed (BRGE).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: If S = 0 (N ⊕ V = 0) then PC <- PC + k + 1
+            Status Register (SREG): None.
 
         Args:
-            label: Destination label or address to jump to if the condition is met.
+            label: Jump target label or numeric address.
         """
-        n = self.get_flag(SREG_N)
-        if n:
+        if not (self.sreg & 0x10):
             self.op_jmp(label)
 
-    def op_brpl(self, label: str | int):
-        """Branch if Plus (Negative flag clear).
+    def op_brlt(self, label: str | int) -> None:
+        """Branch if Less Than Signed (BRLT).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: If S = 1 (N ⊕ V = 1) then PC <- PC + k + 1
+            Status Register (SREG): None.
 
         Args:
-            label: Destination label or address to jump to if the condition is met.
+            label: Jump target label or numeric address.
         """
-        n = self.get_flag(SREG_N)
-        if not n:
+        if self.sreg & 0x10:
             self.op_jmp(label)
 
-    def op_push(self, rr: int):
-        """Push a register value onto the stack.
+    def op_brmi(self, label: str | int) -> None:
+        """Branch if Minus (BRMI).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: If N = 1 then PC <- PC + k + 1
+            Status Register (SREG): None.
 
         Args:
-            rr: Source register index to push.
+            label: Jump target label or numeric address.
+        """
+        if self.sreg & 0x04:
+            self.op_jmp(label)
 
-        Note:
-            The value of register ``rr`` is written to RAM at the current
-            stack pointer, and the stack pointer is then decremented.
+    def op_brpl(self, label: str | int) -> None:
+        """Branch if Plus (BRPL).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: If N = 0 then PC <- PC + k + 1
+            Status Register (SREG): None.
+
+        Args:
+            label: Jump target label or numeric address.
         """
-        val = self.read_reg(rr)
-        self.write_ram(self.sp, val)
-        self.sp -= 1
+        if not (self.sreg & 0x04):
+            self.op_jmp(label)
+
+    def op_push(self, rr: int) -> None:
+        """Push Register on Stack (PUSH).
 
-    def op_pop(self, rd: int):
-        """Pop a value from the stack into a register.
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: STACK <- Rr, SP <- SP - 1
+            Status Register (SREG): None.
 
         Args:
-            rd: Destination register index to receive the popped value.
+            rr: Source register index.
+        """
+        self.write_ram(self.sp, self.read_reg(rr))
+        self.sp -= 1
 
-        Note:
-            The stack pointer is incremented, the byte at the new stack pointer
-            is read from RAM, and the value is written into register ``rd``.
+    def op_pop(self, rd: int) -> None:
+        """Pop Register from Stack (POP).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: SP <- SP + 1, Rd <- STACK
+            Status Register (SREG): None.
+
+        Args:
+            rd: Destination register index.
         """
         self.sp += 1
-        val = self.read_ram(self.sp)
-        self.write_reg(rd, val)
+        self.write_reg(rd, self.read_ram(self.sp))
 
-    def op_call(self, label: str):
-        """Call a subroutine by pushing the return address and jumping to label.
+    def op_call(self, label: str | int) -> None:
+        """Long Call to Subroutine (CALL).
 
-        Args:
-            label: Label to call.
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: STACK <- PC + 1, PC <- k
+            Status Register (SREG): None.
 
-        Note:
-            The return address (pc+1) is pushed as two bytes (high then low) onto
-            the stack, decrementing the stack pointer after each write.
+        Args:
+            label: Subroutine target label or address.
         """
         ret = self.pc + 1
         self.write_ram(self.sp, (ret >> 8) & 0xFF)
@@ -1205,40 +1492,38 @@ def op_call(self, label: str):
         self.sp -= 1
         self.op_jmp(label)
 
-    def op_ret(self):
-        """Return from subroutine by popping the return address and setting PC.
+    def op_ret(self) -> None:
+        """Return from Subroutine (RET).
 
-        Note:
-            Two bytes are popped from the stack (low then high) to reconstruct the
-            return address, which is then loaded into the program counter.
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: PC <- STACK
+            Status Register (SREG): None.
         """
         self.sp += 1
         low = self.read_ram(self.sp)
         self.sp += 1
         high = self.read_ram(self.sp)
-        ret = (high << 8) | low
-        self.pc = ret - 1
+        self.pc = ((high << 8) | low) - 1
 
-    def op_reti(self):
-        """Return from interrupt: pop return address and set I flag."""
+    def op_reti(self) -> None:
+        """Return from Interrupt (RETI).
+
+        Per AVR Instruction Set Manual DS40002198A:
+            Operation: PC <- STACK, I <- 1
+            Status Register (SREG): I
+        """
         self.sp += 1
         low = self.read_ram(self.sp)
         self.sp += 1
         high = self.read_ram(self.sp)
-        ret = (high << 8) | low
         self.set_flag(SREG_I, True)
-        self.pc = ret - 1
+        self.pc = ((high << 8) | low) - 1
 
-    def trigger_interrupt(self, vector_addr: int):
-        """Trigger an interrupt vector if it is enabled.
+    def trigger_interrupt(self, vector_addr: int) -> None:
+        """Trigger an interrupt if enabled in vector configuration.
 
         Args:
-            vector_addr: Interrupt vector address to jump to.
-
-        Note:
-            If the interrupt vector is enabled in ``self.interrupts``, the current
-            PC+1 is pushed onto the stack (high then low byte) and control jumps
-            to ``vector_addr``.
+            vector_addr: Vector entry address in RAM.
         """
         if not self.interrupts.get(vector_addr, False):
             return
diff --git a/src/tiny8/memory.py b/src/tiny8/memory.py
index a4b8ecc..69de4fa 100644
--- a/src/tiny8/memory.py
+++ b/src/tiny8/memory.py
@@ -1,140 +1,161 @@
-"""Memory model for tiny8 - simple RAM and ROM with change tracking."""
+"""Memory model for tiny8 providing RAM and ROM with change tracking."""
+
+from collections import deque
 
 
 class Memory:
-    """Memory class for a simple byte-addressable RAM/ROM model.
+    """Byte-addressable RAM/ROM memory subsystem.
 
-    This class provides a minimal memory subsystem with separate RAM and ROM
-    regions, change-logging for writes/loads, and convenience snapshot
-    methods. All stored values are maintained as 8-bit unsigned bytes (0-255).
+    Maintains separate RAM and ROM buffers as 8-bit unsigned bytes (0-255)
+    and logs modifications for tracing and visualization.
 
     Args:
-        ram_size: Number of bytes in RAM (default 2048).
-        rom_size: Number of bytes in ROM (default 2048).
+        ram_size: Number of bytes in RAM. Defaults to 65536.
+        rom_size: Number of bytes in ROM. Defaults to 2048.
 
     Attributes:
-        ram: Mutable list representing RAM contents (each element 0-255).
-        rom: Mutable list representing ROM contents (each element 0-255).
-        ram_changes: Change log for RAM writes. Each entry is a tuple
-            (addr, old_value, new_value, step) appended only when a write
-            changes the stored byte.
-        rom_changes: Change log for ROM loads. Each entry is a tuple
-            (addr, old_value, new_value, step) appended when load_rom
-            changes bytes.
-
-    Note:
-        - All write/load operations mask values with 0xFF so stored values are
-          always in the range 0..255.
-        - ram_changes and rom_changes record only actual changes (old != new).
-        - read_* methods perform bounds checking and raise IndexError for
-          invalid addresses.
-        - load_rom accepts an iterable of integers and raises ValueError if
-          the input is larger than the configured ROM size.
+        ram_size: Size of RAM in bytes.
+        rom_size: Size of ROM in bytes.
+        ram: Bytearray representing RAM contents.
+        rom: Bytearray representing ROM contents.
+        ram_changes: Log of RAM writes as (addr, old_val, new_val, step) tuples.
+        rom_changes: Log of ROM writes as (addr, old_val, new_val, step) tuples.
     """
 
-    def __init__(self, ram_size: int = 2048, rom_size: int = 2048):
+    __slots__ = (
+        "ram_size",
+        "rom_size",
+        "max_changes",
+        "track_changes",
+        "ram",
+        "rom",
+        "nonzero_ram",
+        "ram_changes",
+        "rom_changes",
+    )
+
+    def __init__(
+        self,
+        ram_size: int = 65536,
+        rom_size: int = 2048,
+        max_changes: int = 2000,
+        track_changes: bool = True,
+    ) -> None:
         self.ram_size = ram_size
         self.rom_size = rom_size
-        self.ram = [0] * ram_size
-        self.rom = [0] * rom_size
-        self.ram_changes: list[tuple[int, int, int, int]] = []
-        self.rom_changes: list[tuple[int, int, int, int]] = []
+        self.max_changes = max_changes
+        self.track_changes = track_changes
+        self.ram = bytearray(ram_size)
+        self.rom = bytearray(rom_size)
+        self.nonzero_ram: dict[int, int] = {}
+        self.ram_changes: deque[tuple[int, int, int, int]] = deque(maxlen=max_changes)
+        self.rom_changes: deque[tuple[int, int, int, int]] = deque(maxlen=max_changes)
 
     def read_ram(self, addr: int) -> int:
-        """Read and return the value stored in RAM at the specified address.
+        """Read a byte from RAM.
 
         Args:
-            addr: The RAM address to read. Must be within the valid range
-                0 <= addr < self.ram_size.
+            addr: Memory address in the range [0, ram_size).
 
         Returns:
-            The integer value stored at the given RAM address.
+            The byte value stored at the address.
 
         Raises:
-            IndexError: If the provided addr is negative or not less than
-                self.ram_size.
+            IndexError: If addr is outside valid RAM boundaries.
         """
-        if addr < 0 or addr >= self.ram_size:
+        if not (0 <= addr < self.ram_size):
             raise IndexError("RAM address out of range")
         return self.ram[addr]
 
     def write_ram(self, addr: int, value: int, step: int = 0) -> None:
-        """Write a byte to RAM at the specified address.
+        """Write a byte to RAM and log change if value changed.
 
         Args:
-            addr: Target RAM address. Must be in the range [0, self.ram_size).
-            value: Value to write; only the low 8 bits are stored (value & 0xFF).
-            step: Optional step/timestamp associated with this write; defaults to 0.
+            addr: Memory address in the range [0, ram_size).
+            value: Byte value to store (masked to 8-bit).
+            step: Step index associated with this write. Defaults to 0.
 
         Raises:
-            IndexError: If addr is out of the valid RAM range.
-
-        Note:
-            The provided value is masked to a single byte before storing. If
-            the stored byte changes, a record (addr, old_value, new_value,
-            step) is appended to self.ram_changes to track the modification.
+            IndexError: If addr is outside valid RAM boundaries.
         """
-        if addr < 0 or addr >= self.ram_size:
+        if not (0 <= addr < self.ram_size):
             raise IndexError("RAM address out of range")
         old = self.ram[addr]
-        self.ram[addr] = value & 0xFF
-        if old != self.ram[addr]:
-            self.ram_changes.append((addr, old, self.ram[addr], step))
+        new = value & 0xFF
+        if old == new:
+            return
+        self.ram[addr] = new
+        if self.track_changes:
+            self.ram_changes.append((addr, old, new, step))
+        if new != 0:
+            self.nonzero_ram[addr] = new
+        elif old != 0:
+            self.nonzero_ram.pop(addr, None)
+
+    def clear_changes(self) -> None:
+        """Clear memory modification history to free memory."""
+        self.ram_changes.clear()
+        self.rom_changes.clear()
+
+    def restore_ram(self, mem_dict: dict[int, int]) -> None:
+        """Restore RAM contents from a dictionary of non-zero entries."""
+        for addr in list(self.nonzero_ram.keys()):
+            self.ram[addr] = 0
+        self.nonzero_ram = dict(mem_dict)
+        for addr, val in self.nonzero_ram.items():
+            if 0 <= addr < self.ram_size:
+                self.ram[addr] = val & 0xFF
 
     def load_rom(self, data: list[int]) -> None:
-        """Load a ROM image into the emulator's ROM buffer.
+        """Load byte sequence into ROM and record changes.
 
         Args:
-            data: Sequence of integer byte values (expected 0-255) comprising
-                the ROM image. Values outside 0-255 will be truncated to 8 bits.
+            data: Sequence of byte values to load into ROM.
 
         Raises:
-            ValueError: If len(data) is greater than self.rom_size.
-
-        Note:
-            Overwrites self.rom[i] for i in range(len(data)) with
-            (data[i] & 0xFF). Appends (index, old_value, new_value, 0) to
-            self.rom_changes for each address where the value actually changed.
+            ValueError: If data length exceeds configured rom_size.
         """
         if len(data) > self.rom_size:
             raise ValueError("ROM image too large")
-        for i, v in enumerate(data):
-            old = self.rom[i]
-            self.rom[i] = v & 0xFF
-            if old != self.rom[i]:
-                self.rom_changes.append((i, old, self.rom[i], 0))
+        if self.track_changes:
+            for i, v in enumerate(data):
+                old = self.rom[i]
+                new = v & 0xFF
+                self.rom[i] = new
+                if old != new:
+                    self.rom_changes.append((i, old, new, 0))
+        else:
+            for i, v in enumerate(data):
+                self.rom[i] = v & 0xFF
 
     def read_rom(self, addr: int) -> int:
-        """Read a value from the ROM at the specified address.
+        """Read a byte from ROM.
 
         Args:
-            addr: Zero-based address within ROM to read.
+            addr: ROM address in the range [0, rom_size).
 
         Returns:
-            The value stored at the given ROM address.
+            The byte value stored at the address.
 
         Raises:
-            IndexError: If ``addr`` is negative or greater than or equal to
-                ``self.rom_size``.
+            IndexError: If addr is outside valid ROM boundaries.
         """
-        if addr < 0 or addr >= self.rom_size:
+        if not (0 <= addr < self.rom_size):
             raise IndexError("ROM address out of range")
         return self.rom[addr]
 
     def snapshot_ram(self) -> list[int]:
-        """Return a snapshot copy of the emulator's RAM.
+        """Return a shallow copy of RAM contents.
 
         Returns:
-            A new list containing the current contents of RAM. Each element
-            represents a byte (0-255). Modifying the returned list will not
-            affect the emulator's internal state.
+            List of integers representing current RAM.
         """
         return list(self.ram)
 
     def snapshot_rom(self) -> list[int]:
-        """Return a snapshot copy of the ROM contents.
+        """Return a shallow copy of ROM contents.
 
         Returns:
-            A list of integers representing the ROM data at the time of the call.
+            List of integers representing current ROM.
         """
         return list(self.rom)
diff --git a/src/tiny8/tui.py b/src/tiny8/tui.py
new file mode 100644
index 0000000..0bfbac1
--- /dev/null
+++ b/src/tiny8/tui.py
@@ -0,0 +1,3807 @@
+"""Modern Textual-based interactive debugger and dashboard for Tiny8.
+
+Provides an OLED black themed TUI with real-time registers, memory, SREG flags,
+gradient heatmap bars, stack explorer, breakpoints, and telemetry.
+"""
+
+from __future__ import annotations
+
+import argparse
+import bisect
+import re
+import shutil
+from collections import Counter
+from pathlib import Path
+from typing import Any, Callable
+
+from rich.text import Text
+from textual import events
+from textual.app import App, ComposeResult
+from textual.binding import Binding
+from textual.containers import Container, Horizontal, Vertical, VerticalScroll
+from textual.reactive import reactive
+from textual.screen import ModalScreen, Screen
+from textual.widgets import (
+    Button,
+    Header,
+    Input,
+    Label,
+    ProgressBar,
+    Static,
+    TabbedContent,
+    TabPane,
+    TextArea,
+)
+
+from .assembler import assemble, assemble_file
+from .compiler import (
+    compile_c_file,
+    compile_c_file_with_symbols,
+    compile_c_with_symbols,
+)
+from .cpu import CPU
+
+PLAYBACK_RATES: list[int] = [1, 5, 20, 100, 500, 2000, 5000, 10000, 50000]
+
+
+class CheckpointManager:
+    """Manages sparse snapshots and loop detection for time-travel.
+
+    Stores complete CPU state snapshots every `interval` steps (default 100),
+    enabling instant seeking and reverse playback without heavy RAM overhead.
+    """
+
+    def __init__(
+        self,
+        cpu: CPU,
+        interval: int = 100,
+        max_snapshots: int = 50000,
+    ) -> None:
+        self.cpu = cpu
+        self.interval = interval
+        self.max_snapshots = max_snapshots
+        self.snapshots: dict[int, dict[str, Any]] = {}
+        self.checkpoint_steps: list[int] = []
+        self._history_signatures: dict[tuple[int, int, tuple[int, ...]], int] = {}
+        self.infinite_loop_detected: bool = False
+        self.loop_reason: str = ""
+
+        # Initial step 0 snapshot
+        self.record(0)
+
+    def record(self, step: int) -> None:
+        """Store a CPU snapshot at the given step."""
+        if step not in self.snapshots and len(self.snapshots) < self.max_snapshots:
+            self.snapshots[step] = self.cpu.snapshot()
+            if not self.checkpoint_steps or step > self.checkpoint_steps[-1]:
+                self.checkpoint_steps.append(step)
+            else:
+                idx = bisect.bisect_right(self.checkpoint_steps, step)
+                self.checkpoint_steps.insert(idx, step)
+
+    def record_if_interval(self, step: int) -> None:
+        """Record snapshot if step is a multiple of interval."""
+        if step % self.interval == 0:
+            self.record(step)
+
+    def restore_exact_step(self, target_step: int) -> bool:
+        """Restore CPU to exact target_step using the closest preceding snapshot."""
+        if target_step < 0 or not self.checkpoint_steps:
+            return False
+
+        # If target_step is beyond currently recorded checkpoints, dynamically extend cache
+        if target_step > self.checkpoint_steps[-1] and not self.infinite_loop_detected:
+            latest_step = self.checkpoint_steps[-1]
+            self.cpu.restore_snapshot(self.snapshots[latest_step])
+            self.cpu.running = 0 <= self.cpu.pc < len(self.cpu.program)
+            old_trace = self.cpu.trace_enabled
+            self.cpu.trace_enabled = False
+            try:
+                while self.cpu.running and self.cpu.step_count < target_step:
+                    if self.detect_loop():
+                        self.cpu.running = False
+                        break
+                    if not self.cpu.step(record_trace=False):
+                        self.cpu.running = False
+                        break
+                    if self.cpu.step_count % self.interval == 0:
+                        self.record(self.cpu.step_count)
+                if self.cpu.step_count not in self.snapshots:
+                    self.record(self.cpu.step_count)
+            finally:
+                self.cpu.trace_enabled = old_trace
+
+        # Find closest checkpoint <= target_step
+        idx = bisect.bisect_right(self.checkpoint_steps, target_step) - 1
+        if idx < 0:
+            base_step = self.checkpoint_steps[0]
+        else:
+            base_step = self.checkpoint_steps[idx]
+
+        self.cpu.restore_snapshot(self.snapshots[base_step])
+        self.cpu.running = 0 <= self.cpu.pc < len(self.cpu.program)
+        self.infinite_loop_detected = False
+        self.loop_reason = ""
+        if self.detect_loop():
+            self.cpu.running = False
+        self.cpu.step_trace.clear()
+
+        # Step forward remaining steps (at most self.interval - 1 steps)
+        steps_to_advance = max(0, target_step - base_step) if self.cpu.running else 0
+        for _ in range(steps_to_advance):
+            if self.detect_loop():
+                self.cpu.running = False
+                break
+            if not self.cpu.step():
+                self.cpu.running = False
+                break
+
+        # Ensure step_trace has at least the current step representation
+        if not self.cpu.step_trace:
+            cur_instr = ""
+            if 0 <= self.cpu.pc < len(self.cpu.program):
+                instr, ops = self.cpu.program[self.cpu.pc]
+                cur_instr = (
+                    f"{instr} " + ", ".join(str(o) for o in ops) if ops else instr
+                )
+            self.cpu.step_trace.append(
+                {
+                    "step": self.cpu.step_count,
+                    "pc": self.cpu.pc,
+                    "instr": cur_instr,
+                    "regs": list(self.cpu.regs),
+                    "mem": dict(self.cpu.mem.nonzero_ram),
+                    "sreg": self.cpu.sreg,
+                    "sp": self.cpu.sp,
+                    "source_line": self.cpu.pc_to_line.get(self.cpu.pc, -1),
+                }
+            )
+        return True
+
+    def invalidate_after(self, step: int) -> None:
+        """Invalidate checkpoints after modified step on memory/register edit."""
+        to_remove = [s for s in self.checkpoint_steps if s > step]
+        for s in to_remove:
+            self.snapshots.pop(s, None)
+            self.checkpoint_steps.remove(s)
+        self._history_signatures.clear()
+        self.infinite_loop_detected = False
+        self.loop_reason = ""
+
+    def detect_loop(self, window_size: int = 256) -> bool:
+        """Detect infinite loop (e.g. self-jump HALT or cycling registers/PC)."""
+        cur_pc = self.cpu.pc
+        if 0 <= cur_pc < len(self.cpu.program):
+            instr, operands = self.cpu.program[cur_pc]
+            if instr in ("RJMP", "JMP") and operands:
+                op = operands[0]
+                target_pc: int | None = None
+                if isinstance(op, str):
+                    target_pc = self.cpu.labels.get(op)
+                elif isinstance(op, int):
+                    if instr == "RJMP":
+                        if op in (-1, 0):
+                            target_pc = cur_pc
+                        else:
+                            target_pc = cur_pc + 1 + op
+                    else:
+                        target_pc = op
+                if target_pc == cur_pc:
+                    self.infinite_loop_detected = True
+                    self.loop_reason = f"HALT spin loop detected at PC=0x{cur_pc:04X} (step {self.cpu.step_count})"
+                    return True
+            elif instr in ("HLT", "BREAK"):
+                self.infinite_loop_detected = True
+                self.loop_reason = f"HALT instruction encountered at PC=0x{cur_pc:04X}"
+                return True
+
+        sig = (cur_pc, self.cpu.sreg, tuple(self.cpu.regs))
+        if sig in self._history_signatures:
+            prev_step = self._history_signatures[sig]
+            diff = self.cpu.step_count - prev_step
+            if 0 < diff <= window_size:
+                self.infinite_loop_detected = True
+                self.loop_reason = f"Cycle loop detected: repeats every {diff} steps at PC=0x{cur_pc:04X}"
+                return True
+        self._history_signatures[sig] = self.cpu.step_count
+        if len(self._history_signatures) > 3000:
+            self._history_signatures.clear()
+        return False
+
+    def precompute(
+        self,
+        max_steps: int | None = None,
+        check_loops: bool = True,
+        progress_callback: Callable[[int, int | None], None] | None = None,
+    ) -> int:
+        """Precompute execution checkpoints until an infinite loop or halt is detected."""
+        if not self.cpu.program or not (0 <= self.cpu.pc < len(self.cpu.program)):
+            return 0
+        old_trace = self.cpu.trace_enabled
+        self.cpu.trace_enabled = False
+        try:
+            self.cpu.running = True
+            computed = 0
+            limit = max_steps if max_steps is not None else 10_000_000
+            while self.cpu.running and computed < limit:
+                if check_loops and self.detect_loop():
+                    self.cpu.running = False
+                    break
+                if not self.cpu.step(record_trace=False):
+                    break
+                computed += 1
+                if self.cpu.step_count % self.interval == 0:
+                    self.record(self.cpu.step_count)
+                if progress_callback and (computed % 10000 == 0):
+                    progress_callback(computed, max_steps)
+            if self.cpu.step_count not in self.snapshots:
+                self.record(self.cpu.step_count)
+            if progress_callback:
+                progress_callback(computed, max_steps)
+            return computed
+        finally:
+            self.cpu.trace_enabled = old_trace
+
+
+INSTRUCTION_DOCS: dict[str, dict[str, str]] = {
+    "NOP": {
+        "name": "No Operation",
+        "syntax": "NOP",
+        "desc": "Performs no operation. The CPU performs a single cycle nop.",
+        "flags": "None",
+    },
+    "LDI": {
+        "name": "Load Immediate",
+        "syntax": "LDI Rd, K",
+        "desc": "Loads an 8-bit constant directly into register Rd (16 <= d <= 31, 0 <= K <= 255).",
+        "flags": "None",
+    },
+    "MOV": {
+        "name": "Copy Register",
+        "syntax": "MOV Rd, Rr",
+        "desc": "Makes a copy of one register into another (Rd <- Rr). The source register Rr is unchanged.",
+        "flags": "None",
+    },
+    "ADD": {
+        "name": "Add without Carry",
+        "syntax": "ADD Rd, Rr",
+        "desc": "Adds two registers without the C Flag and places the result in the destination register Rd (Rd <- Rd + Rr).",
+        "flags": "H, S, V, N, Z, C",
+    },
+    "ADC": {
+        "name": "Add with Carry",
+        "syntax": "ADC Rd, Rr",
+        "desc": "Adds two registers and the contents of the C Flag and places the result in Rd (Rd <- Rd + Rr + C).",
+        "flags": "H, S, V, N, Z, C",
+    },
+    "SUB": {
+        "name": "Subtract without Carry",
+        "syntax": "SUB Rd, Rr",
+        "desc": "Subtracts two registers and places the result in the destination register Rd (Rd <- Rd - Rr).",
+        "flags": "H, S, V, N, Z, C",
+    },
+    "SUBI": {
+        "name": "Subtract Immediate",
+        "syntax": "SUBI Rd, K",
+        "desc": "Subtracts a constant from a register and places the result in Rd (Rd <- Rd - K, 16 <= d <= 31).",
+        "flags": "H, S, V, N, Z, C",
+    },
+    "SBC": {
+        "name": "Subtract with Carry",
+        "syntax": "SBC Rd, Rr",
+        "desc": "Subtracts two registers and subtracts the C Flag and places the result in Rd (Rd <- Rd - Rr - C).",
+        "flags": "H, S, V, N, Z, C",
+    },
+    "SBCI": {
+        "name": "Subtract Immediate with Carry",
+        "syntax": "SBCI Rd, K",
+        "desc": "Subtracts a constant and the C Flag from Rd (Rd <- Rd - K - C, 16 <= d <= 31).",
+        "flags": "H, S, V, N, Z, C",
+    },
+    "AND": {
+        "name": "Logical AND",
+        "syntax": "AND Rd, Rr",
+        "desc": "Performs the logical AND between two registers and places the result in Rd (Rd <- Rd & Rr).",
+        "flags": "S, V=0, N, Z",
+    },
+    "ANDI": {
+        "name": "Logical AND with Immediate",
+        "syntax": "ANDI Rd, K",
+        "desc": "Performs the logical AND between register Rd and a constant (Rd <- Rd & K, 16 <= d <= 31).",
+        "flags": "S, V=0, N, Z",
+    },
+    "OR": {
+        "name": "Logical OR",
+        "syntax": "OR Rd, Rr",
+        "desc": "Performs the logical OR between two registers and places the result in Rd (Rd <- Rd | Rr).",
+        "flags": "S, V=0, N, Z",
+    },
+    "ORI": {
+        "name": "Logical OR with Immediate",
+        "syntax": "ORI Rd, K",
+        "desc": "Performs the logical OR between register Rd and a constant (Rd <- Rd | K, 16 <= d <= 31).",
+        "flags": "S, V=0, N, Z",
+    },
+    "EOR": {
+        "name": "Exclusive OR",
+        "syntax": "EOR Rd, Rr",
+        "desc": "Performs the logical Exclusive OR between two registers and places the result in Rd (Rd <- Rd ^ Rr).",
+        "flags": "S, V=0, N, Z",
+    },
+    "COM": {
+        "name": "One's Complement",
+        "syntax": "COM Rd",
+        "desc": "Performs a One's Complement of register Rd (Rd <- $FF - Rd).",
+        "flags": "S, V=0, N, Z, C=1",
+    },
+    "NEG": {
+        "name": "Two's Complement",
+        "syntax": "NEG Rd",
+        "desc": "Replaces the contents of register Rd with its two's complement (Rd <- $00 - Rd).",
+        "flags": "H, S, V, N, Z, C",
+    },
+    "INC": {
+        "name": "Increment",
+        "syntax": "INC Rd",
+        "desc": "Adds one to the contents of register Rd (Rd <- Rd + 1). The C Flag is not affected.",
+        "flags": "S, V, N, Z",
+    },
+    "DEC": {
+        "name": "Decrement",
+        "syntax": "DEC Rd",
+        "desc": "Subtracts one from the contents of register Rd (Rd <- Rd - 1). The C Flag is not affected.",
+        "flags": "S, V, N, Z",
+    },
+    "MUL": {
+        "name": "Multiply Unsigned",
+        "syntax": "MUL Rd, Rr",
+        "desc": "Performs 8x8 -> 16-bit unsigned multiplication: R1:R0 <- Rd * Rr (R0 = low byte, R1 = high byte).",
+        "flags": "Z, C",
+    },
+    "MULS": {
+        "name": "Multiply Signed",
+        "syntax": "MULS Rd, Rr",
+        "desc": "Performs 8x8 -> 16-bit signed multiplication: R1:R0 <- Rd * Rr (signed).",
+        "flags": "Z, C",
+    },
+    "MULSU": {
+        "name": "Multiply Signed with Unsigned",
+        "syntax": "MULSU Rd, Rr",
+        "desc": "Performs 8x8 -> 16-bit signed-with-unsigned multiplication: R1:R0 <- Rd * Rr (Rd signed, Rr unsigned).",
+        "flags": "Z, C",
+    },
+    "CP": {
+        "name": "Compare",
+        "syntax": "CP Rd, Rr",
+        "desc": "Compares two registers (Rd - Rr) without altering contents and sets SREG flags.",
+        "flags": "H, S, V, N, Z, C",
+    },
+    "CPI": {
+        "name": "Compare with Immediate",
+        "syntax": "CPI Rd, K",
+        "desc": "Compares register Rd with constant K (Rd - K, 16 <= d <= 31) and sets SREG flags.",
+        "flags": "H, S, V, N, Z, C",
+    },
+    "CPSE": {
+        "name": "Compare and Skip if Equal",
+        "syntax": "CPSE Rd, Rr",
+        "desc": "Compares two registers and skips the next instruction if Rd == Rr.",
+        "flags": "None",
+    },
+    "JMP": {
+        "name": "Jump",
+        "syntax": "JMP k",
+        "desc": "Unconditional jump to the entire program space (PC <- k).",
+        "flags": "None",
+    },
+    "RJMP": {
+        "name": "Relative Jump",
+        "syntax": "RJMP k",
+        "desc": "Relative jump to an address within PC - 2K + 1 and PC + 2K (words).",
+        "flags": "None",
+    },
+    "CALL": {
+        "name": "Long Call to a Subroutine",
+        "syntax": "CALL k",
+        "desc": "Calls a subroutine in the entire program space, pushing return address onto the stack.",
+        "flags": "None",
+    },
+    "RCALL": {
+        "name": "Relative Call to a Subroutine",
+        "syntax": "RCALL k",
+        "desc": "Relative call to a subroutine within PC - 2K + 1 and PC + 2K, pushing return address.",
+        "flags": "None",
+    },
+    "RET": {
+        "name": "Return from Subroutine",
+        "syntax": "RET",
+        "desc": "Returns from subroutine by popping return address from the stack into PC.",
+        "flags": "None",
+    },
+    "RETI": {
+        "name": "Return from Interrupt",
+        "syntax": "RETI",
+        "desc": "Returns from interrupt by popping return address from stack and setting Global Interrupt Flag (I <- 1).",
+        "flags": "I=1",
+    },
+    "BREQ": {
+        "name": "Branch if Equal",
+        "syntax": "BREQ k",
+        "desc": "Conditional relative branch: Tests Zero Flag (Z) and branches if Z is set (Z == 1).",
+        "flags": "None",
+    },
+    "BRNE": {
+        "name": "Branch if Not Equal",
+        "syntax": "BRNE k",
+        "desc": "Conditional relative branch: Tests Zero Flag (Z) and branches if Z is cleared (Z == 0).",
+        "flags": "None",
+    },
+    "BRCS": {
+        "name": "Branch if Carry Set",
+        "syntax": "BRCS k",
+        "desc": "Conditional relative branch: Tests Carry Flag (C) and branches if C is set (C == 1).",
+        "flags": "None",
+    },
+    "BRCC": {
+        "name": "Branch if Carry Cleared",
+        "syntax": "BRCC k",
+        "desc": "Conditional relative branch: Tests Carry Flag (C) and branches if C is cleared (C == 0).",
+        "flags": "None",
+    },
+    "BRLO": {
+        "name": "Branch if Lower (Unsigned)",
+        "syntax": "BRLO k",
+        "desc": "Conditional relative branch: Tests Carry Flag (C) and branches if C is set (same as BRCS).",
+        "flags": "None",
+    },
+    "BRSH": {
+        "name": "Branch if Same or Higher (Unsigned)",
+        "syntax": "BRSH k",
+        "desc": "Conditional relative branch: Tests Carry Flag (C) and branches if C is cleared (same as BRCC).",
+        "flags": "None",
+    },
+    "BRGE": {
+        "name": "Branch if Greater or Equal (Signed)",
+        "syntax": "BRGE k",
+        "desc": "Conditional relative branch: Tests Sign Flag (S) and branches if S is cleared (S == 0).",
+        "flags": "None",
+    },
+    "BRLT": {
+        "name": "Branch if Less Than (Signed)",
+        "syntax": "BRLT k",
+        "desc": "Conditional relative branch: Tests Sign Flag (S) and branches if S is set (S == 1).",
+        "flags": "None",
+    },
+    "BRMI": {
+        "name": "Branch if Minus",
+        "syntax": "BRMI k",
+        "desc": "Conditional relative branch: Tests Negative Flag (N) and branches if N is set (N == 1).",
+        "flags": "None",
+    },
+    "BRPL": {
+        "name": "Branch if Plus",
+        "syntax": "BRPL k",
+        "desc": "Conditional relative branch: Tests Negative Flag (N) and branches if N is cleared (N == 0).",
+        "flags": "None",
+    },
+    "PUSH": {
+        "name": "Push Register on Stack",
+        "syntax": "PUSH Rr",
+        "desc": "Stores the contents of register Rr on the stack. The Stack Pointer is post-decremented.",
+        "flags": "None",
+    },
+    "POP": {
+        "name": "Pop Register from Stack",
+        "syntax": "POP Rd",
+        "desc": "Loads register Rd with the contents of the stack. The Stack Pointer is pre-incremented.",
+        "flags": "None",
+    },
+    "LD": {
+        "name": "Load Indirect from Data Space to Register",
+        "syntax": "LD Rd, X / Y / Z",
+        "desc": "Loads one byte indirect from the data space to register Rd using pointer register.",
+        "flags": "None",
+    },
+    "ST": {
+        "name": "Store Indirect from Register to Data Space",
+        "syntax": "ST X / Y / Z, Rr",
+        "desc": "Stores one byte indirect from register Rr to data space using pointer register.",
+        "flags": "None",
+    },
+    "LDS": {
+        "name": "Load Direct from Data Space",
+        "syntax": "LDS Rd, k",
+        "desc": "Loads one byte from the data space to register Rd (Rd <- (k)).",
+        "flags": "None",
+    },
+    "STS": {
+        "name": "Store Direct to Data Space",
+        "syntax": "STS k, Rr",
+        "desc": "Stores one byte from register Rr to the data space ((k) <- Rr).",
+        "flags": "None",
+    },
+    "LSL": {
+        "name": "Logical Shift Left",
+        "syntax": "LSL Rd",
+        "desc": "Shifts all bits in Rd left: C <- Rd7, Rd(n+1) <- Rd(n), Rd0 <- 0 (Alternative to ADD Rd, Rd).",
+        "flags": "H, S, V, N, Z, C",
+    },
+    "LSR": {
+        "name": "Logical Shift Right",
+        "syntax": "LSR Rd",
+        "desc": "Shifts all bits in Rd right: 0 -> Rd7 -> ... -> Rd0 -> C.",
+        "flags": "S, V, N=0, Z, C",
+    },
+    "ASR": {
+        "name": "Arithmetic Shift Right",
+        "syntax": "ASR Rd",
+        "desc": "Shifts all bits in Rd right, preserving sign bit: Rd7 -> Rd7 -> ... -> Rd0 -> C.",
+        "flags": "S, V, N, Z, C",
+    },
+    "ROL": {
+        "name": "Rotate Left Through Carry",
+        "syntax": "ROL Rd",
+        "desc": "Shifts all bits in Rd left through C Flag (Alternative to ADC Rd, Rd).",
+        "flags": "H, S, V, N, Z, C",
+    },
+    "ROR": {
+        "name": "Rotate Right Through Carry",
+        "syntax": "ROR Rd",
+        "desc": "Shifts all bits in Rd right through C Flag: Rd7 <- C, Rd(n) <- Rd(n+1), C <- Rd0.",
+        "flags": "S, V, N, Z, C",
+    },
+    "SWAP": {
+        "name": "Swap Nibbles",
+        "syntax": "SWAP Rd",
+        "desc": "Swaps high and low nibbles in a register: Rd(7..4) <-> Rd(3..0).",
+        "flags": "None",
+    },
+    "TST": {
+        "name": "Test for Zero or Minus",
+        "syntax": "TST Rd",
+        "desc": "Tests if a number is negative or zero: Rd & Rd (Alternative to AND Rd, Rd).",
+        "flags": "S, V=0, N, Z",
+    },
+    "CLR": {
+        "name": "Clear Register",
+        "syntax": "CLR Rd",
+        "desc": "Clears a register: Rd <- Rd ^ Rd = $00 (Alternative to EOR Rd, Rd).",
+        "flags": "S=0, V=0, N=0, Z=1",
+    },
+    "SER": {
+        "name": "Set Register",
+        "syntax": "SER Rd",
+        "desc": "Loads $FF directly into register Rd (16 <= d <= 31; Alternative to LDI Rd, $FF).",
+        "flags": "None",
+    },
+    "ADIW": {
+        "name": "Add Immediate to Word",
+        "syntax": "ADIW Rd+1:Rd, K",
+        "desc": "Adds an immediate value (0-63) to a register pair (R25:R24, R27:R26, R29:R28, R31:R30).",
+        "flags": "S, V, N, Z, C",
+    },
+    "SBIW": {
+        "name": "Subtract Immediate from Word",
+        "syntax": "SBIW Rd+1:Rd, K",
+        "desc": "Subtracts an immediate value (0-63) from a register pair (R25:R24, R27:R26, R29:R28, R31:R30).",
+        "flags": "S, V, N, Z, C",
+    },
+    "SBI": {
+        "name": "Set Bit in I/O Register",
+        "syntax": "SBI A, b",
+        "desc": "Sets a specified bit in an I/O register (0 <= A <= 31, 0 <= b <= 7).",
+        "flags": "None",
+    },
+    "CBI": {
+        "name": "Clear Bit in I/O Register",
+        "syntax": "CBI A, b",
+        "desc": "Clears a specified bit in an I/O register (0 <= A <= 31, 0 <= b <= 7).",
+        "flags": "None",
+    },
+    "IN": {
+        "name": "Load an I/O Location to Register",
+        "syntax": "IN Rd, A",
+        "desc": "Loads data from the I/O Space (Ports, Timers, Configuration Registers) into register Rd.",
+        "flags": "None",
+    },
+    "OUT": {
+        "name": "Store Register to an I/O Location",
+        "syntax": "OUT A, Rr",
+        "desc": "Stores data from register Rr to the I/O Space (Ports, Timers, Configuration Registers).",
+        "flags": "None",
+    },
+    "SEI": {
+        "name": "Set Global Interrupt Flag",
+        "syntax": "SEI",
+        "desc": "Sets the Global Interrupt Flag (I) in SREG. Interrupts will be enabled.",
+        "flags": "I=1",
+    },
+    "CLI": {
+        "name": "Clear Global Interrupt Flag",
+        "syntax": "CLI",
+        "desc": "Clears the Global Interrupt Flag (I) in SREG. Interrupts will be disabled.",
+        "flags": "I=0",
+    },
+    "SBRS": {
+        "name": "Skip if Bit in Register is Set",
+        "syntax": "SBRS Rr, b",
+        "desc": "Tests a bit in a register and skips the next instruction if the bit is set (0 <= b <= 7).",
+        "flags": "None",
+    },
+    "SBRC": {
+        "name": "Skip if Bit in Register is Cleared",
+        "syntax": "SBRC Rr, b",
+        "desc": "Tests a bit in a register and skips the next instruction if the bit is cleared (0 <= b <= 7).",
+        "flags": "None",
+    },
+    "SBIS": {
+        "name": "Skip if Bit in I/O Register is Set",
+        "syntax": "SBIS A, b",
+        "desc": "Tests a bit in an I/O register and skips the next instruction if the bit is set.",
+        "flags": "None",
+    },
+    "SBIC": {
+        "name": "Skip if Bit in I/O Register is Cleared",
+        "syntax": "SBIC A, b",
+        "desc": "Tests a bit in an I/O register and skips the next instruction if the bit is cleared.",
+        "flags": "None",
+    },
+}
+
+
+def interpolate_color(t: float) -> str:
+    """Interpolate RGB color matching authentic Viridis style.
+
+    Args:
+        t: Float value from 0.0 to 1.0.
+
+    Returns:
+        Hex RGB color string (e.g. '#FDE725').
+    """
+    t = max(0.0, min(1.0, t))
+    points = [
+        (0.00, (68, 1, 84)),  # #440154 Deep Purple
+        (0.15, (71, 45, 123)),  # #472D7B Purple
+        (0.30, (49, 104, 142)),  # #31688E Blue
+        (0.45, (33, 145, 140)),  # #21918C Teal
+        (0.60, (53, 183, 121)),  # #35B779 Green
+        (0.75, (109, 205, 89)),  # #6DCD59 Light Green
+        (0.90, (180, 222, 44)),  # #B4DE2C Yellow-Green
+        (1.00, (253, 231, 37)),  # #FDE725 Bright Yellow
+    ]
+    for i in range(len(points) - 1):
+        t0, c0 = points[i]
+        t1, c1 = points[i + 1]
+        if t0 <= t <= t1:
+            ratio = (t - t0) / (t1 - t0) if (t1 - t0) > 0 else 0.0
+            r = int(c0[0] + ratio * (c1[0] - c0[0]))
+            g = int(c0[1] + ratio * (c1[1] - c0[1]))
+            b = int(c0[2] + ratio * (c1[2] - c0[2]))
+            return f"#{r:02X}{g:02X}{b:02X}"
+    return "#FDE725"
+
+
+def get_widget_available_lines(
+    widget: Static, overhead: int = 8, min_lines: int = 4
+) -> int:
+    """Calculate visible content lines available for widget based on terminal/screen height."""
+    try:
+        if widget.screen and widget.screen.size.height > 0:
+            return max(min_lines, widget.screen.size.height - overhead)
+    except Exception:
+        pass
+    try:
+        if getattr(widget, "app", None) and widget.app.size.height > 0:
+            return max(min_lines, widget.app.size.height - overhead)
+    except Exception:
+        pass
+    try:
+        if widget.size.height > 0:
+            return max(min_lines, widget.size.height)
+    except Exception:
+        pass
+    try:
+        return max(min_lines, shutil.get_terminal_size((120, 36)).lines - overhead)
+    except Exception:
+        return 24
+
+
+def render_btop_bar(val: int, max_val: int = 255, width: int = 18) -> Text:
+    """Render horizontal gradient heatmap bar with trailing dot fill.
+
+    Args:
+        val: Current numerical value.
+        max_val: Upper scale limit.
+        width: Character width of bar.
+
+    Returns:
+        Rich Text object containing gradient blocks and shade dots.
+    """
+    ratio = min(1.0, max(0.0, val / max_val)) if max_val > 0 else 0.0
+    filled_blocks = int(ratio * width)
+
+    t = Text()
+    for col in range(width):
+        col_ratio = (col + 1) / width
+        color = interpolate_color(col_ratio)
+        if col < filled_blocks:
+            t.append("█", style=color)
+        else:
+            t.append("░", style="#1A1A1A on #000000")
+    return t
+
+
+class SregWidget(Static):
+    """Badge-style display for SREG condition flags."""
+
+    sreg: reactive[int] = reactive(0)
+
+    FLAGS = [
+        ("I", 7),
+        ("T", 6),
+        ("H", 5),
+        ("S", 4),
+        ("V", 3),
+        ("N", 2),
+        ("Z", 1),
+        ("C", 0),
+    ]
+
+    def render(self) -> Text:
+        res = Text()
+        res.append(" SREG: ", style="bold #00D2FF")
+        for name, bit in self.FLAGS:
+            is_set = (self.sreg >> bit) & 1
+            if is_set:
+                res.append(f" {name} ", style="bold black on #00FF87")
+            else:
+                res.append(f" {name} ", style="dim #444444 on #111111")
+            res.append(" ")
+        res.append(f"(0x{self.sreg:02X})", style="bold #FFAA00")
+        return res
+
+
+class BtopRegistersWidget(Static):
+    """Register bars with graphical gradient heatmaps in a 2-column layout."""
+
+    regs: reactive[list[int]] = reactive(lambda: [0] * 32)
+    prev_regs: reactive[list[int]] = reactive(lambda: [0] * 32)
+    start_r: reactive[int] = reactive(0)
+    visible_count: reactive[int] = reactive(32)
+
+    def render(self) -> Text:
+        t = Text()
+        t.append(
+            " REGISTERS (R00..R31)\n",
+            style="bold #00D2FF",
+        )
+        bar_w = 10
+        for row in range(16):
+            # Left column: R00..R15
+            r_l = row
+            val_l = self.regs[r_l] if r_l < len(self.regs) else 0
+            pval_l = self.prev_regs[r_l] if r_l < len(self.prev_regs) else 0
+            chg_l = val_l != pval_l
+            style_l = (
+                "bold #FFAA00"
+                if chg_l
+                else ("bold #00FF87" if val_l > 0 else "dim #666666")
+            )
+            t.append(f" R{r_l:02d} ", style=style_l)
+            t.append_text(render_btop_bar(val_l, max_val=255, width=bar_w))
+            t.append(f" 0x{val_l:02X}", style=style_l)
+            t.append(f"({val_l:>3})", style="#CCCCCC" if val_l > 0 else "dim #444444")
+            t.append("◀" if chg_l else " ", style="bold #FFAA00")
+
+            t.append(" │ ", style="dim #333333")
+
+            # Right column: R16..R31
+            r_r = row + 16
+            val_r = self.regs[r_r] if r_r < len(self.regs) else 0
+            pval_r = self.prev_regs[r_r] if r_r < len(self.prev_regs) else 0
+            chg_r = val_r != pval_r
+            style_r = (
+                "bold #FFAA00"
+                if chg_r
+                else ("bold #00FF87" if val_r > 0 else "dim #666666")
+            )
+            t.append(f"R{r_r:02d} ", style=style_r)
+            t.append_text(render_btop_bar(val_r, max_val=255, width=bar_w))
+            t.append(f" 0x{val_r:02X}", style=style_r)
+            t.append(f"({val_r:>3})", style="#CCCCCC" if val_r > 0 else "dim #444444")
+            t.append("◀" if chg_r else " ", style="bold #FFAA00")
+            t.append("\n")
+        return t
+
+
+class RegistersWidget(Static):
+    """Grid displaying 32 8-bit general purpose registers."""
+
+    regs: reactive[list[int]] = reactive(lambda: [0] * 32)
+    prev_regs: reactive[list[int]] = reactive(lambda: [0] * 32)
+
+    def render(self) -> Text:
+        t = Text()
+        t.append(" REGISTERS (R0..R31)\n", style="bold #00D2FF")
+        for row in range(4):
+            for col in range(8):
+                idx = row * 8 + col
+                val = self.regs[idx] if idx < len(self.regs) else 0
+                pval = self.prev_regs[idx] if idx < len(self.prev_regs) else 0
+                is_changed = val != pval
+
+                r_label = f"R{idx:02d}:"
+                hex_val = f"{val:02X}"
+                if is_changed:
+                    t.append(f"{r_label}", style="dim #888888")
+                    t.append(f"{hex_val} ", style="bold black on #FFAA00")
+                elif val != 0:
+                    t.append(f"{r_label}", style="dim #888888")
+                    t.append(f"{hex_val} ", style="bold #00FF87")
+                else:
+                    t.append(f"{r_label}", style="dim #333333")
+                    t.append(f"{hex_val} ", style="dim #555555")
+            t.append("\n")
+        return t
+
+
+class MemoryWidget(Static):
+    """32x32 Memory Dump with rich heatmap background coloring for direct visual rendering."""
+
+    mem: reactive[dict[int, int]] = reactive(dict)
+    prev_mem: reactive[dict[int, int]] = reactive(dict)
+    start_addr: reactive[int] = reactive(0x0200)
+    width: int = 32
+    height: int = 32
+    color_mode: reactive[str] = reactive("viridis")
+    show_hex: reactive[bool] = reactive(True)
+
+    @staticmethod
+    def get_heatmap_bg(val: int, color_mode: str = "viridis") -> str:
+        """Calculate rich heat color background for byte value 0..255."""
+        if color_mode == "grayscale":
+            if val <= 0:
+                return "#000000"
+            v = max(0, min(255, val))
+            return f"#{v:02X}{v:02X}{v:02X}"
+        # Viridis mode
+        if val <= 0:
+            return "#0D0818"
+        return interpolate_color(val / 255.0)
+
+    def render(self) -> Text:
+        t = Text()
+        avail_rows = get_widget_available_lines(self, overhead=8, min_lines=4)
+        rows_to_show = max(4, avail_rows - 1)
+        end_addr = min(0xFFFF, self.start_addr + self.width * rows_to_show - 1)
+        palette_lbl = "Viridis" if self.color_mode == "viridis" else "Grayscale"
+        display_lbl = "HEX" if self.show_hex else "PIXEL"
+        t.append(
+            f" MEMORY DUMP (0x{self.start_addr:04X}..0x{end_addr:04X}) "
+            f"[{self.width}x{rows_to_show} | {palette_lbl} | {display_lbl} | g: gray/viridis, x: hex/pixel, j/k: scroll, J/K: fast]\n",
+            style="bold #00D2FF",
+        )
+        for r in range(rows_to_show):
+            row_addr = self.start_addr + r * self.width
+            if row_addr > 0xFFFF:
+                break
+            t.append(f"0x{row_addr:04X}: ", style="bold #666666")
+            for col in range(self.width):
+                addr = row_addr + col
+                if addr > 0xFFFF:
+                    break
+                val = self.mem.get(addr, 0)
+
+                if val == 0:
+                    if self.color_mode == "grayscale":
+                        if self.show_hex:
+                            t.append("..", style="dim #444444 on #000000")
+                        else:
+                            t.append("  ", style="on #000000")
+                    else:
+                        if self.show_hex:
+                            t.append("..", style="dim #472D7B on #0D0818")
+                        else:
+                            t.append("  ", style="on #0D0818")
+                else:
+                    bg = self.get_heatmap_bg(val, self.color_mode)
+                    if self.show_hex:
+                        if self.color_mode == "grayscale":
+                            fg = "#000000" if val >= 128 else "#FFFFFF"
+                        else:
+                            fg = "#000000" if val >= 140 else "#FFFFFF"
+                        t.append(f"{val:02X}", style=f"bold {fg} on {bg}")
+                    else:
+                        t.append("  ", style=f"on {bg}")
+
+            t.append("\n")
+        return t
+
+
+class StackWidget(Static):
+    """Call stack and stack pointer inspector."""
+
+    sp: reactive[int] = reactive(0xFFFF)
+    mem: reactive[dict[int, int]] = reactive(dict)
+    ram_size: reactive[int] = reactive(65536)
+
+    def render(self) -> Text:
+        t = Text()
+        t.append(f" CALL STACK (SP: 0x{self.sp:04X})\n", style="bold #00D2FF")
+
+        max_entries = 5
+        base_sp = self.ram_size - 1
+        depth = base_sp - self.sp
+
+        if depth <= 0:
+            t.append(
+                "  (Stack is currently empty - SP at top of RAM)\n", style="dim #555555"
+            )
+            return t
+
+        for i in range(min(max_entries, depth)):
+            addr = self.sp + 1 + i
+            val = self.mem.get(addr, 0)
+            tag = "TOS (Top of Stack)" if i == 0 else f"TOS+{i}"
+            t.append(f"  0x{addr:04X}: ", style="dim #888888")
+            t.append(f"0x{val:02X} ", style="bold #00FF87")
+            t.append(f"({val:>3}) ", style="#CCCCCC")
+            t.append(f"[{tag}]\n", style="dim #FFAA00")
+
+        if depth > max_entries:
+            t.append(
+                f"  ... and {depth - max_entries} more stack entries\n",
+                style="dim #666666",
+            )
+        return t
+
+
+class InstructionDetailWidget(Static):
+    """Deep-dive inspector displaying current instruction details, syntax, and effects."""
+
+    current_instr: reactive[str] = reactive("")
+    pc: reactive[int] = reactive(0)
+    sp: reactive[int] = reactive(0)
+    source_line: reactive[int] = reactive(-1)
+    source_text: reactive[str] = reactive("")
+
+    def render(self) -> Text:
+        t = Text()
+        t.append(" INSTRUCTION INSPECTOR & REFERENCE\n", style="bold #00D2FF")
+
+        if not self.current_instr:
+            t.append("  (No instruction executed yet)\n", style="dim #555555")
+            return t
+
+        parts = self.current_instr.split()
+        mnemonic = parts[0].upper() if parts else ""
+        doc = INSTRUCTION_DOCS.get(mnemonic, {})
+
+        name = doc.get("name", "Custom / Label")
+        syntax = doc.get("syntax", self.current_instr)
+        desc = doc.get("desc", "Executes CPU instruction step.")
+        flags = doc.get("flags", "None")
+
+        t.append("  Current: ", style="dim #888888")
+        t.append(f"{self.current_instr:<16} ", style="bold #FFFFFF")
+        t.append("PC: ", style="dim #888888")
+        t.append(f"0x{self.pc:04X} ", style="bold #00FF87")
+        t.append("SP: ", style="dim #888888")
+        t.append(f"0x{self.sp:04X}\n", style="bold #FFAA00")
+
+        t.append("  Name:    ", style="dim #888888")
+        t.append(f"{name} ", style="bold #00D2FF")
+        t.append(f"({syntax})\n", style="dim #AAAAAA")
+
+        t.append("  Action:  ", style="dim #888888")
+        t.append(f"{desc}\n", style="#CCCCCC")
+
+        t.append("  Flags:   ", style="dim #888888")
+        t.append(f"{flags}", style="bold #FFAA00")
+
+        if self.source_line >= 0 and self.source_text:
+            t.append("\n  Source:  ", style="dim #888888")
+            t.append(f"Line {self.source_line + 1}: ", style="bold #00FF87")
+            t.append(f"{self.source_text}", style="italic #AAAAAA")
+
+        return t
+
+
+class TelemetryWidget(Static):
+    """Real-time execution metrics and instruction distribution dashboard."""
+
+    total_steps: reactive[int] = reactive(0)
+    current_step: reactive[int] = reactive(0)
+    instr_counts: reactive[dict[str, int]] = reactive(dict)
+
+    def render(self) -> Text:
+        t = Text()
+        t.append(" EXECUTION TELEMETRY\n", style="bold #00D2FF")
+        t.append(
+            f"  Step Progress: {self.current_step}/{self.total_steps}\n",
+            style="#dddddd",
+        )
+
+        top_instr = Counter(self.instr_counts).most_common(5)
+        if top_instr:
+            t.append("  Top Instructions:\n", style="dim #888888")
+            max_c = max(c for _, c in top_instr) if top_instr else 1
+            for name, count in top_instr:
+                bar_len = int((count / max_c) * 14)
+                bar = "█" * bar_len
+                t.append(f"    {name:<5}: ", style="bold #FFAA00")
+                t.append(f"{bar:<14} ", style="#00FF87")
+                t.append(f"{count:>4}\n", style="dim #777777")
+        return t
+
+
+class CodeViewWidget(Static):
+    """Assembly and source line inspection with execution pointer and breakpoints."""
+
+    program: reactive[list[tuple[str, tuple]]] = reactive(list)
+    current_pc: reactive[int] = reactive(0)
+    source_lines: reactive[list[str]] = reactive(list)
+    pc_to_line: reactive[dict[int, int]] = reactive(dict)
+    breakpoints: reactive[set[int]] = reactive(set)
+
+    def render(self) -> Text:
+        t = Text()
+        t.append(" PROGRAM EXECUTION [b: toggle breakpoint]\n", style="bold #00D2FF")
+
+        window = 7
+        start = max(0, self.current_pc - window // 2)
+        end = min(len(self.program), start + window)
+
+        for pc in range(start, end):
+            is_current = pc == self.current_pc
+            has_bp = pc in self.breakpoints
+            instr, ops = self.program[pc]
+            ops_str = ", ".join(
+                f"R{op[1]}" if isinstance(op, tuple) and op[0] == "reg" else str(op)
+                for op in ops
+            )
+            line_str = f"0x{pc:04X}: {instr:<5} {ops_str}"
+
+            bp_marker = "● " if has_bp else "  "
+            bp_style = "bold #FF0055" if has_bp else "dim #444444"
+
+            t.append(bp_marker, style=bp_style)
+            if is_current:
+                t.append(f"▶ {line_str:<28}\n", style="bold black on #00D2FF")
+            else:
+                t.append(f"  {line_str:<28}\n", style="#FFFFFF")
+        return t
+
+
+def eval_condition(expr: str, regs: list[int], mem: dict[int, int]) -> bool:
+    """Safely evaluate debugger watch and conditional breakpoint expressions."""
+    expr = expr.strip()
+    match = re.match(r"^(.*?)\s*(==|!=|<=|>=|<|>)\s*(.*?)$", expr)
+    if not match:
+        r_m = re.match(r"^[rR](\d+)$", expr)
+        if r_m:
+            idx = int(r_m.group(1))
+            return bool(regs[idx]) if 0 <= idx < len(regs) else False
+        return False
+
+    left_str, op, right_str = match.groups()
+
+    def resolve(val_str: str) -> int:
+        val_str = val_str.strip()
+        r_m = re.match(r"^[rR](\d+)$", val_str)
+        if r_m:
+            r_idx = int(r_m.group(1))
+            return regs[r_idx] if 0 <= r_idx < len(regs) else 0
+        m_m = re.match(r"^mem\[(0x[0-9a-fA-F]+|\d+)\]$", val_str)
+        if m_m:
+            addr = (
+                int(m_m.group(1), 16)
+                if m_m.group(1).startswith("0x")
+                else int(m_m.group(1))
+            )
+            return mem.get(addr, 0)
+        return int(val_str, 16) if val_str.startswith("0x") else int(val_str)
+
+    try:
+        left = resolve(left_str)
+        right = resolve(right_str)
+        if op == "==":
+            return left == right
+        if op == "!=":
+            return left != right
+        if op == "<=":
+            return left <= right
+        if op == ">=":
+            return left >= right
+        if op == "<":
+            return left < right
+        if op == ">":
+            return left > right
+    except Exception:
+        return False
+    return False
+
+
+def extract_call_frames(
+    traces: list[dict[str, Any]], current_idx: int
+) -> list[dict[str, Any]]:
+    """Reconstruct active function call frames up to current trace index."""
+    frames: list[dict[str, Any]] = []
+    for i in range(min(current_idx + 1, len(traces))):
+        instr = traces[i].get("instr", "")
+        parts = instr.split()
+        if not parts:
+            continue
+        op = parts[0].upper()
+        if op in ("RCALL", "CALL") and len(parts) > 1:
+            target = parts[1]
+            frames.append(
+                {
+                    "func": target,
+                    "pc": traces[i].get("pc", 0),
+                    "sp": traces[i].get("sp", 0),
+                    "step": i,
+                }
+            )
+        elif op == "RET":
+            if frames:
+                frames.pop()
+    return frames
+
+
+class CVariablesWidget(Static):
+    """Live C variable table showing symbol names, addresses, and runtime values."""
+
+    var_symbols: reactive[dict[str, dict[str, Any]]] = reactive(dict)
+    mem: reactive[dict[int, int]] = reactive(dict)
+    prev_mem: reactive[dict[int, int]] = reactive(dict)
+
+    def render(self) -> Text:
+        t = Text()
+        t.append(" C VARIABLES (LIVE SYMBOL TABLE)\n", style="bold #00D2FF")
+        if not self.var_symbols:
+            t.append("  (No C variable symbols loaded)\n", style="dim #666666")
+            t.append(
+                "  Compile or run C code ('tiny8 <file.c>') to inspect variables\n",
+                style="dim #444444",
+            )
+            return t
+
+        t.append(
+            f"  {'VARIABLE':<12} {'TYPE':<6} {'ADDR':<8} {'HEX':<6} {'DEC':<6} {'STATUS'}\n",
+            style="bold #888888",
+        )
+        t.append(
+            f"  {'-' * 12} {'-' * 6} {'-' * 8} {'-' * 6} {'-' * 6} {'-' * 8}\n",
+            style="dim #444444",
+        )
+
+        for name, meta in sorted(
+            self.var_symbols.items(), key=lambda x: x[1].get("addr", 0)
+        ):
+            addr = meta.get("addr", 0)
+            vtype = meta.get("type", "int")
+            val = self.mem.get(addr, 0)
+            pval = self.prev_mem.get(addr, 0)
+            is_chg = val != pval
+
+            name_style = "bold #FFAA00" if is_chg else "bold #FFFFFF"
+            val_style = (
+                "bold black on #FFAA00"
+                if is_chg
+                else ("bold #00FF87" if val > 0 else "dim #555555")
+            )
+
+            t.append(f"  {name:<12} ", style=name_style)
+            t.append(f"{vtype:<6} ", style="#00D2FF")
+            t.append(f"0x{addr:04X}   ", style="dim #AAAAAA")
+            t.append(f"0x{val:02X}   ", style=val_style)
+            t.append(f"{val:>3}    ", style="#CCCCCC" if val > 0 else "dim #555555")
+            if is_chg:
+                t.append("UPDATED ◀\n", style="bold #FFAA00")
+            elif val > 0:
+                t.append("ACTIVE\n", style="dim #00FF87")
+            else:
+                t.append("ZERO\n", style="dim #444444")
+        return t
+
+
+class CallStackWidget(Static):
+    """Dynamic function backtrace reconstructed from execution calls and returns."""
+
+    frames: reactive[list[dict[str, Any]]] = reactive(list)
+    current_pc: reactive[int] = reactive(0)
+
+    def render(self) -> Text:
+        t = Text()
+        t.append(" FUNCTION CALL STACK (BACKTRACE)\n", style="bold #00D2FF")
+        if not self.frames:
+            t.append(
+                f"  #0  main() at PC:0x{self.current_pc:04X} (active frame)\n",
+                style="bold #00FF87",
+            )
+            return t
+
+        for i, frame in enumerate(reversed(self.frames)):
+            depth = len(self.frames) - i
+            fname = frame.get("func", "function")
+            call_pc = frame.get("pc", 0)
+            call_sp = frame.get("sp", 0)
+            is_top = i == 0
+            prefix = "▶ " if is_top else "  "
+            style = "bold #00FF87" if is_top else "#CCCCCC"
+            t.append(f"{prefix}#{depth}  {fname}() ", style=style)
+            t.append(
+                f"[called from PC:0x{call_pc:04X}, SP:0x{call_sp:04X}]\n",
+                style="dim #888888",
+            )
+
+        t.append("   #0  main() (root entry)\n", style="dim #666666")
+        return t
+
+
+class MemoryMatrixWidget(Static):
+    """2D RAM access heatmap showing read and write activity across addresses."""
+
+    mem: reactive[dict[int, int]] = reactive(dict)
+    read_counts: reactive[dict[int, int]] = reactive(dict)
+    write_counts: reactive[dict[int, int]] = reactive(dict)
+    base_addr: reactive[int] = reactive(0x60)
+
+    def render(self) -> Text:
+        t = Text()
+        end_matrix_addr = min(0xFFFF, self.base_addr + 127)
+        t.append(
+            f" 2D RAM ACCESS ACTIVITY MATRIX (0x{self.base_addr:04X}..0x{end_matrix_addr:04X})\n",
+            style="bold #00D2FF",
+        )
+        t.append(
+            "  Legend: [.] Untouched  [R] Read  [W] Write  [X] Read+Write (Hot)\n\n",
+            style="dim #888888",
+        )
+
+        t.append("         ", style="")
+        for c in range(16):
+            t.append(f" {c:X} ", style="dim #00D2FF")
+        t.append("\n")
+
+        for row in range(8):
+            row_start = self.base_addr + row * 16
+            if row_start > 0xFFFF:
+                break
+            t.append(f"  0x{row_start:04X}: ", style="bold #666666")
+            for col in range(16):
+                addr = row_start + col
+                if addr > 0xFFFF:
+                    break
+                rc = self.read_counts.get(addr, 0)
+                wc = self.write_counts.get(addr, 0)
+                val = self.mem.get(addr, 0)
+
+                if rc > 0 and wc > 0:
+                    t.append(" X ", style="bold black on #00D2FF")
+                elif wc > 0:
+                    t.append(" W ", style="bold black on #FFAA00")
+                elif rc > 0:
+                    t.append(" R ", style="bold black on #00FF87")
+                elif val > 0:
+                    t.append(" · ", style="bold #555555")
+                else:
+                    t.append(" . ", style="dim #222222")
+            t.append("\n")
+        return t
+
+
+class CacheProgressModalScreen(ModalScreen):
+    """Sleek modal dialog displaying a progress bar while precomputing cache checkpoints."""
+
+    CSS = """
+    CacheProgressModalScreen {
+        align: center middle;
+        background: rgba(0, 0, 0, 0.85);
+    }
+    #cache-dialog {
+        width: 76;
+        height: auto;
+        background: #000000;
+        border: solid #00D2FF;
+        padding: 1 2;
+    }
+    #cache-title {
+        text-align: center;
+        color: #00D2FF;
+        text-style: bold;
+        margin-bottom: 1;
+    }
+    #cache-status {
+        text-align: center;
+        color: #FFFFFF;
+        text-style: bold;
+        margin-bottom: 1;
+    }
+    #cache-detail {
+        text-align: center;
+        color: #888888;
+    }
+    ProgressBar {
+        margin: 1 0;
+    }
+    ProgressBar > .progress--bar {
+        color: #00FF87;
+        background: #1a1a1a;
+    }
+    ProgressBar > .progress--percentage {
+        color: #FFAA00;
+        text-style: bold;
+    }
+    """
+
+    def __init__(self, max_steps: int | None = None) -> None:
+        super().__init__()
+        self.target_steps = max_steps
+
+    def compose(self) -> ComposeResult:
+        """Compose modal progress bar widgets."""
+        with Vertical(id="cache-dialog"):
+            yield Label("PRECOMPUTING CACHE CHECKPOINTS", id="cache-title")
+            yield Label("Initializing CPU cache checkpoints...", id="cache-status")
+            yield ProgressBar(
+                id="cache-bar",
+                total=self.target_steps,
+                show_eta=bool(self.target_steps),
+            )
+            yield Label(
+                "Sparse CPU state snapshots cached for instant time-travel",
+                id="cache-detail",
+            )
+
+    def update_progress(self, current: int, total: int | None) -> None:
+        try:
+            bar = self.query_one("#cache-bar", ProgressBar)
+            lbl = self.query_one("#cache-status", Label)
+            if total is not None and total > 0:
+                bar.total = total
+                bar.update(progress=current)
+                pct = (current / max(1, total)) * 100
+                lbl.update(
+                    f"Caching execution: {current:,} / {total:,} steps ({pct:.1f}%)"
+                )
+            else:
+                bar.total = None
+                bar.update(progress=current)
+                lbl.update(
+                    f"Caching execution until infinite loop: {current:,} steps..."
+                )
+        except Exception:
+            pass
+
+
+class TUIHelpScreen(ModalScreen):
+    """Full-screen modal displaying TUI application usage, keyboard shortcuts, and guides."""
+
+    CSS = """
+    TUIHelpScreen {
+        align: center middle;
+        background: rgba(0, 0, 0, 0.85);
+    }
+    #help-dialog {
+        width: 85%;
+        height: 85%;
+        background: #000000;
+        border: solid #00D2FF;
+        padding: 1 2;
+    }
+    #help-title {
+        text-align: center;
+        color: #00D2FF;
+        text-style: bold;
+        margin-bottom: 1;
+    }
+    #help-scroll {
+        height: 1fr;
+    }
+    """
+
+    def compose(self) -> ComposeResult:
+        """Compose help screen dialog widgets."""
+        with Vertical(id="help-dialog"):
+            yield Label("TINY8 TUI APPLICATION USAGE & KEYBOARD GUIDE", id="help-title")
+            with VerticalScroll(id="help-scroll"):
+                t_text = Text()
+
+                t_text.append(
+                    "EXECUTION & TIME-TRAVEL CONTROLS\n", style="bold #00D2FF"
+                )
+                t_text.append("  n              ", style="bold #FFAA00")
+                t_text.append("Step forward 1 instruction (+1 step)\n", style="#FFFFFF")
+                t_text.append("  p              ", style="bold #FFAA00")
+                t_text.append(
+                    "Step backward 1 instruction (-1 step, Time-Travel debug)\n",
+                    style="#FFFFFF",
+                )
+                t_text.append("  Space          ", style="bold #FFAA00")
+                t_text.append(
+                    "Play / pause automatic continuous execution\n",
+                    style="#FFFFFF",
+                )
+                t_text.append("  c              ", style="bold #FFAA00")
+                t_text.append(
+                    "Continue forward until next breakpoint or program completion\n",
+                    style="#FFFFFF",
+                )
+                t_text.append("  C (Shift+c)    ", style="bold #FFAA00")
+                t_text.append(
+                    "Reverse continue backward until previous breakpoint or start\n",
+                    style="#FFFFFF",
+                )
+                t_text.append("  b              ", style="bold #FFAA00")
+                t_text.append(
+                    "Toggle breakpoint at current PC position\n", style="#FFFFFF"
+                )
+                t_text.append("  + / -          ", style="bold #FFAA00")
+                t_text.append(
+                    "Increase / decrease automatic playback execution speed\n",
+                    style="#FFFFFF",
+                )
+                t_text.append("  r              ", style="bold #FFAA00")
+                t_text.append(
+                    "Reset execution back to Step 0 (start)\n", style="#FFFFFF"
+                )
+                t_text.append("  q              ", style="bold #FFAA00")
+                t_text.append("Quit Tiny8 application\n\n", style="#FFFFFF")
+
+                t_text.append("INSPECTION & HELP MODALS\n", style="bold #00FF87")
+                t_text.append("  h  or  ?       ", style="bold #FFAA00")
+                t_text.append(
+                    "Open this TUI Application Usage & Keyboard Guide\n",
+                    style="#FFFFFF",
+                )
+                t_text.append("  i              ", style="bold #FFAA00")
+                t_text.append(
+                    "Inspect details of currently selected/executing instruction\n",
+                    style="#FFFFFF",
+                )
+                t_text.append("  j / k          ", style="bold #FFAA00")
+                t_text.append(
+                    "Scroll memory view down / up (J / K for fast scroll)\n",
+                    style="#FFFFFF",
+                )
+                t_text.append("  g              ", style="bold #FFAA00")
+                t_text.append(
+                    "Toggle Grayscale / Viridis color palette\n", style="#FFFFFF"
+                )
+                t_text.append("  x              ", style="bold #FFAA00")
+                t_text.append(
+                    "Toggle Hexadecimal digits (02X) / Graphic Pixel blocks\n",
+                    style="#FFFFFF",
+                )
+                t_text.append("  m              ", style="bold #FFAA00")
+                t_text.append(
+                    "Cycle view modes (Viridis+Hex -> Viridis+Pixel -> Grayscale+Pixel -> Grayscale+Hex)\n\n",
+                    style="#FFFFFF",
+                )
+
+                t_text.append("BUILT-IN VIM MODAL EDITOR\n", style="bold #FFAA00")
+                t_text.append("  e              ", style="bold #FFAA00")
+                t_text.append(
+                    "Launch full-screen Vim-style modal editor anytime\n",
+                    style="#FFFFFF",
+                )
+                t_text.append("  NORMAL Mode    ", style="bold #00D2FF")
+                t_text.append(
+                    "h/j/k/l movement, w/b word jump, 0/$ line bounds, gg/G top/bottom\n",
+                    style="#CCCCCC",
+                )
+                t_text.append("                 ", style="bold #00D2FF")
+                t_text.append(
+                    "x delete char, dd delete line, yy copy line, p paste, u undo, Ctrl+r redo\n",
+                    style="#CCCCCC",
+                )
+                t_text.append("  INSERT Mode    ", style="bold #00D2FF")
+                t_text.append(
+                    "Type 'i' / 'a' / 'o' to edit code, press <Esc> to return to normal mode\n",
+                    style="#CCCCCC",
+                )
+                t_text.append("  COMMAND Mode   ", style="bold #00D2FF")
+                t_text.append("Type ':' in normal mode:\n", style="#CCCCCC")
+                t_text.append(
+                    "                 :w [path]     Save code\n", style="dim #FFFFFF"
+                )
+                t_text.append(
+                    "                 :wq / :x      Save and return to debugger\n",
+                    style="dim #FFFFFF",
+                )
+                t_text.append(
+                    "                 :run          Compile / assemble and restart debugging\n",
+                    style="dim #FFFFFF",
+                )
+                t_text.append(
+                    "                 :q / :q!      Exit editor\n\n",
+                    style="dim #FFFFFF",
+                )
+
+                t_text.append("COMMAND BAR (:) SHORTCUTS\n", style="bold #FF007F")
+                t_text.append(
+                    "  Press ':' anytime from the debugger to enter commands:\n",
+                    style="#CCCCCC",
+                )
+                t_text.append("  :goto <step>       ", style="bold #FFAA00")
+                t_text.append("Jump directly to specific step index\n", style="#FFFFFF")
+                t_text.append("  :b <pc> [if expr]  ", style="bold #FFAA00")
+                t_text.append(
+                    "Set breakpoint at PC with optional condition (e.g. :b 0x0010 if R16 > 10)\n",
+                    style="#FFFFFF",
+                )
+                t_text.append("  :watch <target>    ", style="bold #FFAA00")
+                t_text.append(
+                    "Set watchpoint on register/memory (e.g. :watch R16 or :watch 0x0100)\n",
+                    style="#FFFFFF",
+                )
+                t_text.append("  :set <reg/addr> <val>", style="bold #FFAA00")
+                t_text.append(
+                    "Dynamically edit register or memory value (e.g. :set R16 42, :set 0x0100 255)\n",
+                    style="#FFFFFF",
+                )
+                t_text.append("  :mem <addr/name>   ", style="bold #FFAA00")
+                t_text.append(
+                    "Jump memory dump to address 0x0000..0xFFFF or alias (e.g. :mem 0x0600, :mem 0xFFFF, :mem vram, :mem stack)\n",
+                    style="#FFFFFF",
+                )
+                t_text.append("  :exec <asm>        ", style="bold #FFAA00")
+                t_text.append(
+                    "Dynamically execute an assembly instruction immediately (e.g. :exec LDI R16, 5)\n",
+                    style="#FFFFFF",
+                )
+                t_text.append("  :tab <name>        ", style="bold #FFAA00")
+                t_text.append(
+                    "Switch active tab (memory, cvars, callstack)\n",
+                    style="#FFFFFF",
+                )
+                t_text.append("  :rc                ", style="bold #FFAA00")
+                t_text.append("Run reverse continue\n", style="#FFFFFF")
+                t_text.append("  :h / :help / :?    ", style="bold #FFAA00")
+                t_text.append("Open this help guide\n", style="#FFFFFF")
+                t_text.append("  :i / :info / :instr", style="bold #FFAA00")
+                t_text.append(
+                    "Open current instruction detail modal\n\n", style="#FFFFFF"
+                )
+
+                t_text.append("PANELS & TABS OVERVIEW\n", style="bold #00FF87")
+                t_text.append(
+                    "  • Code View:       Source code disassembly with current execution pointer and breakpoints\n",
+                    style="#CCCCCC",
+                )
+                t_text.append(
+                    "  • Inspector:       Real-time breakdown of current instruction, operands, PC, SP\n",
+                    style="#CCCCCC",
+                )
+                t_text.append(
+                    "  • SREG Timeline:   Condition flags timeline history (Carry, Zero, Negative, etc.)\n",
+                    style="#CCCCCC",
+                )
+                t_text.append(
+                    "  • Registers:       General-purpose registers R0..R31 with change highlight bars\n",
+                    style="#CCCCCC",
+                )
+                t_text.append(
+                    "  • Memory:          32x32 Memory dump covering full 0x0000..0xFFFF RAM (including 0x0200..0x05FF VRAM)\n",
+                    style="#CCCCCC",
+                )
+                t_text.append(
+                    "  • C Variables:     Variable symbols table tracking types, memory addresses, values\n",
+                    style="#CCCCCC",
+                )
+                t_text.append(
+                    "  • Call Stack:      Reconstructed active function stack frames and return addresses\n",
+                    style="#CCCCCC",
+                )
+
+                yield Static(t_text)
+
+    def on_button_pressed(self, event: Button.Pressed) -> None:
+        self.dismiss()
+
+    def key_escape(self) -> None:
+        self.dismiss()
+
+    def key_enter(self) -> None:
+        self.dismiss()
+
+    def key_h(self) -> None:
+        self.dismiss()
+
+    def key_question_mark(self) -> None:
+        self.dismiss()
+
+
+class InstructionDetailModalScreen(ModalScreen):
+    """Full-screen modal displaying in-depth specifications for the currently selected instruction."""
+
+    CSS = """
+    InstructionDetailModalScreen {
+        align: center middle;
+        background: rgba(0, 0, 0, 0.85);
+    }
+    #detail-modal-dialog {
+        width: 85%;
+        height: 85%;
+        background: #000000;
+        border: solid #00FF87;
+        padding: 1 2;
+    }
+    #detail-modal-title {
+        text-align: center;
+        color: #00FF87;
+        text-style: bold;
+        margin-bottom: 1;
+    }
+    #detail-modal-scroll {
+        height: 1fr;
+    }
+    #detail-close-btn {
+        margin-top: 1;
+        dock: bottom;
+    }
+    """
+
+    def __init__(
+        self,
+        instr: str = "",
+        pc: int = 0,
+        sp: int = 0,
+        source_line: int = -1,
+        sreg: int = 0,
+    ) -> None:
+        super().__init__()
+        self.instr = instr
+        self.pc = pc
+        self.sp = sp
+        self.source_line = source_line
+        self.sreg = sreg
+
+    def compose(self) -> ComposeResult:
+        """Compose instruction detail modal widgets."""
+        with Vertical(id="detail-modal-dialog"):
+            yield Label(
+                "CURRENT INSTRUCTION SPECIFICATION & DETAILS",
+                id="detail-modal-title",
+            )
+            with VerticalScroll(id="detail-modal-scroll"):
+                t = Text()
+
+                parts = self.instr.strip().split() if self.instr else []
+                mnemonic = parts[0].upper() if parts else ""
+                doc = INSTRUCTION_DOCS.get(mnemonic, {})
+
+                t.append(
+                    "┌─ SELECTED INSTRUCTION EXECUTION CONTEXT ─────────────────────────────┐\n",
+                    style="bold #00D2FF",
+                )
+                t.append("│ Instruction : ", style="bold #00D2FF")
+                t.append(
+                    f"{self.instr if self.instr else '(None)':<24} ",
+                    style="bold #FFAA00",
+                )
+                t.append("PC : ", style="bold #00D2FF")
+                t.append(f"0x{self.pc:04X}  ", style="bold #00FF87")
+                t.append("SP : ", style="bold #00D2FF")
+                t.append(f"0x{self.sp:04X} │\n", style="bold #FFAA00")
+
+                line_str = f"Line {self.source_line}" if self.source_line > 0 else "N/A"
+                sreg_bits = f"0b{self.sreg:08b} (0x{self.sreg:02X})"
+                t.append("│ Source Line : ", style="bold #00D2FF")
+                t.append(f"{line_str:<24} ", style="#FFFFFF")
+                t.append("SREG: ", style="bold #00D2FF")
+                t.append(f"{sreg_bits:<20} │\n", style="dim #00FF87")
+                t.append(
+                    "└─────────────────────────────────────────────────────────────────────┘\n\n",
+                    style="bold #00D2FF",
+                )
+
+                if doc:
+                    name = doc.get("name", mnemonic)
+                    syntax = doc.get("syntax", self.instr)
+                    desc = doc.get("desc", "Executes CPU instruction step.")
+                    flags = doc.get("flags", "None")
+
+                    t.append("ARCHITECTURAL SPECIFICATION\n", style="bold #00FF87")
+                    t.append("  Mnemonic       : ", style="bold #FFAA00")
+                    t.append(f"{mnemonic}\n", style="bold #FFFFFF")
+                    t.append("  Instruction    : ", style="bold #FFAA00")
+                    t.append(f"{name}\n", style="bold #FFFFFF")
+                    t.append("  Syntax Pattern : ", style="bold #FFAA00")
+                    t.append(f"{syntax}\n", style="bold #00D2FF")
+                    t.append("  Operation      : ", style="bold #FFAA00")
+                    t.append(f"{desc}\n", style="#CCCCCC")
+                    t.append("  Flags Affected : ", style="bold #FFAA00")
+                    t.append(
+                        f"{flags}\n\n",
+                        style="bold #FF5555" if flags != "None" else "dim #888888",
+                    )
+
+                    t.append("SREG STATUS REGISTER BREAKDOWN\n", style="bold #FFAA00")
+                    flag_names = [
+                        (
+                            "C",
+                            "Carry",
+                            0,
+                            "Set if arithmetic operation generated a carry out of bit 7",
+                        ),
+                        ("Z", "Zero", 1, "Set if arithmetic/logic result is zero"),
+                        (
+                            "N",
+                            "Negative",
+                            2,
+                            "Set if MSB (bit 7) of result is set (signed negative)",
+                        ),
+                        (
+                            "V",
+                            "Overflow",
+                            3,
+                            "Set if two's complement signed overflow occurred",
+                        ),
+                        (
+                            "S",
+                            "Sign (N ⊕ V)",
+                            4,
+                            "Exclusive-OR of Negative and Overflow flags",
+                        ),
+                        (
+                            "H",
+                            "Half Carry",
+                            5,
+                            "Set if carry occurred from bit 3 to bit 4 (BCD arithmetic)",
+                        ),
+                        (
+                            "T",
+                            "Bit Copy",
+                            6,
+                            "Temporary storage bit for BST and BLD instructions",
+                        ),
+                        (
+                            "I",
+                            "Interrupt",
+                            7,
+                            "Global Interrupt Enable bit (SEI / CLI)",
+                        ),
+                    ]
+                    for code, fl_name, bit_idx, fl_desc in flag_names:
+                        is_active = bool(self.sreg & (1 << bit_idx))
+                        status_str = "[ACTIVE]" if is_active else "[CLEAR]"
+                        status_style = "bold #00FF87" if is_active else "dim #555555"
+                        is_affected = code in flags
+                        t.append(
+                            f"  [{code}] {fl_name:<11} {status_str} (Bit {bit_idx}) ",
+                            style=status_style,
+                        )
+                        if is_affected:
+                            t.append(
+                                "(Affected by this instruction)\n", style="bold #FFAA00"
+                            )
+                        else:
+                            t.append("\n")
+                        t.append(f"      {fl_desc}\n", style="dim #AAAAAA")
+                    t.append("\n")
+                else:
+                    t.append(
+                        "  (No built-in documentation found for this instruction/label)\n\n",
+                        style="dim #888888",
+                    )
+
+                t.append(
+                    "ALL TINY8 INSTRUCTIONS QUICK REFERENCE\n", style="bold #00D2FF"
+                )
+                for mn, d in sorted(INSTRUCTION_DOCS.items()):
+                    prefix = "▶ " if mn == mnemonic else "  "
+                    hl_style = "bold #00FF87" if mn == mnemonic else "bold #FFAA00"
+                    t.append(f"{prefix}{mn:<6} ", style=hl_style)
+                    t.append(f"[{d['syntax']}]", style="bold #00D2FF")
+                    t.append(f" - {d['name']}: {d['desc']}\n", style="#CCCCCC")
+
+                yield Static(t)
+            yield Button(
+                "Close (Esc / Enter)", id="detail-close-btn", variant="primary"
+            )
+
+    def on_button_pressed(self, event: Button.Pressed) -> None:
+        self.dismiss()
+
+    def key_escape(self) -> None:
+        self.dismiss()
+
+    def key_enter(self) -> None:
+        self.dismiss()
+
+
+class InstructionReferenceScreen(ModalScreen):
+    """Full-screen reference modal showing all instruction details."""
+
+    CSS = """
+    InstructionReferenceScreen {
+        align: center middle;
+        background: rgba(0, 0, 0, 0.85);
+    }
+    #modal-dialog {
+        width: 80%;
+        height: 80%;
+        background: #000000;
+        border: solid #00D2FF;
+        padding: 1 2;
+    }
+    #modal-title {
+        text-align: center;
+        color: #00D2FF;
+        text-style: bold;
+        margin-bottom: 1;
+    }
+    #modal-scroll {
+        height: 1fr;
+    }
+    #close-btn {
+        margin-top: 1;
+        dock: bottom;
+    }
+    """
+
+    def compose(self) -> ComposeResult:
+        """Compose instruction reference modal widgets."""
+        with Vertical(id="modal-dialog"):
+            yield Label("TINY8 INSTRUCTION SET REFERENCE", id="modal-title")
+            with VerticalScroll(id="modal-scroll"):
+                t = Text()
+                for mnemonic, doc in sorted(INSTRUCTION_DOCS.items()):
+                    t.append(f"{mnemonic:<6} ", style="bold #FFAA00")
+                    t.append(f"[{doc['syntax']}]", style="bold #00FF87")
+                    t.append(f" - {doc['name']}\n", style="bold #FFFFFF")
+                    t.append(f"       Operation: {doc['desc']}\n", style="#CCCCCC")
+                    t.append(
+                        f"       Flags:     {doc['flags']}\n\n", style="dim #00D2FF"
+                    )
+                yield Static(t)
+            yield Button("Close (Esc / Enter)", id="close-btn", variant="primary")
+
+    def on_button_pressed(self, event: Button.Pressed) -> None:
+        self.dismiss()
+
+    def key_escape(self) -> None:
+        self.dismiss()
+
+    def key_enter(self) -> None:
+        self.dismiss()
+
+
+DEFAULT_C_TEMPLATE = """int main() {
+    int a = 10;
+    int b = 20;
+    int sum = a + b;
+    return sum;
+}
+"""
+
+DEFAULT_ASM_TEMPLATE = """; Tiny8 Assembly Program
+LDI R16, 10
+LDI R17, 20
+ADD R16, R17
+"""
+
+
+class LazyStatusWidget(Static):
+    """Bottom statusline with mode badge, file stats, and help hint."""
+
+    mode: reactive[str] = reactive("NORMAL")
+    filename: reactive[str] = reactive("tiny8")
+    current_step: reactive[int] = reactive(0)
+    total_steps: reactive[int] = reactive(0)
+    current_pc: reactive[int] = reactive(0)
+    current_sp: reactive[int] = reactive(0)
+    current_instr: reactive[str] = reactive("")
+    sub_info: reactive[str] = reactive("")
+    hint: reactive[str] = reactive("h: help")
+
+    def render(self) -> Text:
+        right_hints = self.hint if self.hint else "h: help"
+        right_t = Text()
+        tokens = right_hints.split("  ")
+        for i, token in enumerate(tokens):
+            if i > 0:
+                right_t.append("  ")
+            parts = token.split(" ", 1)
+            if len(parts) == 2:
+                key_part, label_part = parts
+                right_t.append(key_part, style="bold #00D2FF")
+                right_t.append(" ")
+                right_t.append(label_part, style="#AAAAAA")
+            else:
+                right_t.append(token, style="dim #888888")
+
+        screen_width = self.size.width if self.size.width > 0 else 120
+        right_len = len(right_t.plain)
+
+        status_t = Text()
+        if "PLAY" in self.mode or self.mode in ("RUNNING", "INSERT"):
+            status_t.append(f" {self.mode} ", style="bold black on #00FF87")
+        elif "REV" in self.mode:
+            status_t.append(f" {self.mode} ", style="bold black on #00D2FF")
+        elif self.mode == "COMMAND":
+            status_t.append(f" {self.mode} ", style="bold black on #00D2FF")
+        elif self.mode == "BREAKPOINT":
+            status_t.append(f" {self.mode} ", style="bold black on #FF0055")
+        else:
+            status_t.append(f" {self.mode} ", style="bold black on #FABD2F")
+
+        status_t.append(" ")
+        status_t.append(f"{self.filename}", style="bold #FFFFFF")
+
+        if self.sub_info:
+            status_t.append(" | ", style="dim #555555")
+            status_t.append(f"{self.sub_info}", style="#CCCCCC")
+        else:
+            status_t.append(" | ", style="dim #555555")
+            status_t.append(f"Step: {self.current_step}", style="bold #00D2FF")
+            status_t.append(" | ", style="dim #555555")
+            status_t.append(f"PC: 0x{self.current_pc:04X}", style="bold #00FF87")
+            status_t.append(" | ", style="dim #555555")
+            status_t.append(f"SP: 0x{self.current_sp:04X}", style="bold #FFAA00")
+
+            if self.current_instr:
+                status_t.append(" | ", style="dim #555555")
+                status_t.append(f"{self.current_instr}", style="#E6EDF3")
+
+        cur_len = len(status_t.plain)
+        pad = max(2, screen_width - cur_len - right_len - 1)
+        status_t.append(" " * pad)
+        status_t.append_text(right_t)
+        return status_t
+
+
+class VimTextArea(TextArea):
+    """TextArea enhanced with Vim modal navigation and editing."""
+
+    mode: reactive[str] = reactive("NORMAL")
+    pending_key: str = ""
+    yanked_text: str = ""
+    is_modified: reactive[bool] = reactive(False)
+
+    def on_key(self, event: events.Key) -> None:
+        if self.mode == "INSERT":
+            if event.key == "escape":
+                self.mode = "NORMAL"
+                event.prevent_default()
+                event.stop()
+                if hasattr(self.screen, "update_editor_status"):
+                    self.screen.update_editor_status()
+            else:
+                self.is_modified = True
+                if hasattr(self.screen, "update_editor_status"):
+                    self.screen.update_editor_status()
+            return
+
+        if self.mode == "NORMAL":
+            key = event.character or event.key
+
+            if self.pending_key:
+                prefix = self.pending_key
+                self.pending_key = ""
+                if prefix == "d" and key == "d":
+                    self.action_delete_line()
+                    self.is_modified = True
+                    event.prevent_default()
+                    event.stop()
+                    if hasattr(self.screen, "update_editor_status"):
+                        self.screen.update_editor_status()
+                    return
+                elif prefix == "y" and key == "y":
+                    row, _ = self.cursor_location
+                    if row < len(self.document.lines):
+                        self.yanked_text = self.document.get_line(row)
+                    event.prevent_default()
+                    event.stop()
+                    return
+                elif prefix == "g" and key == "g":
+                    self.move_cursor((0, 0))
+                    event.prevent_default()
+                    event.stop()
+                    if hasattr(self.screen, "update_editor_status"):
+                        self.screen.update_editor_status()
+                    return
+
+            if event.key == "escape":
+                self.pending_key = ""
+                event.prevent_default()
+                event.stop()
+                return
+
+            if key in ("h", "left"):
+                self.action_cursor_left()
+                event.prevent_default()
+                event.stop()
+            elif key in ("j", "down"):
+                self.action_cursor_down()
+                event.prevent_default()
+                event.stop()
+            elif key in ("k", "up"):
+                self.action_cursor_up()
+                event.prevent_default()
+                event.stop()
+            elif key in ("l", "right"):
+                self.action_cursor_right()
+                event.prevent_default()
+                event.stop()
+            elif key == "w":
+                self.action_cursor_word_right()
+                event.prevent_default()
+                event.stop()
+            elif key == "b":
+                self.action_cursor_word_left()
+                event.prevent_default()
+                event.stop()
+            elif key == "0":
+                self.action_cursor_line_start()
+                event.prevent_default()
+                event.stop()
+            elif key == "$":
+                self.action_cursor_line_end()
+                event.prevent_default()
+                event.stop()
+            elif key == "G":
+                last_line = max(0, len(self.document.lines) - 1)
+                self.move_cursor((last_line, 0))
+                event.prevent_default()
+                event.stop()
+            elif key in ("g", "d", "y"):
+                self.pending_key = key
+                event.prevent_default()
+                event.stop()
+            elif key == "i":
+                self.mode = "INSERT"
+                event.prevent_default()
+                event.stop()
+            elif key == "a":
+                self.action_cursor_right()
+                self.mode = "INSERT"
+                event.prevent_default()
+                event.stop()
+            elif key == "I":
+                self.action_cursor_line_start()
+                self.mode = "INSERT"
+                event.prevent_default()
+                event.stop()
+            elif key == "A":
+                self.action_cursor_line_end()
+                self.mode = "INSERT"
+                event.prevent_default()
+                event.stop()
+            elif key == "o":
+                self.action_cursor_line_end()
+                self.insert("\n")
+                self.mode = "INSERT"
+                self.is_modified = True
+                event.prevent_default()
+                event.stop()
+            elif key == "O":
+                self.action_cursor_line_start()
+                self.insert("\n")
+                self.action_cursor_up()
+                self.mode = "INSERT"
+                self.is_modified = True
+                event.prevent_default()
+                event.stop()
+            elif key == "x":
+                self.action_delete_right()
+                self.is_modified = True
+                event.prevent_default()
+                event.stop()
+            elif key == "p":
+                if self.yanked_text:
+                    self.action_cursor_line_end()
+                    self.insert("\n" + self.yanked_text)
+                    self.is_modified = True
+                event.prevent_default()
+                event.stop()
+            elif key == "u":
+                self.action_undo()
+                event.prevent_default()
+                event.stop()
+            elif event.key == "ctrl+r":
+                self.action_redo()
+                event.prevent_default()
+                event.stop()
+            elif key in (":", "colon"):
+                if hasattr(self.screen, "action_open_vim_command"):
+                    self.screen.action_open_vim_command()
+                event.prevent_default()
+                event.stop()
+            else:
+                event.prevent_default()
+                event.stop()
+
+            if hasattr(self.screen, "update_editor_status"):
+                self.screen.update_editor_status()
+
+
+class VimEditorScreen(Screen):
+    """Full-screen modal Vim editor for creating and modifying C and ASM files."""
+
+    CSS = """
+    VimEditorScreen {
+        background: #000000;
+        color: #E6EDF3;
+    }
+    #editor-header {
+        height: 1;
+        dock: top;
+        background: #050505;
+        border-bottom: solid #222222;
+        padding: 0 1;
+    }
+    #vim-editor {
+        height: 1fr;
+        background: #000000;
+        border: none;
+    }
+    #vim-status {
+        dock: bottom;
+        height: 1;
+        background: #000000;
+        color: #E6EDF3;
+        padding: 0;
+        margin: 0 1;
+    }
+    #vim-cmd-bar {
+        dock: bottom;
+        height: 3;
+        background: #000000;
+        border-top: solid #00D2FF;
+        display: none;
+        padding: 0 1;
+        margin: 0;
+    }
+    #vim-cmd-prefix {
+        color: #00D2FF;
+        text-style: bold;
+        width: 2;
+        height: 1;
+        padding: 0;
+        margin: 0;
+    }
+    #vim-cmd-input {
+        background: #000000;
+        color: #00FF87;
+        border: none;
+        height: 1;
+        padding: 0;
+        margin: 0;
+        width: 1fr;
+    }
+    """
+
+    BINDINGS = [
+        Binding("escape", "handle_escape", "Normal Mode / Cancel"),
+        Binding("f5", "execute_run", "Run (Compile & Debug)", priority=True),
+    ]
+
+    def __init__(self, file_path: str = "main.c", initial_code: str = "") -> None:
+        super().__init__()
+        self.file_path = file_path
+        self.initial_code = initial_code
+        self.message = ""
+
+    def compose(self) -> ComposeResult:
+        """Compose widgets for the Vim editor screen."""
+        with Container(id="editor-header"):
+            yield Label(
+                "[bold #00D2FF]TINY8 VIM EDITOR[/] | [bold #FFAA00]:w[/] Save  "
+                "[bold #00FF87]:run[/] Debug  [bold #00D2FF]:q[/] Quit  [dim]'h'[/] Help"
+            )
+        yield VimTextArea(
+            text=self.initial_code,
+            theme="vscode_dark",
+            show_line_numbers=True,
+            id="vim-editor",
+        )
+        with Horizontal(id="vim-cmd-bar"):
+            yield Label(":", id="vim-cmd-prefix")
+            yield Input(placeholder="w, q, wq, run, e <file>", id="vim-cmd-input")
+        yield LazyStatusWidget(id="vim-status")
+
+    def on_mount(self) -> None:
+        text_area = self.query_one("#vim-editor", VimTextArea)
+        text_area.focus()
+        self.update_editor_status()
+
+    def update_editor_status(self) -> None:
+        try:
+            editor = self.query_one("#vim-editor", VimTextArea)
+            status = self.query_one("#vim-status", LazyStatusWidget)
+            status.mode = editor.mode
+            fname = Path(self.file_path).name
+            mod_tag = " [+]" if editor.is_modified else ""
+            status.filename = f"{fname}{mod_tag}"
+            row, col = editor.cursor_location
+            total_lines = len(editor.document.lines)
+            ftype = "C Source" if fname.endswith(".c") else "Assembly"
+            status.sub_info = (
+                f"[{ftype}] | Line {row + 1}, Col {col + 1} | {total_lines} lines"
+            )
+            if self.message:
+                status.sub_info = f"{status.sub_info} | {self.message}"
+            if editor.mode == "INSERT":
+                status.hint = "<Esc> Normal"
+            else:
+                status.hint = ":run Debug  :w Save  :q Quit  h Help"
+        except Exception:
+            pass
+
+    def action_open_vim_command(self) -> None:
+        self.query_one("#vim-status").styles.display = "none"
+        cmd_bar = self.query_one("#vim-cmd-bar")
+        cmd_bar.styles.display = "block"
+        cmd_input = self.query_one("#vim-cmd-input", Input)
+        cmd_input.value = ""
+        cmd_input.focus()
+
+    def action_handle_escape(self) -> None:
+        cmd_bar = self.query_one("#vim-cmd-bar")
+        if cmd_bar.styles.display != "none":
+            cmd_bar.styles.display = "none"
+            self.query_one("#vim-status").styles.display = "block"
+            self.query_one("#vim-editor").focus()
+            return
+        editor = self.query_one("#vim-editor", VimTextArea)
+        if editor.mode == "INSERT":
+            editor.mode = "NORMAL"
+            self.update_editor_status()
+
+    def on_input_submitted(self, event: Input.Submitted) -> None:
+        if event.input.id == "vim-cmd-input":
+            event.stop()
+            self.handle_vim_command(event.value.strip())
+
+    def handle_vim_command(self, raw_cmd: str) -> None:
+        cmd_bar = self.query_one("#vim-cmd-bar")
+        cmd_bar.styles.display = "none"
+        self.query_one("#vim-status").styles.display = "block"
+        editor = self.query_one("#vim-editor", VimTextArea)
+        editor.focus()
+
+        cmd = raw_cmd.lstrip(":")
+        if not cmd:
+            return
+
+        parts = cmd.split()
+        sub = parts[0].lower()
+
+        if sub in ("w", "write"):
+            target_file = parts[1] if len(parts) > 1 else self.file_path
+            self.save_file(target_file)
+        elif sub in ("q", "quit", "q!", "quit!"):
+            if editor.is_modified and not (cmd.endswith("!") or sub.endswith("!")):
+                self.message = (
+                    "[bold #FF0055]No write since last change (add ! to override)[/]"
+                )
+                self.update_editor_status()
+                return
+            if len(self.app.screen_stack) > 1:
+                self.app.pop_screen()
+            else:
+                self.app.exit()
+        elif sub in ("wq", "x"):
+            self.save_file(self.file_path)
+            self.action_execute_run()
+        elif sub in ("run", "r", "make"):
+            self.action_execute_run()
+        elif sub in ("e", "edit") and len(parts) > 1:
+            self.load_target_file(parts[1])
+        elif sub == "new":
+            new_name = parts[1] if len(parts) > 1 else "untitled.c"
+            self.file_path = new_name
+            editor.text = ""
+            editor.is_modified = False
+            self.message = f"[New File] {new_name}"
+            self.update_editor_status()
+        elif sub in ("h", "help", "?"):
+            self.app.push_screen(TUIHelpScreen())
+
+    def save_file(self, target_path: str) -> bool:
+        editor = self.query_one("#vim-editor", VimTextArea)
+        try:
+            Path(target_path).write_text(editor.text, encoding="utf-8")
+            self.file_path = target_path
+            editor.is_modified = False
+            lines = len(editor.document.lines)
+            self.message = f'[bold #00FF87]"{target_path}" {lines}L written[/]'
+            self.update_editor_status()
+            return True
+        except Exception as e:
+            self.message = f"[bold #FF0055]Error saving: {e}[/]"
+            self.update_editor_status()
+            return False
+
+    def load_target_file(self, target_path: str) -> None:
+        editor = self.query_one("#vim-editor", VimTextArea)
+        p = Path(target_path)
+        if p.exists():
+            editor.text = p.read_text(encoding="utf-8")
+            self.message = f'"{target_path}" loaded'
+        else:
+            editor.text = ""
+            self.message = f'[New File] "{target_path}"'
+        self.file_path = target_path
+        editor.is_modified = False
+        self.update_editor_status()
+
+    def action_execute_run(self) -> None:
+        editor = self.query_one("#vim-editor", VimTextArea)
+        self.save_file(self.file_path)
+        code = editor.text
+
+        try:
+            if self.file_path.endswith(".c"):
+                asm_src, symbols = compile_c_with_symbols(code)
+                asm = assemble(asm_src)
+                src_lines = code.splitlines()
+                if hasattr(self.app, "var_symbols"):
+                    self.app.var_symbols = symbols
+            else:
+                asm = assemble(code)
+                src_lines = code.splitlines()
+                if hasattr(self.app, "var_symbols"):
+                    self.app.var_symbols = {}
+
+            cpu = CPU()
+            cpu.load_program(asm)
+            cpu.source_lines = src_lines
+            cpu.pc_to_line = asm.pc_to_line
+            max_steps = getattr(self.app, "max_steps", None)
+
+            # Precompute checkpoint cache before execution starts
+            mgr = CheckpointManager(cpu, interval=100)
+            computed = mgr.precompute(max_steps=max_steps)
+
+            init_steps = min(1000, computed)
+            mgr.restore_exact_step(0)
+            cpu.run(max_steps=init_steps, show_progress=False)
+
+            self.app.cpu = cpu
+            self.app.checkpoint_manager = mgr
+            self.app.execution_mode = "cache"
+            self.app.traces = list(cpu.step_trace)
+            self.app.num_traces = len(cpu.step_trace)
+            self.app.current_idx = 0
+            self.app.file_path = self.file_path
+            self.app.title_text = Path(self.file_path).name
+
+            code_w = self.app.query_one("#code-view", CodeViewWidget)
+            code_w.program = cpu.program
+            code_w.source_lines = cpu.source_lines
+            code_w.pc_to_line = cpu.pc_to_line
+            self.app.update_views()
+
+            if len(self.app.screen_stack) > 1:
+                self.app.pop_screen()
+        except Exception as err:
+            self.message = f"[bold #FF0055]Build error: {err}[/]"
+            self.update_editor_status()
+
+
+class Tiny8App(App):
+    """Textual application with OLED black background and advanced debugger features."""
+
+    TITLE = "Tiny8"
+
+    CSS = """
+    Screen {
+        background: #000000;
+        color: #E6EDF3;
+    }
+    Header {
+        background: #000000;
+        color: #00D2FF;
+        text-style: bold;
+        border-bottom: solid #222222;
+    }
+    #sreg-view {
+        height: auto;
+        padding: 0;
+        margin: 1 0;
+        width: 1fr;
+    }
+    #main-container {
+        layout: horizontal;
+        height: 1fr;
+        margin: 0 1;
+    }
+    #left-panel {
+        width: 1fr;
+        height: 1fr;
+        border: solid #222222;
+        background: #000000;
+        margin-right: 1;
+        padding: 1;
+        overflow-y: auto;
+    }
+    #right-panel {
+        width: 1fr;
+        height: 1fr;
+        border: solid #222222;
+        background: #000000;
+        padding: 1;
+        overflow-y: auto;
+    }
+    #lazy-status {
+        dock: bottom;
+        height: 1;
+        background: #000000;
+        color: #E6EDF3;
+        padding: 0;
+        margin: 0 1;
+    }
+    #command-bar {
+        dock: bottom;
+        height: 3;
+        background: #000000;
+        border-top: solid #00D2FF;
+        display: none;
+        padding: 0 1;
+        margin: 0;
+    }
+    #cmd-prefix {
+        color: #00D2FF;
+        text-style: bold;
+        width: 2;
+        height: 1;
+        padding: 0;
+        margin: 0;
+    }
+    #cmd-input {
+        background: #000000;
+        color: #00FF87;
+        border: none;
+        height: 1;
+        padding: 0;
+        margin: 0;
+        width: 1fr;
+    }
+    TabbedContent {
+        height: 1fr;
+    }
+    TabPane {
+        padding: 0;
+        background: #000000;
+    }
+    Static {
+        margin-bottom: 1;
+    }
+    """
+
+    BINDINGS = [
+        Binding("space", "toggle_play", "Play Forward"),
+        Binding("shift+space", "toggle_reverse_play", "Play Reverse"),
+        Binding("backspace", "toggle_reverse_play", "Play Reverse"),
+        Binding("n", "step_forward", "Step +1"),
+        Binding("p", "step_backward", "Step -1"),
+        Binding("c", "continue_run", "Continue (to Breakpoint)"),
+        Binding("shift+c", "reverse_continue", "Rev Continue"),
+        Binding("C", "reverse_continue", "Rev Continue"),
+        Binding("b", "toggle_breakpoint", "Toggle Breakpoint"),
+        Binding("j", "scroll_down", "Scroll Down"),
+        Binding("k", "scroll_up", "Scroll Up"),
+        Binding("shift+j", "scroll_page_down", "Page Down", show=False),
+        Binding("J", "scroll_page_down", "Page Down", show=False),
+        Binding("shift+k", "scroll_page_up", "Page Up", show=False),
+        Binding("K", "scroll_page_up", "Page Up", show=False),
+        Binding("pagedown", "scroll_page_down", "Page Down", show=False),
+        Binding("pageup", "scroll_page_up", "Page Up", show=False),
+        Binding("colon", "open_command", "Command (:)"),
+        Binding(":", "open_command", "Command (:)"),
+        Binding("shift+semicolon", "open_command", "Command (:)"),
+        Binding("e", "open_editor", "Vim Editor"),
+        Binding("r", "reset", "Reset"),
+        Binding("h", "show_help", "Help"),
+        Binding("question_mark", "show_help", "Help"),
+        Binding("?", "show_help", "Help"),
+        Binding("i", "show_instruction_detail", "Instruction Detail"),
+        Binding("escape", "cancel_command", "Cancel Command"),
+        Binding("+", "faster", "Speed +"),
+        Binding("-", "slower", "Speed -"),
+        Binding("g", "toggle_grayscale", "Grayscale/Viridis"),
+        Binding("x", "toggle_hex", "Hex/Pixel"),
+        Binding("m", "cycle_mode", "Cycle View Mode"),
+        Binding("q", "quit", "Quit"),
+    ]
+
+    current_idx: reactive[int] = reactive(0)
+    playing: reactive[bool] = reactive(False)
+    play_direction: reactive[int] = reactive(1)
+    playback_rate_idx: reactive[int] = reactive(0)
+    speed_ms: reactive[int] = reactive(100)
+    batch_size: reactive[int] = reactive(1)
+    execution_mode: reactive[str] = reactive("cache")
+    breakpoints: reactive[set[int]] = reactive(set)
+    mem_start: reactive[int] = reactive(0x60)
+    reg_start: reactive[int] = reactive(0)
+    color_mode: reactive[str] = reactive("viridis")
+    show_hex: reactive[bool] = reactive(True)
+
+    def __init__(
+        self,
+        cpu: CPU | None = None,
+        title_text: str = "Tiny8 Debugger",
+        file_path: str = "main.c",
+        start_in_editor: bool = False,
+        max_steps: int | None = None,
+        var_symbols: dict[str, dict[str, Any]] | None = None,
+        checkpoint_manager: CheckpointManager | None = None,
+        execution_mode: str = "cache",
+        precompute_cache: bool = True,
+        show_cache_progress: bool = False,
+    ) -> None:
+        super().__init__()
+        self.file_path = file_path
+        self.start_in_editor = start_in_editor
+        self.max_steps = max_steps
+        self.show_cache_progress = show_cache_progress
+        self.precompute_cache = precompute_cache
+        self.var_symbols: dict[str, dict[str, Any]] = var_symbols or {}
+        self.conditional_breakpoints: dict[int, str] = {}
+        self.watchpoints: set[str] = set()
+        self.bookmarks: dict[str, int] = {}
+        self.execution_mode = execution_mode
+        if cpu is not None:
+            self.cpu = cpu
+            self.traces = list(cpu.step_trace)[-1000:]
+        else:
+            self.cpu = CPU()
+            self.traces = []
+        self.num_traces = len(self.traces)
+
+        if checkpoint_manager is not None:
+            self.checkpoint_manager = checkpoint_manager
+        else:
+            self.checkpoint_manager = CheckpointManager(self.cpu, interval=100)
+            if (
+                precompute_cache
+                and self.cpu.program
+                and not self.start_in_editor
+                and not show_cache_progress
+            ):
+                if self.cpu.step_count == 0:
+                    computed = self.checkpoint_manager.precompute(
+                        max_steps=self.max_steps
+                    )
+                    self.checkpoint_manager.restore_exact_step(0)
+                    init_steps = min(
+                        1000,
+                        self.max_steps if self.max_steps is not None else computed,
+                    )
+                    self.cpu.run(max_steps=init_steps, show_progress=False)
+                    self.traces = list(self.cpu.step_trace)
+                    self.num_traces = len(self.traces)
+                elif self.cpu.step_trace:
+                    for tr in self.cpu.step_trace:
+                        st = tr.get("step", 0)
+                        if st % self.checkpoint_manager.interval == 0:
+                            if st not in self.checkpoint_manager.snapshots:
+                                self.checkpoint_manager.snapshots[st] = {
+                                    "step": st,
+                                    "pc": tr.get("pc", 0),
+                                    "sp": tr.get("sp", self.cpu.mem.ram_size - 1),
+                                    "sreg": tr.get("sreg", 0),
+                                    "regs": list(tr.get("regs", [0] * 32)),
+                                    "mem": dict(tr.get("mem", {})),
+                                    "running": True,
+                                }
+                                if st not in self.checkpoint_manager.checkpoint_steps:
+                                    idx = bisect.bisect_right(
+                                        self.checkpoint_manager.checkpoint_steps, st
+                                    )
+                                    self.checkpoint_manager.checkpoint_steps.insert(
+                                        idx, st
+                                    )
+
+        self.title_text = Path(file_path).name if file_path else title_text
+        self.timer: Any = None
+        if self.file_path and any(
+            k in self.file_path.lower()
+            for k in ("diffusion", "mnist", "heatmap", "vram")
+        ):
+            self.mem_start = 0x0200
+
+    def on_key(self, event: events.Key) -> None:
+        if len(self.screen_stack) > 1:
+            return
+        cmd_bar = self.query_one("#command-bar")
+        if cmd_bar.styles.display != "none":
+            return
+        if (
+            event.key in (":", "colon", "shift+colon", "shift+semicolon")
+            or event.character == ":"
+        ):
+            self.action_open_command()
+            event.prevent_default()
+            event.stop()
+            return
+
+    def compose(self) -> ComposeResult:
+        """Compose the root application layout and widgets."""
+        yield Header(show_clock=True)
+        with Horizontal(id="main-container"):
+            with Vertical(id="left-panel"):
+                yield CodeViewWidget(id="code-view")
+                yield InstructionDetailWidget(id="detail-view")
+                yield SregWidget(id="sreg-view")
+                yield BtopRegistersWidget(id="btop-regs-view")
+            with Vertical(id="right-panel"):
+                with TabbedContent():
+                    with TabPane("Memory", id="tab-btop"):
+                        yield MemoryWidget(id="mem-view")
+                    with TabPane("C Variables", id="tab-cvars"):
+                        yield CVariablesWidget(id="cvars-view")
+                    with TabPane("Call Stack", id="tab-callstack"):
+                        yield CallStackWidget(id="callstack-view")
+        with Horizontal(id="command-bar"):
+            yield Label(":", id="cmd-prefix")
+            yield Input(
+                placeholder="goto <step/mark>, b <pc> [if expr], watch <var>, rc, set R0 5, exec <asm>",
+                id="cmd-input",
+            )
+        yield LazyStatusWidget(id="lazy-status")
+
+    def on_mount(self) -> None:
+        code_widget = self.query_one("#code-view", CodeViewWidget)
+        code_widget.program = self.cpu.program
+        code_widget.source_lines = self.cpu.source_lines
+        code_widget.pc_to_line = self.cpu.pc_to_line
+        self.update_views()
+        if self.start_in_editor:
+            self.action_open_editor()
+        elif (
+            self.show_cache_progress
+            and self.cpu.program
+            and len(self.checkpoint_manager.checkpoint_steps) <= 1
+        ):
+            self._start_cache_precompute_with_progress()
+
+    def _start_cache_precompute_with_progress(self) -> None:
+        """Launch visual progress modal and run cache precomputation in background worker thread."""
+        modal = CacheProgressModalScreen(max_steps=self.max_steps)
+        self.push_screen(modal)
+        self.run_worker(self._worker_precompute_cache, thread=True)
+
+    def _worker_precompute_cache(self) -> None:
+        def on_prog(cur: int, tot: int | None) -> None:
+            self.call_from_thread(self._on_cache_progress_update, cur, tot)
+
+        computed = self.checkpoint_manager.precompute(
+            max_steps=self.max_steps, progress_callback=on_prog
+        )
+        self.checkpoint_manager.restore_exact_step(0)
+        init_steps = min(
+            1000, self.max_steps if self.max_steps is not None else computed
+        )
+        self.cpu.run(max_steps=init_steps, show_progress=False)
+        self.traces = list(self.cpu.step_trace)
+        self.num_traces = len(self.traces)
+        self.current_idx = 0
+        self.call_from_thread(self._on_cache_precompute_done, computed)
+
+    def _on_cache_progress_update(self, current: int, total: int | None) -> None:
+        if isinstance(self.screen, CacheProgressModalScreen):
+            self.screen.update_progress(current, total)
+
+    def _on_cache_precompute_done(self, computed: int) -> None:
+        if isinstance(self.screen, CacheProgressModalScreen):
+            self.screen.dismiss()
+        self.update_views()
+        loop_msg = (
+            f" ({self.checkpoint_manager.loop_reason})"
+            if self.checkpoint_manager.infinite_loop_detected
+            else ""
+        )
+        self.notify(
+            f"Cache precomputation completed: {computed:,} steps cached{loop_msg}",
+            timeout=3.0,
+        )
+
+    def action_open_editor(self) -> None:
+        """Open full-screen Vim editor for source code."""
+        code = ""
+        p = Path(self.file_path)
+        if p.exists():
+            code = p.read_text(encoding="utf-8")
+        elif self.cpu.source_lines:
+            code = "\n".join(self.cpu.source_lines)
+        else:
+            code = (
+                DEFAULT_C_TEMPLATE
+                if self.file_path.endswith(".c")
+                else DEFAULT_ASM_TEMPLATE
+            )
+        self.push_screen(VimEditorScreen(file_path=self.file_path, initial_code=code))
+
+    def update_views(self) -> None:
+        if (
+            not getattr(self, "_screen_stack", None)
+            or not self.traces
+            or not (0 <= self.current_idx < self.num_traces)
+        ):
+            return
+
+        entry = self.traces[self.current_idx]
+        prev = self.traces[self.current_idx - 1] if self.current_idx > 0 else None
+
+        sreg_widget = self.query_one("#sreg-view", SregWidget)
+        sreg_widget.sreg = entry.get("sreg", 0)
+
+        btop_regs = self.query_one("#btop-regs-view", BtopRegistersWidget)
+        btop_regs.prev_regs = (
+            prev.get("regs", entry.get("regs", [0] * 32))
+            if prev
+            else entry.get("regs", [0] * 32)
+        )
+        btop_regs.regs = entry.get("regs", [0] * 32)
+        btop_regs.start_r = self.reg_start
+
+        try:
+            regs_widget = self.query_one("#regs-view", RegistersWidget)
+            regs_widget.prev_regs = (
+                prev.get("regs", entry.get("regs", [0] * 32))
+                if prev
+                else entry.get("regs", [0] * 32)
+            )
+            regs_widget.regs = entry.get("regs", [0] * 32)
+        except Exception:
+            pass
+
+        mem_widget = self.query_one("#mem-view", MemoryWidget)
+        mem_widget.prev_mem = (
+            prev.get("mem", entry.get("mem", {})) if prev else entry.get("mem", {})
+        )
+        mem_widget.mem = entry.get("mem", {})
+        mem_widget.start_addr = self.mem_start
+        mem_widget.color_mode = getattr(self, "color_mode", "viridis")
+        mem_widget.show_hex = getattr(self, "show_hex", True)
+
+        try:
+            cvars_widget = self.query_one("#cvars-view", CVariablesWidget)
+            cvars_widget.var_symbols = getattr(self, "var_symbols", {})
+            cvars_widget.mem = entry.get("mem", {})
+            cvars_widget.prev_mem = (
+                prev.get("mem", entry.get("mem", {})) if prev else entry.get("mem", {})
+            )
+        except Exception:
+            pass
+
+        try:
+            callstack_widget = self.query_one("#callstack-view", CallStackWidget)
+            callstack_widget.frames = extract_call_frames(self.traces, self.current_idx)
+            callstack_widget.current_pc = entry.get("pc", 0)
+        except Exception:
+            pass
+
+        try:
+            matrix_widget = self.query_one("#matrix-view", MemoryMatrixWidget)
+            matrix_widget.mem = entry.get("mem", {})
+            matrix_widget.base_addr = self.mem_start
+            wc: Counter[int] = Counter()
+            rc: Counter[int] = Counter()
+            start_i = max(0, self.current_idx - 200)
+            for i in range(start_i, self.current_idx + 1):
+                cur_e = self.traces[i]
+                prv_e = self.traces[i - 1] if i > 0 else None
+                c_m = cur_e.get("mem", {})
+                p_m = prv_e.get("mem", {}) if prv_e else {}
+                for a, v in c_m.items():
+                    if p_m.get(a) != v:
+                        wc[a] += 1
+                instr = cur_e.get("instr", "")
+                if instr:
+                    op = instr.split()[0].upper()
+                    if op in ("LD", "LDS", "LDD", "POP", "RET"):
+                        rc[cur_e.get("sp", 0)] += 1
+            matrix_widget.write_counts = dict(wc)
+            matrix_widget.read_counts = dict(rc)
+        except Exception:
+            pass
+
+        try:
+            stack_w = self.query_one("#stack-view-grid", StackWidget)
+            stack_w.sp = entry.get("sp", self.cpu.mem.ram_size - 1)
+            stack_w.mem = entry.get("mem", {})
+            stack_w.ram_size = self.cpu.mem.ram_size
+        except Exception:
+            pass
+
+        code_widget = self.query_one("#code-view", CodeViewWidget)
+        code_widget.current_pc = entry.get("pc", 0)
+        code_widget.breakpoints = set(self.breakpoints)
+
+        detail_widget = self.query_one("#detail-view", InstructionDetailWidget)
+        detail_widget.current_instr = entry.get("instr", "")
+        detail_widget.pc = entry.get("pc", 0)
+        detail_widget.sp = entry.get("sp", 0)
+        source_line_idx = entry.get("source_line", -1)
+        detail_widget.source_line = source_line_idx
+        if 0 <= source_line_idx < len(self.cpu.source_lines) and self.cpu.source_lines:
+            detail_widget.source_text = self.cpu.source_lines[source_line_idx].strip()
+        else:
+            detail_widget.source_text = ""
+
+        # Determine actual execution step number and total count from trace entry or CPU state
+        actual_step = (
+            entry.get("step", self.cpu.step_count if self.cpu else self.current_idx + 1)
+            if entry
+            else (self.cpu.step_count if self.cpu else self.current_idx)
+        )
+        total_steps = max(self.cpu.step_count if self.cpu else 0, self.num_traces)
+
+        try:
+            telemetry_widget = self.query_one("#telemetry-view", TelemetryWidget)
+            telemetry_widget.total_steps = total_steps
+            telemetry_widget.current_step = actual_step
+            counts: Counter[str] = Counter()
+            for i in range(self.current_idx + 1):
+                instr_str = self.traces[i].get("instr", "")
+                if instr_str:
+                    counts[instr_str.split()[0]] += 1
+            telemetry_widget.instr_counts = dict(counts)
+        except Exception:
+            pass
+
+        try:
+            lazy_status = self.query_one("#lazy-status", LazyStatusWidget)
+            if self.current_idx in self.breakpoints:
+                lazy_status.mode = "BREAKPOINT"
+            elif self.playing:
+                rate = (
+                    PLAYBACK_RATES[self.playback_rate_idx] if self.speed_ms <= 30 else 1
+                )
+                tag = f"x{rate:,}" if self.speed_ms <= 30 else f"{self.speed_ms}ms"
+                if self.play_direction == 1:
+                    lazy_status.mode = f"PLAY ▶ {tag}"
+                else:
+                    lazy_status.mode = f"REV ◀ {tag}"
+            else:
+                tag = "CACHE" if self.execution_mode == "cache" else "LIVE"
+                lazy_status.mode = f"NORMAL ({tag})"
+            lazy_status.filename = self.title_text
+            lazy_status.current_step = actual_step
+            lazy_status.total_steps = total_steps
+            lazy_status.current_pc = entry.get("pc", 0)
+            lazy_status.current_sp = entry.get("sp", 0)
+            lazy_status.current_instr = entry.get("instr", "")
+        except Exception:
+            pass
+
+    def action_step_forward(self) -> None:
+        if self.current_idx < self.num_traces - 1:
+            self.current_idx += 1
+            self.update_views()
+        elif self.cpu and self.cpu.running:
+            self.cpu.step()
+            self.traces = list(self.cpu.step_trace)
+            self.num_traces = len(self.traces)
+            self.current_idx = max(0, self.num_traces - 1)
+            self.update_views()
+
+    def action_step_backward(self) -> None:
+        if self.current_idx > 0:
+            self.current_idx -= 1
+            self.update_views()
+
+    def action_toggle_breakpoint(self) -> None:
+        """Toggle breakpoint on current PC."""
+        if not self.traces or not (0 <= self.current_idx < self.num_traces):
+            return
+        cur_pc = self.traces[self.current_idx].get("pc", 0)
+        if cur_pc in self.breakpoints:
+            self.breakpoints.remove(cur_pc)
+            self.conditional_breakpoints.pop(cur_pc, None)
+        else:
+            self.breakpoints.add(cur_pc)
+        self.update_views()
+
+    def _is_breakpoint_hit(self, step_idx: int) -> bool:
+        if not (0 <= step_idx < self.num_traces):
+            return False
+        entry = self.traces[step_idx]
+        pc = entry.get("pc", 0)
+        if pc in self.breakpoints:
+            cond = self.conditional_breakpoints.get(pc)
+            if not cond:
+                return True
+            regs = entry.get("regs", [0] * 32)
+            mem = entry.get("mem", {})
+            return eval_condition(cond, regs, mem)
+        return False
+
+    def _check_watchpoints_triggered(self, step_idx: int) -> bool:
+        if not self.watchpoints or step_idx <= 0 or step_idx >= self.num_traces:
+            return False
+        cur = self.traces[step_idx]
+        prev = self.traces[step_idx - 1]
+        regs = cur.get("regs", [0] * 32)
+        prev_regs = prev.get("regs", [0] * 32)
+        mem = cur.get("mem", {})
+        prev_mem = prev.get("mem", {})
+        for wp in self.watchpoints:
+            m_r = re.match(r"^[rR](\d+)$", wp.strip())
+            if m_r:
+                ridx = int(m_r.group(1))
+                if 0 <= ridx < len(regs) and regs[ridx] != prev_regs[ridx]:
+                    return True
+                continue
+            m_m = re.match(r"^(?:mem\[)?(0x[0-9a-fA-F]+|\d+)\]?$", wp.strip())
+            if m_m:
+                addr = (
+                    int(m_m.group(1), 16)
+                    if m_m.group(1).startswith("0x")
+                    else int(m_m.group(1))
+                )
+                if mem.get(addr, 0) != prev_mem.get(addr, 0):
+                    return True
+                continue
+            if eval_condition(wp, regs, mem):
+                if not eval_condition(wp, prev_regs, prev_mem):
+                    return True
+        return False
+
+    def action_continue_run(self) -> None:
+        """Run forward until next breakpoint, watchpoint, or program completion."""
+        next_step = self.current_idx + 1
+        while next_step < self.num_traces:
+            if self._is_breakpoint_hit(next_step) or self._check_watchpoints_triggered(
+                next_step
+            ):
+                self.current_idx = next_step
+                self.update_views()
+                return
+            next_step += 1
+        self.current_idx = self.num_traces - 1
+        self.update_views()
+
+    def action_reverse_continue(self) -> None:
+        """Run backward until previous breakpoint, watchpoint, or program start."""
+        prev_step = self.current_idx - 1
+        while prev_step >= 0:
+            if self._is_breakpoint_hit(prev_step) or self._check_watchpoints_triggered(
+                prev_step
+            ):
+                self.current_idx = prev_step
+                self.update_views()
+                return
+            prev_step -= 1
+        self.current_idx = 0
+        self.update_views()
+
+    def action_exec_instruction(self, instr_str: str) -> None:
+        """Execute an assembly instruction dynamically in REPL mode."""
+        try:
+            asm_res = assemble(instr_str)
+            if not asm_res.program:
+                return
+            cur = self.traces[self.current_idx]
+            self.cpu.regs = list(cur.get("regs", [0] * 32))
+            self.cpu.sreg = cur.get("sreg", 0)
+            self.cpu.sp = cur.get("sp", self.cpu.mem.ram_size - 1)
+            for a, v in cur.get("mem", {}).items():
+                self.cpu.mem.ram[a] = v
+            self.cpu.load_program(asm_res)
+            self.cpu.running = True
+            self.cpu.step()
+            if self.cpu.step_trace:
+                self.cpu.step_trace.pop()
+
+            new_entry = {
+                "step": self.num_traces + 1,
+                "pc": cur.get("pc", 0),
+                "instr": f"[REPL] {instr_str}",
+                "regs": list(self.cpu.regs),
+                "mem": {i: v for i, v in enumerate(self.cpu.mem.ram) if v != 0},
+                "sreg": self.cpu.sreg,
+                "sp": self.cpu.sp,
+                "source_line": -1,
+            }
+            self.traces.insert(self.current_idx + 1, new_entry)
+            self.num_traces = len(self.traces)
+            self.current_idx += 1
+            self.update_views()
+        except Exception:
+            pass
+
+    def watch_mem_start(self, new_val: int) -> None:
+        """Update only the memory widget when mem_start changes."""
+        try:
+            mem_widget = self.query_one("#mem-view", MemoryWidget)
+            mem_widget.start_addr = new_val
+        except Exception:
+            pass
+        try:
+            matrix_widget = self.query_one("#matrix-view", MemoryMatrixWidget)
+            matrix_widget.base_addr = new_val
+        except Exception:
+            pass
+
+    def action_scroll_down(self) -> None:
+        """Scroll memory down (1 row = 32 bytes)."""
+        self.mem_start = min(0xFFE0, self.mem_start + 32)
+
+    def action_scroll_up(self) -> None:
+        """Scroll memory up (1 row = 32 bytes)."""
+        self.mem_start = max(0x0000, self.mem_start - 32)
+
+    def action_scroll_page_down(self) -> None:
+        """Fast scroll memory down (4 rows = 128 bytes)."""
+        self.mem_start = min(0xFFE0, self.mem_start + 128)
+
+    def action_scroll_page_up(self) -> None:
+        """Fast scroll memory up (4 rows = 128 bytes)."""
+        self.mem_start = max(0x0000, self.mem_start - 128)
+
+    def action_open_command(self) -> None:
+        """Open command bar input."""
+        cmd_bar = self.query_one("#command-bar")
+        cmd_bar.styles.display = "block"
+        self.query_one("#lazy-status").styles.display = "none"
+        cmd_input = self.query_one("#cmd-input", Input)
+        cmd_input.value = ""
+        cmd_input.focus()
+
+    def action_cancel_command(self) -> None:
+        """Cancel and close command input or dismiss modal dialog."""
+        if len(self.screen_stack) > 1:
+            self.pop_screen()
+            return
+        cmd_bar = self.query_one("#command-bar")
+        if cmd_bar.styles.display != "none":
+            cmd_bar.styles.display = "none"
+            self.query_one("#lazy-status").styles.display = "block"
+            self.set_focus(None)
+
+    def on_input_submitted(self, event: Input.Submitted) -> None:
+        """Process entered command."""
+        if event.input.id != "cmd-input":
+            return
+        event.stop()
+        cmd_bar = self.query_one("#command-bar")
+        cmd_bar.styles.display = "none"
+        self.query_one("#lazy-status").styles.display = "block"
+        self.set_focus(None)
+        raw_cmd = event.value.strip().lstrip(":")
+
+        if not raw_cmd:
+            return
+
+        if raw_cmd.startswith("'"):
+            mark_name = raw_cmd[1:].strip()
+            if mark_name in self.bookmarks:
+                self.current_idx = self.bookmarks[mark_name]
+                self.update_views()
+            return
+
+        parts = raw_cmd.split()
+        sub = parts[0].lower()
+
+        if sub.isdigit():
+            step_target = int(sub)
+            if 0 <= step_target < self.num_traces:
+                self.current_idx = step_target
+                self.update_views()
+            else:
+                found = False
+                for idx, tr in enumerate(self.traces):
+                    if tr.get("step") == step_target:
+                        self.current_idx = idx
+                        self.update_views()
+                        found = True
+                        break
+                if (
+                    not found
+                    and self.execution_mode == "cache"
+                    and self.checkpoint_manager.checkpoint_steps
+                ):
+                    if self.checkpoint_manager.restore_exact_step(step_target):
+                        self.traces = list(self.cpu.step_trace)
+                        self.num_traces = len(self.traces)
+                        self.current_idx = max(0, self.num_traces - 1)
+                        self.update_views()
+        elif sub in ("goto", "step", "s") and len(parts) > 1:
+            target = parts[1]
+            if target in self.bookmarks:
+                self.current_idx = self.bookmarks[target]
+                self.update_views()
+            elif target.isdigit():
+                step_target = int(target)
+                if 0 <= step_target < self.num_traces:
+                    self.current_idx = step_target
+                    self.update_views()
+                else:
+                    found = False
+                    for idx, tr in enumerate(self.traces):
+                        if tr.get("step") == step_target:
+                            self.current_idx = idx
+                            self.update_views()
+                            found = True
+                            break
+                    if (
+                        not found
+                        and self.execution_mode == "cache"
+                        and self.checkpoint_manager.checkpoint_steps
+                    ):
+                        if self.checkpoint_manager.restore_exact_step(step_target):
+                            self.traces = list(self.cpu.step_trace)
+                            self.num_traces = len(self.traces)
+                            self.current_idx = max(0, self.num_traces - 1)
+                            self.update_views()
+        elif sub in ("b", "break", "bp"):
+            if len(parts) > 1:
+                cmd_rest = " ".join(parts[1:])
+                if " if " in cmd_rest:
+                    pc_part, cond = cmd_rest.split(" if ", 1)
+                    try:
+                        target_pc = (
+                            int(pc_part.strip(), 16)
+                            if pc_part.strip().startswith("0x")
+                            else int(pc_part.strip())
+                        )
+                        self.breakpoints.add(target_pc)
+                        self.conditional_breakpoints[target_pc] = cond.strip()
+                        self.update_views()
+                    except ValueError:
+                        pass
+                else:
+                    try:
+                        target_pc = (
+                            int(parts[1], 16)
+                            if parts[1].startswith("0x")
+                            else int(parts[1])
+                        )
+                        if target_pc in self.breakpoints:
+                            self.breakpoints.remove(target_pc)
+                            self.conditional_breakpoints.pop(target_pc, None)
+                        else:
+                            self.breakpoints.add(target_pc)
+                        self.update_views()
+                    except ValueError:
+                        pass
+            else:
+                self.action_toggle_breakpoint()
+        elif sub in ("bc", "clear", "unbreak"):
+            self.breakpoints.clear()
+            self.conditional_breakpoints.clear()
+            self.update_views()
+        elif sub in ("w", "watch") and len(parts) > 1:
+            wp_expr = " ".join(parts[1:]).strip()
+            self.watchpoints.add(wp_expr)
+        elif sub in ("unwatch", "uw"):
+            if len(parts) > 1:
+                wp_expr = " ".join(parts[1:]).strip()
+                self.watchpoints.discard(wp_expr)
+            else:
+                self.watchpoints.clear()
+        elif sub in ("mark", "bookmark") and len(parts) > 1:
+            mark_name = parts[1].strip()
+            self.bookmarks[mark_name] = self.current_idx
+        elif sub in ("rc", "rev", "reverse"):
+            self.action_reverse_continue()
+        elif sub in ("set", "poke") and len(parts) > 2:
+            reg_match = re.match(r"^[rR](\d+)$", parts[1])
+            if reg_match:
+                try:
+                    ridx = int(reg_match.group(1))
+                    val = (
+                        int(parts[2], 16)
+                        if parts[2].startswith(("0x", "0X"))
+                        else int(parts[2])
+                    )
+                    if 0 <= ridx < 32:
+                        cur_step = (
+                            self.traces[self.current_idx].get(
+                                "step", self.cpu.step_count
+                            )
+                            if self.traces and 0 <= self.current_idx < self.num_traces
+                            else self.cpu.step_count
+                        )
+                        if self.traces and (0 <= self.current_idx < self.num_traces):
+                            self.traces[self.current_idx]["regs"][ridx] = val & 0xFF
+                        if ridx < len(self.cpu.regs):
+                            self.cpu.regs[ridx] = val & 0xFF
+                        self.checkpoint_manager.invalidate_after(cur_step)
+                        self.notify(
+                            f"R{ridx} set to {val}. Checkpoint cache invalidated after step {cur_step}.",
+                            timeout=1.5,
+                        )
+                        self.update_views()
+                except ValueError:
+                    pass
+            else:
+                try:
+                    addr = (
+                        int(parts[1], 16)
+                        if parts[1].startswith(("0x", "0X"))
+                        else int(parts[1])
+                    )
+                    val = (
+                        int(parts[2], 16)
+                        if parts[2].startswith(("0x", "0X"))
+                        else int(parts[2])
+                    )
+                    if 0 <= addr < self.cpu.mem.ram_size:
+                        cur_step = (
+                            self.traces[self.current_idx].get(
+                                "step", self.cpu.step_count
+                            )
+                            if self.traces and 0 <= self.current_idx < self.num_traces
+                            else self.cpu.step_count
+                        )
+                        if self.traces and (0 <= self.current_idx < self.num_traces):
+                            self.traces[self.current_idx]["mem"][addr] = val & 0xFF
+                        self.cpu.mem.ram[addr] = val & 0xFF
+                        self.cpu.mem.nonzero_ram[addr] = val & 0xFF
+                        self.checkpoint_manager.invalidate_after(cur_step)
+                        self.notify(
+                            f"Memory 0x{addr:04X} set to {val}. Checkpoint cache invalidated after step {cur_step}.",
+                            timeout=1.5,
+                        )
+                        self.update_views()
+                except ValueError:
+                    pass
+        elif sub == "exec" and len(parts) > 1:
+            instr_str = " ".join(parts[1:])
+            self.action_exec_instruction(instr_str)
+        elif sub in ("c", "cont", "continue", "run"):
+            self.action_continue_run()
+        elif sub in ("m", "mem", "memory") and len(parts) > 1:
+            target = parts[1].lower()
+            addr = None
+            if target in ("regs", "reg", "r"):
+                addr = 0x0000
+            elif target in ("io", "ports"):
+                addr = 0x0020
+            elif target in ("sram", "ram"):
+                addr = 0x0060
+            elif target in ("vram", "video", "heatmap"):
+                addr = 0x0200
+            elif target in ("ext", "extended", "data", "heap"):
+                addr = 0x0600
+            elif target in ("sp", "stack", "top"):
+                addr = self.cpu.sp
+            else:
+                try:
+                    if target.startswith(("0x", "0X")):
+                        addr = int(target, 16)
+                    else:
+                        try:
+                            addr = int(target)
+                        except ValueError:
+                            addr = int(target, 16)
+                except ValueError:
+                    addr = None
+
+            if addr is not None:
+                self.mem_start = max(0, min(0xFFE0, addr & ~0x1F))
+                self.update_views()
+        elif sub in ("find", "search", "/") and len(parts) > 1:
+            term = parts[1].lower()
+            for i in range(self.current_idx + 1, self.num_traces):
+                instr = self.traces[i].get("instr", "").lower()
+                if term in instr:
+                    self.current_idx = i
+                    self.update_views()
+                    break
+        elif sub in ("play", "forward"):
+            self.action_toggle_play()
+        elif sub in ("revplay", "reverse_play", "rev"):
+            self.action_toggle_reverse_play()
+        elif sub in ("mode", "toggle") and len(parts) > 1:
+            m = parts[1].lower()
+            if m in ("cache", "cached"):
+                self.execution_mode = "cache"
+                self.notify("Execution Mode: CACHE (Checkpoints enabled)", timeout=1.5)
+            elif m in ("live", "direct", "realtime"):
+                self.execution_mode = "live"
+                self.notify("Execution Mode: LIVE (Direct step)", timeout=1.5)
+            else:
+                self.action_cycle_mode()
+            self.update_views()
+        elif sub in ("cache",):
+            self.execution_mode = "cache"
+            self.notify("Execution Mode: CACHE", timeout=1.5)
+            self.update_views()
+        elif sub in ("live",):
+            self.execution_mode = "live"
+            self.notify("Execution Mode: LIVE", timeout=1.5)
+            self.update_views()
+        elif sub in ("precompute", "pcomp"):
+            limit = int(parts[1]) if len(parts) > 1 and parts[1].isdigit() else None
+            msg = (
+                f"Precomputing cache up to {limit:,} steps..."
+                if limit
+                else "Precomputing cache until infinite loop..."
+            )
+            self.notify(msg, timeout=1.5)
+            done = self.checkpoint_manager.precompute(max_steps=limit)
+            self.traces = list(self.cpu.step_trace)
+            self.num_traces = len(self.traces)
+            self.current_idx = max(0, self.num_traces - 1)
+            reason = (
+                f" ({self.checkpoint_manager.loop_reason})"
+                if self.checkpoint_manager.infinite_loop_detected
+                else ""
+            )
+            self.notify(
+                f"Precomputed {done:,} steps{reason}. Total checkpoints: {len(self.checkpoint_manager.checkpoint_steps)}",
+                timeout=2.5,
+            )
+            self.update_views()
+        elif sub in ("gray", "grayscale", "grey"):
+            self.action_toggle_grayscale()
+        elif sub in ("viridis", "color", "colour"):
+            self.color_mode = "viridis"
+            self.update_views()
+        elif sub in ("hex", "hexadecimal"):
+            self.show_hex = True
+            self.update_views()
+        elif sub in ("pixel", "block", "graphic", "img", "image"):
+            self.show_hex = False
+            self.update_views()
+        elif sub in ("mode", "toggle"):
+            self.action_cycle_mode()
+        elif sub in ("speed", "spd") and len(parts) > 1:
+            if parts[1].isdigit():
+                self.speed_ms = max(1, min(1000, int(parts[1])))
+                if self.playing and self.timer:
+                    self.timer.stop()
+                    self.timer = self.set_interval(
+                        self.speed_ms / 1000.0, self._auto_step
+                    )
+                self.notify(
+                    f"Speed set to {self.speed_ms}ms (batch: {self.batch_size})",
+                    timeout=1.5,
+                )
+        elif sub in ("batch", "bth") and len(parts) > 1:
+            if parts[1].isdigit():
+                self.batch_size = max(1, min(200000, int(parts[1])))
+                self.notify(
+                    f"Batch size set to {self.batch_size} (speed: {self.speed_ms}ms)",
+                    timeout=1.5,
+                )
+        elif sub in ("turbo", "fast", "max"):
+            self.speed_ms = 30
+            self.playback_rate_idx = len(PLAYBACK_RATES) - 1
+            self.batch_size = PLAYBACK_RATES[self.playback_rate_idx]
+            self.notify(
+                f"TURBO mode enabled: {self.batch_size:,} steps/tick (~33 fps)",
+                timeout=1.5,
+            )
+            self.update_views()
+        elif sub in ("normal", "std", "default"):
+            self.speed_ms = 100
+            self.playback_rate_idx = 0
+            self.batch_size = 1
+            self.notify(
+                "Standard speed enabled: 100ms interval (1 step/tick)", timeout=1.5
+            )
+            self.update_views()
+        elif sub in ("e", "edit", "vim"):
+            if len(parts) > 1:
+                self.file_path = parts[1]
+            self.action_open_editor()
+        elif sub in ("r", "reset"):
+            self.action_reset()
+        elif sub in ("h", "help", "?"):
+            self.action_show_help()
+        elif sub in ("i", "info", "instr", "detail"):
+            self.action_show_instruction_detail()
+        elif sub in ("ref", "reference"):
+            self.action_show_reference()
+        elif sub in ("q", "quit", "exit"):
+            self.exit()
+
+    def action_reset(self) -> None:
+        self.current_idx = 0
+        self.playing = False
+        if self.timer:
+            self.timer.stop()
+        self.update_views()
+
+    def action_toggle_grayscale(self) -> None:
+        """Toggle between Viridis and Grayscale color palette."""
+        self.color_mode = "grayscale" if self.color_mode == "viridis" else "viridis"
+        self.update_views()
+
+    def action_toggle_hex(self) -> None:
+        """Toggle between Hexadecimal digits (02X) and Graphic Pixel blocks."""
+        self.show_hex = not self.show_hex
+        self.update_views()
+
+    def action_cycle_mode(self) -> None:
+        """Cycle view modes (Viridis+Hex -> Viridis+Pixel -> Grayscale+Pixel -> Grayscale+Hex)."""
+        if self.color_mode == "viridis" and self.show_hex:
+            self.show_hex = False
+        elif self.color_mode == "viridis" and not self.show_hex:
+            self.color_mode = "grayscale"
+        elif self.color_mode == "grayscale" and not self.show_hex:
+            self.show_hex = True
+        else:
+            self.color_mode = "viridis"
+            self.show_hex = True
+        self.update_views()
+
+    def action_show_help(self) -> None:
+        """Show full TUI application usage and keyboard guide."""
+        self.push_screen(TUIHelpScreen())
+
+    def action_show_instruction_detail(self) -> None:
+        """Show in-depth specification and effects for the currently selected instruction."""
+        instr_str = ""
+        pc = 0
+        sp = 0
+        source_line = -1
+        sreg = 0
+        if self.traces and 0 <= self.current_idx < self.num_traces:
+            entry = self.traces[self.current_idx]
+            instr_str = entry.get("instr", "")
+            pc = entry.get("pc", 0)
+            sp = entry.get("sp", 0)
+            source_line = entry.get("source_line", -1)
+            sreg = entry.get("sreg", 0)
+        elif self.cpu:
+            pc = self.cpu.pc
+            sp = self.cpu.sp
+            sreg = self.cpu.sreg
+            source_line = self.cpu.pc_to_line.get(pc, -1)
+            if 0 <= pc < len(self.cpu.program):
+                instr, ops = self.cpu.program[pc]
+                ops_str = ", ".join(
+                    f"R{o[1]}"
+                    if isinstance(o, tuple) and len(o) == 2 and o[0] == "reg"
+                    else str(o)
+                    for o in ops
+                )
+                instr_str = f"{instr} {ops_str}".strip()
+
+        self.push_screen(
+            InstructionDetailModalScreen(
+                instr=instr_str, pc=pc, sp=sp, source_line=source_line, sreg=sreg
+            )
+        )
+
+    def action_show_reference(self) -> None:
+        """Show full instruction set reference modal."""
+        self.push_screen(InstructionReferenceScreen())
+
+    def action_toggle_play(self) -> None:
+        """Toggle forward automatic playback."""
+        if self.playing and self.play_direction == 1:
+            self.playing = False
+            if self.timer:
+                self.timer.stop()
+        else:
+            self.play_direction = 1
+            self.playing = True
+            if self.timer:
+                self.timer.stop()
+            interval = max(0.025, self.speed_ms / 1000.0)
+            self.timer = self.set_interval(interval, self._auto_step)
+        self.update_views()
+
+    def action_toggle_reverse_play(self) -> None:
+        """Toggle reverse automatic playback (time-travel replay)."""
+        if self.playing and self.play_direction == -1:
+            self.playing = False
+            if self.timer:
+                self.timer.stop()
+        else:
+            self.play_direction = -1
+            self.playing = True
+            if self.timer:
+                self.timer.stop()
+            interval = max(0.025, self.speed_ms / 1000.0)
+            self.timer = self.set_interval(interval, self._auto_step)
+        self.update_views()
+
+    def _auto_step(self) -> None:
+        if not self.cpu:
+            self.playing = False
+            if self.timer:
+                self.timer.stop()
+            return
+
+        batch = (
+            PLAYBACK_RATES[self.playback_rate_idx]
+            if self.speed_ms <= 30
+            else self.batch_size
+        )
+        cur_step = (
+            self.traces[self.current_idx].get("step", self.cpu.step_count)
+            if (self.traces and 0 <= self.current_idx < len(self.traces))
+            else self.cpu.step_count
+        )
+
+        if self.play_direction == 1:
+            # Forward playback in Cache mode using precomputed checkpoints
+            if (
+                self.execution_mode == "cache"
+                and self.checkpoint_manager.checkpoint_steps
+            ):
+                target_step = cur_step + batch
+                self.checkpoint_manager.restore_exact_step(target_step)
+                self.traces = list(self.cpu.step_trace)
+                self.num_traces = len(self.traces)
+                self.current_idx = max(0, self.num_traces - 1)
+                if (
+                    not self.cpu.running
+                    or self.checkpoint_manager.infinite_loop_detected
+                    or self._is_breakpoint_hit(self.current_idx)
+                    or self._check_watchpoints_triggered(self.current_idx)
+                ):
+                    self.playing = False
+                    if self.timer:
+                        self.timer.stop()
+                    if self.checkpoint_manager.infinite_loop_detected:
+                        self.notify(
+                            f"Auto-stopped: {self.checkpoint_manager.loop_reason}",
+                            timeout=3.0,
+                        )
+                self.update_views()
+                return
+
+            if self.current_idx < self.num_traces - 1:
+                adv = min(batch, self.num_traces - 1 - self.current_idx)
+                self.current_idx += adv
+                if self._is_breakpoint_hit(
+                    self.current_idx
+                ) or self._check_watchpoints_triggered(self.current_idx):
+                    self.playing = False
+                    if self.timer:
+                        self.timer.stop()
+                self.update_views()
+            elif self.cpu.running:
+                # Live mode or computing beyond cached checkpoints
+                old_trace = self.cpu.trace_enabled
+                is_large_batch = batch > 20
+                if is_large_batch:
+                    self.cpu.trace_enabled = False
+                try:
+                    for i in range(batch):
+                        if not self.cpu.running:
+                            break
+                        if (
+                            self.execution_mode == "cache"
+                            and i % 16 == 0
+                            and self.checkpoint_manager.detect_loop()
+                        ):
+                            self.cpu.running = False
+                            self.notify(
+                                f"Auto-stopped: {self.checkpoint_manager.loop_reason}",
+                                timeout=3.0,
+                            )
+                            break
+                        record_this = not is_large_batch or (i == batch - 1)
+                        if not self.cpu.step(record_trace=record_this):
+                            break
+                        if self.execution_mode == "cache":
+                            self.checkpoint_manager.record_if_interval(
+                                self.cpu.step_count
+                            )
+                        if self.cpu.pc in self.breakpoints:
+                            break
+                finally:
+                    self.cpu.trace_enabled = old_trace
+
+                self.traces = list(self.cpu.step_trace)
+                self.num_traces = len(self.traces)
+                self.current_idx = max(0, self.num_traces - 1)
+                if (
+                    not self.cpu.running
+                    or self._is_breakpoint_hit(self.current_idx)
+                    or self._check_watchpoints_triggered(self.current_idx)
+                ):
+                    self.playing = False
+                    if self.timer:
+                        self.timer.stop()
+                self.update_views()
+            else:
+                self.playing = False
+                if self.timer:
+                    self.timer.stop()
+        else:
+            # Reverse playback (Time-Travel replay)
+            target_step = max(0, cur_step - batch)
+            if target_step == cur_step or cur_step == 0:
+                self.playing = False
+                if self.timer:
+                    self.timer.stop()
+                self.notify("Reached start of execution (Step 0)", timeout=1.5)
+                return
+
+            if (
+                self.execution_mode == "cache"
+                and self.checkpoint_manager.checkpoint_steps
+            ):
+                self.checkpoint_manager.restore_exact_step(target_step)
+                self.traces = list(self.cpu.step_trace)
+                self.num_traces = len(self.traces)
+                self.current_idx = max(0, self.num_traces - 1)
+            else:
+                if self.current_idx > 0:
+                    self.current_idx = max(0, self.current_idx - batch)
+                else:
+                    self.playing = False
+                    if self.timer:
+                        self.timer.stop()
+            if target_step == 0:
+                self.playing = False
+                if self.timer:
+                    self.timer.stop()
+            self.update_views()
+
+    def action_faster(self) -> None:
+        """Increase playback execution speed.
+
+        Decreases timer interval down to visual limit (30ms / ~33 fps), then automatically
+        transitions to adaptive batch processing scaling up to 50,000 steps per tick.
+        """
+        if self.speed_ms > 30:
+            self.speed_ms = max(30, self.speed_ms - 20)
+            msg = f"Visual Speed: {self.speed_ms}ms"
+        else:
+            if self.playback_rate_idx < len(PLAYBACK_RATES) - 1:
+                self.playback_rate_idx += 1
+            rate = PLAYBACK_RATES[self.playback_rate_idx]
+            self.batch_size = rate
+            msg = f"Adaptive Batch: {rate:,} steps/tick (~33 fps)"
+
+        if self.playing and self.timer:
+            self.timer.stop()
+            interval = max(0.025, self.speed_ms / 1000.0)
+            self.timer = self.set_interval(interval, self._auto_step)
+
+        self.notify(msg, timeout=1.2)
+        self.update_views()
+
+    def action_slower(self) -> None:
+        """Decrease playback execution speed.
+
+        Scales down batch processing first, then transitions back to observable visual delay.
+        """
+        if self.playback_rate_idx > 0:
+            self.playback_rate_idx -= 1
+            rate = PLAYBACK_RATES[self.playback_rate_idx]
+            self.batch_size = rate
+            msg = f"Adaptive Batch: {rate:,} steps/tick (~33 fps)"
+        else:
+            self.speed_ms = min(500, self.speed_ms + 20)
+            msg = f"Visual Speed: {self.speed_ms}ms"
+
+        if self.playing and self.timer:
+            self.timer.stop()
+            interval = max(0.025, self.speed_ms / 1000.0)
+            self.timer = self.set_interval(interval, self._auto_step)
+
+        self.notify(msg, timeout=1.2)
+        self.update_views()
+
+
+def run_cli(
+    cpu: CPU,
+    mem_addr_start: int = 0x60,
+    mem_addr_end: int = 0xDF,
+    delay: float = 0.1,
+    source_lines: list[str] | None = None,
+    var_symbols: dict[str, dict[str, Any]] | None = None,
+) -> None:
+    """Launch modern Textual TUI debugger with OLED black theme and gradient heatmaps.
+
+    Args:
+        cpu: CPU emulator with execution history.
+        mem_addr_start: Start address for memory viewer.
+        mem_addr_end: End address for memory viewer.
+        delay: Playback interval in seconds.
+        source_lines: Source assembly or C lines.
+        var_symbols: C variable metadata symbols.
+    """
+    if not cpu.step_trace:
+        raise RuntimeError("cpu.step_trace is empty")
+    app = Tiny8App(cpu=cpu, var_symbols=var_symbols)
+    app.run()
+
+
+def main() -> None:
+    """Entry point for tiny8 CLI supporting Assembly and C sources."""
+    from tiny8 import __version__
+
+    parser = argparse.ArgumentParser(
+        prog="tiny8",
+        description="Tiny8 modern CPU simulator, C compiler, Vim editor, and Textual debugger",
+    )
+    parser.add_argument(
+        "--version",
+        "-v",
+        action="version",
+        version=f"%(prog)s {__version__}",
+    )
+    parser.add_argument(
+        "file",
+        nargs="?",
+        default=None,
+        help="assembly file (.asm) or C source file (.c) to run or edit (default: main.c in editor)",
+    )
+    parser.add_argument(
+        "--edit",
+        "-e",
+        action="store_true",
+        help="launch directly into Vim editor mode",
+    )
+    parser.add_argument(
+        "--max-steps",
+        type=int,
+        default=None,
+        help="maximum CPU execution steps (default: until infinite loop or halt)",
+    )
+    parser.add_argument(
+        "--compile-only",
+        "-c",
+        action="store_true",
+        help="compile C code and print generated Tiny8 assembly without running",
+    )
+
+    args = parser.parse_args()
+
+    if args.file is None:
+        app = Tiny8App(
+            file_path="main.c", start_in_editor=True, max_steps=args.max_steps
+        )
+        app.run()
+        return
+
+    target_path = Path(args.file)
+    if args.compile_only:
+        if args.file.endswith(".c"):
+            print(compile_c_file(args.file))
+        else:
+            print(target_path.read_text(encoding="utf-8"))
+        return
+
+    if not target_path.exists() or args.edit:
+        app = Tiny8App(
+            file_path=args.file, start_in_editor=True, max_steps=args.max_steps
+        )
+        app.run()
+        return
+
+    if args.file.endswith(".c"):
+        asm_code, symbols = compile_c_file_with_symbols(args.file)
+        asm = assemble(asm_code)
+        src_lines = target_path.read_text(encoding="utf-8").splitlines()
+    else:
+        asm = assemble_file(args.file)
+        src_lines = target_path.read_text(encoding="utf-8").splitlines()
+        symbols = {}
+
+    max_steps = args.max_steps
+
+    cpu = CPU()
+    cpu.load_program(asm)
+    cpu.source_lines = src_lines
+    cpu.pc_to_line = asm.pc_to_line
+
+    checkpoint_mgr = CheckpointManager(cpu, interval=100)
+
+    app = Tiny8App(
+        cpu=cpu,
+        file_path=args.file,
+        max_steps=max_steps,
+        var_symbols=symbols,
+        checkpoint_manager=checkpoint_mgr,
+        execution_mode="cache",
+        precompute_cache=True,
+        show_cache_progress=True,
+    )
+    app.current_idx = 0
+    app.run()
+
+
+if __name__ == "__main__":
+    main()
diff --git a/src/tiny8/utils.py b/src/tiny8/utils.py
index 804f822..f2b91b2 100644
--- a/src/tiny8/utils.py
+++ b/src/tiny8/utils.py
@@ -1,70 +1,40 @@
-"""Utility functions for Tiny8, including tqdm-like progress bar.
-
-The ProgressBar class provides a simple, tqdm-like progress indicator that
-can be used to visualize long-running CPU executions or other iterative
-processes. The progress bar automatically adapts to the terminal width.
-
-Example usage with CPU:
-    >>> from tiny8 import CPU, assemble
-    >>> asm = assemble("ldi r16, 10\\nloop:\\ndec r16\\njmp loop")
-    >>> cpu = CPU()
-    >>> cpu.load_program(asm)
-    >>> cpu.run(max_steps=1000, show_progress=True)
-    CPU execution: 100.0%|████████████| 1000/1000 [00:00<00:00, 5000.00it/s]
-
-Example usage standalone (auto-detect width):
-    >>> from tiny8 import ProgressBar
-    >>> with ProgressBar(total=100, desc="Processing") as pb:
-    ...     for i in range(100):
-    ...         # do work
-    ...         pb.update(1)
-
-Example usage with custom width:
-    >>> with ProgressBar(total=100, desc="Processing", ncols=60) as pb:
-    ...     for i in range(100):
-    ...         pb.update(1)
-"""
+"""Utility helpers for tiny8 including terminal progress bar."""
 
+import math
 import shutil
 import sys
 import time
-from typing import Optional
 
 
 class ProgressBar:
-    """A simple tqdm-like progress bar for Tiny8 CPU execution.
-
-    Usage:
-        with ProgressBar(total=1000, desc="Running") as pb:
-            for i in range(1000):
-                # do work
-                pb.update(1)
-
-    Or:
-        pb = ProgressBar(total=1000)
-        for i in range(1000):
-            # do work
-            pb.update(1)
-        pb.close()
+    """Terminal progress bar indicator adapting to terminal width.
+
+    Args:
+        total: Total number of iterations, or None for indeterminate progress.
+        desc: Prefix description string. Defaults to "".
+        disable: True to disable output completely. Defaults to False.
+        ncols: Explicit width in characters, or None for auto-detection.
+        mininterval: Minimum interval in seconds between screen refreshes.
+
+    Attributes:
+        total: Total iterations expected.
+        desc: Description prefix text.
+        disable: Flag controlling output suppression.
+        ncols: Target bar character width.
+        mininterval: Refresh rate throttle in seconds.
+        n: Current iteration step count.
+        start_time: Monotonic start timestamp.
+        last_print_time: Timestamp of last bar render.
     """
 
     def __init__(
         self,
-        total: Optional[int] = None,
+        total: int | None = None,
         desc: str = "",
         disable: bool = False,
-        ncols: Optional[int] = None,
+        ncols: int | None = None,
         mininterval: float = 0.1,
-    ):
-        """Initialize progress bar.
-
-        Args:
-            total: Total number of iterations (None for indeterminate)
-            desc: Description prefix for the progress bar
-            disable: If True, disable the progress bar completely
-            ncols: Width of the progress bar in characters (None for auto-detect)
-            mininterval: Minimum time between updates in seconds
-        """
+    ) -> None:
         self.total = total
         self.desc = desc
         self.disable = disable
@@ -72,22 +42,22 @@ def __init__(
         self.mininterval = mininterval
         self.n = 0
         self.start_time = time.time()
-        self.last_print_time = 0
+        self.last_print_time = 0.0
 
-    def __enter__(self):
-        """Context manager entry."""
+    def __enter__(self) -> "ProgressBar":
+        """Enter context manager."""
         return self
 
-    def __exit__(self, exc_type, exc_val, exc_tb):
-        """Context manager exit."""
+    def __exit__(self, exc_type, exc_val, exc_tb) -> bool:
+        """Exit context manager and flush output."""
         self.close()
         return False
 
-    def update(self, n: int = 1):
-        """Update progress by n steps.
+    def update(self, n: int = 1) -> None:
+        """Increment progress by n steps.
 
         Args:
-            n: Number of steps to increment
+            n: Number of iterations to increment. Defaults to 1.
         """
         if self.disable:
             return
@@ -104,10 +74,10 @@ def update(self, n: int = 1):
         self._print_bar()
 
     def _get_terminal_width(self) -> int:
-        """Get the current terminal width.
+        """Return detected or default terminal width in characters.
 
         Returns:
-            Terminal width in characters, defaults to 80 if unable to detect
+            Width in characters, fallback to 80.
         """
         if self.ncols is not None:
             return self.ncols
@@ -117,8 +87,8 @@ def _get_terminal_width(self) -> int:
         except Exception:
             return 80
 
-    def _print_bar(self):
-        """Print the progress bar to stderr."""
+    def _print_bar(self) -> None:
+        """Render and output progress bar to stderr."""
         if self.disable:
             return
 
@@ -126,10 +96,9 @@ def _print_bar(self):
         elapsed = time.time() - self.start_time
 
         if self.total is not None and self.total > 0:
-            percent = min(100, (self.n / self.total) * 100)
-
-            rate = self.n / elapsed if elapsed > 0 else 0
-            eta = (self.total - self.n) / rate if rate > 0 else 0
+            percent = min(100.0, (self.n / self.total) * 100)
+            rate = self.n / elapsed if elapsed > 0 else 0.0
+            eta = (self.total - self.n) / rate if rate > 0 else 0.0
 
             prefix = f"{self.desc}: {percent:>5.1f}%|"
             suffix = f"| {self.n}/{self.total} [{self._format_time(elapsed)}<{self._format_time(eta)}, {rate:.2f}it/s]"
@@ -139,13 +108,11 @@ def _print_bar(self):
 
             filled = int(bar_width * self.n / self.total)
             bar = "█" * filled + "░" * (bar_width - filled)
-
             output = f"\r{prefix}{bar}{suffix}"
         else:
             spinner = ["⠋", "⠙", "⠹", "⠸", "⠼", "⠴", "⠦", "⠧", "⠇", "⠏"]
             spin_char = spinner[self.n % len(spinner)]
-            rate = self.n / elapsed if elapsed > 0 else 0
-
+            rate = self.n / elapsed if elapsed > 0 else 0.0
             output = f"\r{self.desc}: {spin_char} {self.n} [{self._format_time(elapsed)}, {rate:.2f}it/s]"
 
         if len(output) > terminal_width:
@@ -155,37 +122,33 @@ def _print_bar(self):
         sys.stderr.flush()
 
     def _format_time(self, seconds: float) -> str:
-        """Format seconds as MM:SS or HH:MM:SS.
+        """Format duration in seconds as MM:SS or HH:MM:SS string.
 
         Args:
-            seconds: Time in seconds
+            seconds: Duration in seconds.
 
         Returns:
-            Formatted time string
+            Formatted time string.
         """
-        if seconds < 0 or seconds != seconds:
+        if seconds < 0 or math.isnan(seconds):
             return "??:??"
 
-        seconds = int(seconds)
-        if seconds < 3600:
-            return f"{seconds // 60:02d}:{seconds % 60:02d}"
-        else:
-            hours = seconds // 3600
-            minutes = (seconds % 3600) // 60
-            secs = seconds % 60
-            return f"{hours:02d}:{minutes:02d}:{secs:02d}"
+        sec = int(seconds)
+        if sec < 3600:
+            return f"{sec // 60:02d}:{sec % 60:02d}"
+        return f"{sec // 3600:02d}:{(sec % 3600) // 60:02d}:{sec % 60:02d}"
 
-    def set_description(self, desc: str):
-        """Update the description.
+    def set_description(self, desc: str) -> None:
+        """Update description prefix and re-render bar.
 
         Args:
-            desc: New description string
+            desc: New description text.
         """
         self.desc = desc
         self._print_bar()
 
-    def close(self):
-        """Close the progress bar and print newline."""
+    def close(self) -> None:
+        """Finalize progress bar and print trailing newline."""
         if self.disable:
             return
 
@@ -193,8 +156,8 @@ def close(self):
         sys.stderr.write("\n")
         sys.stderr.flush()
 
-    def reset(self):
-        """Reset the progress bar to initial state."""
+    def reset(self) -> None:
+        """Reset progress counter and timers to initial state."""
         self.n = 0
         self.start_time = time.time()
-        self.last_print_time = 0
+        self.last_print_time = 0.0
diff --git a/src/tiny8/visualizer.py b/src/tiny8/visualizer.py
deleted file mode 100644
index 3ba9ae5..0000000
--- a/src/tiny8/visualizer.py
+++ /dev/null
@@ -1,345 +0,0 @@
-"""Visualization helpers using Matplotlib to plot register/memory changes.
-
-This module provides a simple Visualizer class that can create an animated
-visualization of the CPU step trace showing SREG bits, registers and a
-memory range.
-"""
-
-import matplotlib.pyplot as plt
-import numpy as np
-from matplotlib import animation
-
-
-class Visualizer:
-    def __init__(self, cpu):
-        self.cpu = cpu
-
-    def animate_execution(
-        self,
-        mem_addr_start: int = 0x60,
-        mem_addr_end: int = 0x7F,
-        filename: str | None = None,
-        interval: int = 200,
-        fps: int = 30,
-        fontsize=9,
-        cmap="inferno",
-        plot_every: int = 1,
-    ):
-        """Animate SREG bits, registers (R0..R31), and a memory range as three stacked subplots.
-
-        Args:
-            mem_addr_start: Start memory address for memory subplot.
-            mem_addr_end: End memory address for memory subplot.
-            filename: Optional output filename for saving animation.
-            interval: Milliseconds between frames.
-            fps: Frames per second for saving output.
-            fontsize: Font size for labels and ticks.
-            cmap: Matplotlib colormap name for the heatmaps.
-            plot_every: Plot every N steps (downsampling).
-        """
-        num_steps = len(self.cpu.step_trace)
-
-        flag_names = ["I", "T", "H", "S", "V", "N", "Z", "C"]
-        sreg_mat = np.zeros((8, num_steps))
-        reg_mat = np.zeros((32, num_steps))
-        mem_rows = mem_addr_end - mem_addr_start + 1
-        mem_mat = np.zeros((mem_rows, num_steps))
-
-        for idx, entry in enumerate(self.cpu.step_trace):
-            s = entry.get("sreg", 0)
-            for b in range(8):
-                sreg_mat[7 - b, idx] = 1.0 if ((s >> b) & 1) else 0.0
-
-            regs = entry.get("regs", [])
-            for r in range(min(32, len(regs))):
-                reg_mat[r, idx] = regs[r]
-
-            memsnap = entry.get("mem", {})
-            for a, v in memsnap.items():
-                if mem_addr_start <= a <= mem_addr_end:
-                    mem_mat[a - mem_addr_start, idx] = v
-
-        plt.style.use("dark_background")
-        fig, axes = plt.subplots(
-            3, 1, figsize=(15, 10), gridspec_kw={"height_ratios": [1, 4, 4]}
-        )
-
-        im_sreg = axes[0].imshow(
-            sreg_mat[:, :1],
-            aspect="auto",
-            cmap=cmap,
-            interpolation="nearest",
-            vmin=0,
-            vmax=1,
-        )
-        axes[0].set_yticks(range(8))
-        axes[0].set_yticklabels(flag_names, fontsize=fontsize)
-        axes[0].set_ylabel("SREG", fontsize=fontsize)
-
-        im_regs = axes[1].imshow(
-            reg_mat[:, :1],
-            aspect="auto",
-            cmap=cmap,
-            interpolation="nearest",
-            vmin=0,
-            vmax=255,
-        )
-        axes[1].set_yticks(range(32))
-        axes[1].set_yticklabels([f"R{i}" for i in range(32)], fontsize=fontsize)
-        axes[1].set_ylabel("Registers", fontsize=fontsize)
-
-        im_mem = axes[2].imshow(
-            mem_mat[:, :1],
-            aspect="auto",
-            cmap=cmap,
-            interpolation="nearest",
-            vmin=0,
-            vmax=255,
-        )
-        axes[2].set_yticks(range(mem_rows))
-        axes[2].set_yticklabels(
-            [hex(a) for a in range(mem_addr_start, mem_addr_end + 1)], fontsize=fontsize
-        )
-        axes[2].set_ylabel("Memory", fontsize=fontsize)
-        axes[2].set_xlabel("Step", fontsize=fontsize)
-
-        for ax in axes:
-            ax.tick_params(axis="x", labelsize=fontsize)
-            ax.tick_params(axis="y", labelsize=fontsize)
-
-        fig.colorbar(im_sreg, ax=axes[0], fraction=0.015, pad=0.01)
-        fig.colorbar(im_regs, ax=axes[1], fraction=0.015, pad=0.01)
-        fig.colorbar(im_mem, ax=axes[2], fraction=0.015, pad=0.01)
-
-        plt.tight_layout(pad=0.2)
-        fig.subplots_adjust(top=0.96, bottom=0.05, hspace=0.02)
-
-        def update(frame):
-            im_sreg.set_data(sreg_mat[:, : frame + 1])
-            im_regs.set_data(reg_mat[:, : frame + 1])
-            im_mem.set_data(mem_mat[:, : frame + 1])
-
-            im_sreg.set_extent([0, frame + 1, 8, 0])
-            im_regs.set_extent([0, frame + 1, 32, 0])
-            im_mem.set_extent([0, frame + 1, mem_rows, 0])
-
-            entry = self.cpu.step_trace[frame]
-            instr = entry.get("instr", "")
-            pc = entry.get("pc", 0)
-            sp = entry.get("sp", 0)
-
-            fig.suptitle(
-                f"Step: {frame}, PC: 0x{pc:04x}, SP: 0x{sp:04x}, {instr}",
-                x=0.01,
-                ha="left",
-                fontsize=fontsize,
-            )
-            return im_sreg, im_regs, im_mem
-
-        frames = range(0, num_steps, plot_every)
-        anim = animation.FuncAnimation(
-            fig, update, frames=frames, interval=interval, blit=False
-        )
-
-        if filename:
-            anim.save(filename, fps=fps)
-        else:
-            plt.show()
-
-    def show_register_history(self, registers: list[int] = None, figsize=(14, 8)):
-        """Plot timeline of register value changes over execution.
-
-        Args:
-            registers: List of register indices to plot (default: R0-R7).
-            figsize: Figure size as (width, height).
-        """
-        if registers is None:
-            registers = list(range(8))
-
-        num_steps = len(self.cpu.step_trace)
-        reg_data = {r: np.zeros(num_steps) for r in registers}
-
-        for idx, entry in enumerate(self.cpu.step_trace):
-            regs = entry.get("regs", [])
-            for r in registers:
-                if r < len(regs):
-                    reg_data[r][idx] = regs[r]
-
-        plt.style.use("dark_background")
-        fig, ax = plt.subplots(figsize=figsize)
-
-        for r in registers:
-            ax.plot(reg_data[r], label=f"R{r}", linewidth=1.5, marker="o", markersize=3)
-
-        ax.set_xlabel("Step", fontsize=12)
-        ax.set_ylabel("Register Value", fontsize=12)
-        ax.set_title("Register Values Over Time", fontsize=14, pad=20)
-        ax.legend(loc="best", ncol=4, fontsize=10)
-        ax.grid(True, alpha=0.3)
-        plt.tight_layout()
-        plt.show()
-
-    def show_memory_access(
-        self, mem_addr_start: int = 0, mem_addr_end: int = 255, figsize=(12, 8)
-    ):
-        """Plot a heatmap showing memory access patterns over time.
-
-        Args:
-            mem_addr_start: Start memory address.
-            mem_addr_end: End memory address.
-            figsize: Figure size as (width, height).
-        """
-        num_steps = len(self.cpu.step_trace)
-        mem_rows = mem_addr_end - mem_addr_start + 1
-        mem_mat = np.zeros((mem_rows, num_steps))
-
-        for idx, entry in enumerate(self.cpu.step_trace):
-            memsnap = entry.get("mem", {})
-            for a, v in memsnap.items():
-                if mem_addr_start <= a <= mem_addr_end:
-                    mem_mat[a - mem_addr_start, idx] = v
-
-        plt.style.use("dark_background")
-        fig, ax = plt.subplots(figsize=figsize)
-
-        im = ax.imshow(mem_mat, aspect="auto", cmap="viridis", interpolation="nearest")
-        ax.set_xlabel("Step", fontsize=12)
-        ax.set_ylabel("Memory Address", fontsize=12)
-        ax.set_title(
-            f"Memory Access Pattern (0x{mem_addr_start:04x} - 0x{mem_addr_end:04x})",
-            fontsize=14,
-            pad=20,
-        )
-
-        num_ticks = min(20, mem_rows)
-        tick_positions = np.linspace(0, mem_rows - 1, num_ticks, dtype=int)
-        ax.set_yticks(tick_positions)
-        ax.set_yticklabels([hex(mem_addr_start + pos) for pos in tick_positions])
-
-        fig.colorbar(im, ax=ax, label="Value")
-        plt.tight_layout()
-        plt.show()
-
-    def show_flag_history(self, figsize=(14, 6)):
-        """Plot SREG flag changes over execution time.
-
-        Args:
-            figsize: Figure size as (width, height).
-        """
-        flag_names = ["C", "Z", "N", "V", "S", "H", "T", "I"]
-        num_steps = len(self.cpu.step_trace)
-        flag_data = {name: np.zeros(num_steps) for name in flag_names}
-
-        for idx, entry in enumerate(self.cpu.step_trace):
-            s = entry.get("sreg", 0)
-            for bit, name in enumerate(flag_names):
-                flag_data[name][idx] = 1 if ((s >> bit) & 1) else 0
-
-        plt.style.use("dark_background")
-        fig, ax = plt.subplots(figsize=figsize)
-
-        offset = 0
-        colors = plt.cm.Set3(np.linspace(0, 1, 8))
-
-        for idx, name in enumerate(flag_names):
-            values = flag_data[name] + offset
-            ax.fill_between(
-                range(num_steps),
-                offset,
-                values,
-                alpha=0.7,
-                label=name,
-                color=colors[idx],
-            )
-            offset += 1.2
-
-        ax.set_xlabel("Step", fontsize=12)
-        ax.set_ylabel("Flags", fontsize=12)
-        ax.set_title("SREG Flag Activity", fontsize=14, pad=20)
-        ax.set_yticks([i * 1.2 + 0.5 for i in range(8)])
-        ax.set_yticklabels(flag_names)
-        ax.legend(loc="upper right", ncol=8, fontsize=10)
-        ax.grid(True, alpha=0.2, axis="x")
-        plt.tight_layout()
-        plt.show()
-
-    def show_statistics(self, top_n: int = 10):
-        """Plot execution summary statistics.
-
-        Args:
-            top_n: Number of top memory addresses to show in access frequency.
-        """
-        num_steps = len(self.cpu.step_trace)
-
-        # Count instruction types
-        instr_counts = {}
-        for entry in self.cpu.step_trace:
-            instr = entry.get("instr", "").split()[0]
-            instr_counts[instr] = instr_counts.get(instr, 0) + 1
-
-        # Track memory access frequency
-        mem_access = {}
-        for entry in self.cpu.step_trace:
-            memsnap = entry.get("mem", {})
-            for addr in memsnap.keys():
-                mem_access[addr] = mem_access.get(addr, 0) + 1
-
-        plt.style.use("dark_background")
-        fig, axes = plt.subplots(2, 2, figsize=(14, 10))
-
-        # Instruction frequency
-        sorted_instrs = sorted(instr_counts.items(), key=lambda x: x[1], reverse=True)[
-            :top_n
-        ]
-        if sorted_instrs:
-            instrs, counts = zip(*sorted_instrs)
-            axes[0, 0].barh(instrs, counts, color="skyblue")
-            axes[0, 0].set_xlabel("Count", fontsize=11)
-            axes[0, 0].set_title("Top Instructions", fontsize=12)
-            axes[0, 0].invert_yaxis()
-
-        # Memory access frequency
-        sorted_mem = sorted(mem_access.items(), key=lambda x: x[1], reverse=True)[
-            :top_n
-        ]
-        if sorted_mem:
-            addrs, counts = zip(*sorted_mem)
-            addr_labels = [f"0x{a:04x}" for a in addrs]
-            axes[0, 1].barh(addr_labels, counts, color="lightcoral")
-            axes[0, 1].set_xlabel("Access Count", fontsize=11)
-            axes[0, 1].set_title("Top Memory Accesses", fontsize=12)
-            axes[0, 1].invert_yaxis()
-
-        # Register usage
-        reg_changes = [0] * 32
-        for entry in self.cpu.step_trace:
-            regs = entry.get("regs", [])
-            for r in range(min(32, len(regs))):
-                if r < len(regs) and regs[r] != 0:
-                    reg_changes[r] += 1
-
-        axes[1, 0].bar(range(32), reg_changes, color="mediumseagreen")
-        axes[1, 0].set_xlabel("Register", fontsize=11)
-        axes[1, 0].set_ylabel("Non-zero Count", fontsize=11)
-        axes[1, 0].set_title("Register Usage", fontsize=12)
-        axes[1, 0].set_xticks(range(0, 32, 4))
-
-        # Execution timeline
-        axes[1, 1].text(
-            0.5,
-            0.5,
-            f"Total Instructions: {num_steps}\n"
-            f"Unique Instructions: {len(instr_counts)}\n"
-            f"Memory Locations Accessed: {len(mem_access)}\n"
-            f"Final PC: 0x{self.cpu.pc:04x}\n"
-            f"Final SP: 0x{self.cpu.sp:04x}",
-            ha="center",
-            va="center",
-            fontsize=14,
-            bbox=dict(boxstyle="round", facecolor="wheat", alpha=0.3),
-        )
-        axes[1, 1].set_title("Execution Summary", fontsize=12)
-        axes[1, 1].axis("off")
-
-        plt.tight_layout()
-        plt.show()
diff --git a/tests/test_arithmetic.py b/tests/test_arithmetic.py
index 6074a69..c9534a8 100644
--- a/tests/test_arithmetic.py
+++ b/tests/test_arithmetic.py
@@ -1,6 +1,6 @@
 """Test suite for arithmetic instructions.
 
-Covers: ADD, ADC, SUB, SUBI, SBC, SBCI, INC, DEC, MUL, DIV, NEG, ADIW, SBIW
+Covers: ADD, ADC, SUB, SUBI, SBC, SBCI, INC, DEC, MUL, NEG, ADIW, SBIW
 """
 
 import pytest
@@ -291,9 +291,9 @@ def test_mul_with_overflow(self, cpu_with_program, helper):
             ldi r3, 100
             mul r2, r3
         """)
-        # 200 * 100 = 20000 = 0x4E20
-        helper.assert_register(cpu, 2, 0x20)  # Low byte
-        helper.assert_register(cpu, 3, 0x4E)  # High byte
+        # 200 * 100 = 20000 = 0x4E20 -> R1:R0 = 0x4E:0x20 per AVR DS40002198A
+        helper.assert_register(cpu, 0, 0x20)  # R0: Low byte
+        helper.assert_register(cpu, 1, 0x4E)  # R1: High byte
 
     def test_mul_zero(self, cpu_with_program, helper):
         """Test multiplication by zero."""
@@ -302,8 +302,8 @@ def test_mul_zero(self, cpu_with_program, helper):
             ldi r5, 0
             mul r4, r5
         """)
-        helper.assert_register(cpu, 4, 0)
-        helper.assert_register(cpu, 5, 0)
+        helper.assert_register(cpu, 0, 0)
+        helper.assert_register(cpu, 1, 0)
         helper.assert_flag(cpu, SREG_Z, True, "Z")
 
     @pytest.mark.parametrize(
@@ -319,70 +319,14 @@ def test_mul_zero(self, cpu_with_program, helper):
     def test_mul_parametrized(self, cpu_with_program, helper, a, b, low, high):
         """Test MUL with various input combinations."""
         cpu = cpu_with_program(f"""
-            ldi r0, {a}
-            ldi r1, {b}
-            mul r0, r1
+            ldi r2, {a}
+            ldi r3, {b}
+            mul r2, r3
         """)
         helper.assert_register(cpu, 0, low)
         helper.assert_register(cpu, 1, high)
 
 
-class TestDIV:
-    """Test DIV (Division) instruction."""
-
-    def test_div_basic(self, cpu_with_program, helper):
-        """Test basic division."""
-        cpu = cpu_with_program("""
-            ldi r0, 42
-            ldi r1, 7
-            div r0, r1
-        """)
-        helper.assert_register(cpu, 0, 6)  # Quotient
-        helper.assert_register(cpu, 1, 0)  # Remainder
-
-    def test_div_with_remainder(self, cpu_with_program, helper):
-        """Test division with remainder."""
-        cpu = cpu_with_program("""
-            ldi r2, 100
-            ldi r3, 7
-            div r2, r3
-        """)
-        helper.assert_register(cpu, 2, 14)  # 100 // 7 = 14
-        helper.assert_register(cpu, 3, 2)  # 100 % 7 = 2
-
-    def test_div_by_one(self, cpu_with_program, helper):
-        """Test division by 1."""
-        cpu = cpu_with_program("""
-            ldi r4, 123
-            ldi r5, 1
-            div r4, r5
-        """)
-        helper.assert_register(cpu, 4, 123)
-        helper.assert_register(cpu, 5, 0)
-
-    @pytest.mark.parametrize(
-        "dividend,divisor,quotient,remainder",
-        [
-            (10, 3, 3, 1),
-            (20, 4, 5, 0),
-            (255, 16, 15, 15),
-            (100, 100, 1, 0),
-            (7, 10, 0, 7),
-        ],
-    )
-    def test_div_parametrized(
-        self, cpu_with_program, helper, dividend, divisor, quotient, remainder
-    ):
-        """Test DIV with various input combinations."""
-        cpu = cpu_with_program(f"""
-            ldi r0, {dividend}
-            ldi r1, {divisor}
-            div r0, r1
-        """)
-        helper.assert_register(cpu, 0, quotient)
-        helper.assert_register(cpu, 1, remainder)
-
-
 class TestNEG:
     """Test NEG (Two's complement negation) instruction."""
 
@@ -436,3 +380,33 @@ def test_sbiw_basic(self, cpu_with_program, helper):
         """)
         helper.assert_register(cpu, 24, 0x02)
         helper.assert_register(cpu, 25, 0x00)
+
+    def test_adiw_preserves_h_flag(self, cpu_with_program, helper):
+        """Test ADIW preserves H flag per AVR DS40002198A."""
+        cpu = cpu_with_program("""
+            ldi r24, 0xFF
+            ldi r25, 0x00
+            adiw r24, 1
+        """)
+        cpu.set_flag(SREG_H, True)
+        cpu.step()  # ldi
+        cpu.step()  # ldi
+        cpu.step()  # adiw
+        helper.assert_flag(cpu, SREG_H, True, "H")
+        helper.assert_register(cpu, 24, 0x00)
+        helper.assert_register(cpu, 25, 0x01)
+        helper.assert_flag(cpu, SREG_Z, False, "Z")
+
+    def test_sbiw_preserves_h_flag(self, cpu_with_program, helper):
+        """Test SBIW preserves H flag per AVR DS40002198A."""
+        cpu = cpu_with_program("""
+            ldi r24, 0x01
+            ldi r25, 0x00
+            sbiw r24, 1
+        """)
+        cpu.set_flag(SREG_H, True)
+        cpu.step()  # ldi
+        cpu.step()  # ldi
+        cpu.step()  # sbiw
+        helper.assert_flag(cpu, SREG_H, True, "H")
+        helper.assert_flag(cpu, SREG_Z, True, "Z")
diff --git a/tests/test_assembler.py b/tests/test_assembler.py
index 4ebf3d5..20380db 100644
--- a/tests/test_assembler.py
+++ b/tests/test_assembler.py
@@ -91,3 +91,12 @@ def test_assemble_file_with_actual_file(self, tmp_path):
 
         result = assemble_file(str(asm_file))
         assert len(result.program) == 2
+
+    def test_parse_number_empty_token(self):
+        """Test parsing empty token or hash only raises ValueError."""
+        from tiny8.assembler import _parse_number
+
+        with pytest.raises(ValueError, match="Unable to parse numeric token"):
+            _parse_number("")
+        with pytest.raises(ValueError, match="Unable to parse numeric token"):
+            _parse_number("#")
diff --git a/tests/test_cli.py b/tests/test_cli.py
deleted file mode 100644
index 9a10abd..0000000
--- a/tests/test_cli.py
+++ /dev/null
@@ -1,794 +0,0 @@
-"""Comprehensive tests for CLI module functions.
-
-Tests command parsing, state management, and utility functions
-without requiring actual terminal/curses interaction.
-"""
-
-import time
-
-from tiny8 import CPU, assemble
-from tiny8.cli import KeyContext, ViewState, format_byte, run_command
-
-
-class TestFormatByte:
-    """Test byte formatting utility."""
-
-    def test_format_byte_zero(self):
-        """Test formatting zero."""
-        assert format_byte(0) == "00"
-
-    def test_format_byte_single_digit(self):
-        """Test formatting single digit values."""
-        assert format_byte(1) == "01"
-        assert format_byte(9) == "09"
-        assert format_byte(15) == "0F"
-
-    def test_format_byte_two_digit(self):
-        """Test formatting two digit values."""
-        assert format_byte(16) == "10"
-        assert format_byte(255) == "FF"
-        assert format_byte(128) == "80"
-
-    def test_format_byte_various(self):
-        """Test formatting various byte values."""
-        assert format_byte(0x42) == "42"
-        assert format_byte(0xAB) == "AB"
-        assert format_byte(0xCD) == "CD"
-
-
-class TestRunCommandNumeric:
-    """Test numeric command parsing."""
-
-    def test_absolute_step_valid(self):
-        """Test jumping to absolute step number."""
-        state = ViewState()
-        traces = [{"step": i} for i in range(10)]
-
-        result = run_command(state, traces)
-        state.command_buffer = "5"
-        result = run_command(state, traces)
-
-        assert "→ step 5" in result
-        assert state.step_idx == 5
-        assert state.scroll_offset == 0
-
-    def test_absolute_step_zero(self):
-        """Test jumping to step zero."""
-        state = ViewState(step_idx=5)
-        traces = [{"step": i} for i in range(10)]
-        state.command_buffer = "0"
-
-        result = run_command(state, traces)
-
-        assert "→ step 0" in result
-        assert state.step_idx == 0
-
-    def test_absolute_step_invalid_too_large(self):
-        """Test invalid step number (too large)."""
-        state = ViewState()
-        traces = [{"step": i} for i in range(10)]
-        state.command_buffer = "20"
-
-        result = run_command(state, traces)
-
-        assert "Invalid" in result
-        assert state.step_idx == 0  # Should not change
-
-    def test_absolute_step_invalid_negative(self):
-        """Test invalid step number (negative shown as invalid)."""
-        state = ViewState()
-        traces = [{"step": i} for i in range(10)]
-        state.command_buffer = "-5"
-
-        result = run_command(state, traces)
-
-        assert state.step_idx == 0 or "Invalid" in result
-
-
-class TestRunCommandRelative:
-    """Test relative jump commands."""
-
-    def test_relative_forward(self):
-        """Test jumping forward relative steps."""
-        state = ViewState(step_idx=5)
-        traces = [{"step": i} for i in range(20)]
-        state.command_buffer = "+3"
-
-        result = run_command(state, traces)
-
-        assert "→ step 8" in result
-        assert state.step_idx == 8
-
-    def test_relative_backward(self):
-        """Test jumping backward relative steps."""
-        state = ViewState(step_idx=10)
-        traces = [{"step": i} for i in range(20)]
-        state.command_buffer = "-5"
-
-        result = run_command(state, traces)
-
-        assert "→ step 5" in result
-        assert state.step_idx == 5
-
-    def test_relative_forward_out_of_bounds(self):
-        """Test relative forward beyond trace length."""
-        state = ViewState(step_idx=8)
-        traces = [{"step": i} for i in range(10)]
-        state.command_buffer = "+10"
-
-        result = run_command(state, traces)
-
-        assert "Invalid" in result
-        assert state.step_idx == 8  # Should not change
-
-    def test_relative_backward_out_of_bounds(self):
-        """Test relative backward beyond start."""
-        state = ViewState(step_idx=3)
-        traces = [{"step": i} for i in range(10)]
-        state.command_buffer = "-5"
-
-        result = run_command(state, traces)
-
-        assert "Invalid" in result
-        assert state.step_idx == 3  # Should not change
-
-
-class TestRunCommandSearch:
-    """Test instruction search commands."""
-
-    def test_forward_search_found(self):
-        """Test forward search finding instruction."""
-        state = ViewState(step_idx=0)
-        traces = [
-            {"step": 0, "instr": "LDI R16, 42"},
-            {"step": 1, "instr": "LDI R17, 100"},
-            {"step": 2, "instr": "ADD R16, R17"},
-        ]
-        state.command_buffer = "/add"
-
-        result = run_command(state, traces)
-
-        assert "Found at step 2" in result
-        assert "ADD" in result
-        assert state.step_idx == 2
-
-    def test_forward_search_case_insensitive(self):
-        """Test forward search is case insensitive."""
-        state = ViewState(step_idx=0)
-        traces = [
-            {"step": 0, "instr": "LDI R16, 42"},
-            {"step": 1, "instr": "ADD R16, R17"},
-        ]
-        state.command_buffer = "/ADD"
-
-        result = run_command(state, traces)
-
-        assert "Found" in result
-        assert state.step_idx == 1
-
-    def test_forward_search_not_found(self):
-        """Test forward search when not found."""
-        state = ViewState(step_idx=0)
-        traces = [
-            {"step": 0, "instr": "LDI R16, 42"},
-            {"step": 1, "instr": "LDI R17, 100"},
-        ]
-        state.command_buffer = "/mul"
-
-        result = run_command(state, traces)
-
-        assert "Not found" in result
-        assert state.step_idx == 0  # Should not change
-
-    def test_forward_search_empty(self):
-        """Test forward search with empty pattern."""
-        state = ViewState(step_idx=0)
-        traces = [{"step": 0, "instr": "LDI R16, 42"}]
-        state.command_buffer = "/"
-
-        result = run_command(state, traces)
-
-        assert "Empty search" in result
-
-    def test_backward_search_found(self):
-        """Test backward search finding instruction."""
-        state = ViewState(step_idx=2)
-        traces = [
-            {"step": 0, "instr": "LDI R16, 42"},
-            {"step": 1, "instr": "LDI R17, 100"},
-            {"step": 2, "instr": "ADD R16, R17"},
-        ]
-        state.command_buffer = "?ldi"
-
-        result = run_command(state, traces)
-
-        assert "Found at step 1" in result
-        assert state.step_idx == 1
-
-    def test_backward_search_not_found(self):
-        """Test backward search when not found."""
-        state = ViewState(step_idx=2)
-        traces = [
-            {"step": 0, "instr": "LDI R16, 42"},
-            {"step": 1, "instr": "LDI R17, 100"},
-            {"step": 2, "instr": "ADD R16, R17"},
-        ]
-        state.command_buffer = "?mul"
-
-        result = run_command(state, traces)
-
-        assert "Not found" in result
-        assert state.step_idx == 2
-
-
-class TestRunCommandPCJump:
-    """Test PC address jump commands."""
-
-    def test_pc_jump_decimal(self):
-        """Test jumping to PC address in decimal."""
-        state = ViewState()
-        traces = [
-            {"step": 0, "pc": 0},
-            {"step": 1, "pc": 1},
-            {"step": 2, "pc": 100},
-        ]
-        state.command_buffer = "@100"
-
-        result = run_command(state, traces)
-
-        assert "→ step 2" in result
-        assert "PC=0x0064" in result
-        assert state.step_idx == 2
-
-    def test_pc_jump_hex(self):
-        """Test jumping to PC address in hex."""
-        state = ViewState()
-        traces = [
-            {"step": 0, "pc": 0},
-            {"step": 1, "pc": 1},
-            {"step": 2, "pc": 0x64},
-        ]
-        state.command_buffer = "@0x64"
-
-        result = run_command(state, traces)
-
-        assert "→ step 2" in result
-        assert state.step_idx == 2
-
-    def test_pc_jump_not_found(self):
-        """Test PC jump when address not found."""
-        state = ViewState()
-        traces = [
-            {"step": 0, "pc": 0},
-            {"step": 1, "pc": 1},
-        ]
-        state.command_buffer = "@999"
-
-        result = run_command(state, traces)
-
-        assert "not found" in result
-        assert state.step_idx == 0
-
-    def test_pc_jump_invalid_format(self):
-        """Test PC jump with invalid format."""
-        state = ViewState()
-        traces = [{"step": 0, "pc": 0}]
-        state.command_buffer = "@xyz"
-
-        result = run_command(state, traces)
-
-        assert "Invalid address" in result
-
-
-class TestRunCommandRegister:
-    """Test register tracking and search commands."""
-
-    def test_register_track_change(self):
-        """Test tracking register changes."""
-        state = ViewState(step_idx=0)
-        traces = [
-            {"step": 0, "regs": [0] * 32},
-            {"step": 1, "regs": [0] * 32},
-            {"step": 2, "regs": [42] + [0] * 31},  # R0 changes
-        ]
-        state.command_buffer = "r0"
-
-        result = run_command(state, traces)
-
-        assert "R0 changed at step 2" in result
-        assert "0x2A" in result
-        assert state.step_idx == 2
-
-    def test_register_track_no_change(self):
-        """Test tracking register that doesn't change."""
-        state = ViewState(step_idx=0)
-        traces = [
-            {"step": 0, "regs": [0] * 32},
-            {"step": 1, "regs": [0] * 32},
-        ]
-        state.command_buffer = "r16"
-
-        result = run_command(state, traces)
-
-        assert "doesn't change" in result
-        assert state.step_idx == 0
-
-    def test_register_search_value_decimal(self):
-        """Test searching for register value in decimal."""
-        state = ViewState(step_idx=0)
-        traces = [
-            {"step": 0, "regs": [0] * 32},
-            {"step": 1, "regs": [42] + [0] * 31},
-        ]
-        state.command_buffer = "r0=42"
-
-        result = run_command(state, traces)
-
-        assert "R0=0x2A at step 1" in result
-        assert state.step_idx == 1
-
-    def test_register_search_value_hex(self):
-        """Test searching for register value in hex."""
-        state = ViewState(step_idx=0)
-        traces = [
-            {"step": 0, "regs": [0] * 32},
-            {"step": 1, "regs": [255] + [0] * 31},
-        ]
-        state.command_buffer = "r0=0xFF"
-
-        result = run_command(state, traces)
-
-        assert "R0=0xFF at step 1" in result
-        assert state.step_idx == 1
-
-    def test_register_search_not_found(self):
-        """Test register search when value not found."""
-        state = ViewState(step_idx=0)
-        traces = [
-            {"step": 0, "regs": [0] * 32},
-            {"step": 1, "regs": [42] + [0] * 31},
-        ]
-        state.command_buffer = "r0=99"
-
-        result = run_command(state, traces)
-
-        assert "not found" in result
-
-    def test_register_invalid_number(self):
-        """Test invalid register number."""
-        state = ViewState()
-        traces = [{"step": 0, "regs": [0] * 32}]
-        state.command_buffer = "r32"
-
-        result = run_command(state, traces)
-
-        assert "Invalid register" in result
-
-    def test_register_invalid_format(self):
-        """Test invalid register command format."""
-        state = ViewState()
-        traces = [{"step": 0, "regs": [0] * 32}]
-        state.command_buffer = "rabc"
-
-        result = run_command(state, traces)
-
-        assert "Invalid" in result
-
-
-class TestRunCommandMemory:
-    """Test memory tracking and search commands."""
-
-    def test_memory_track_change(self):
-        """Test tracking memory changes."""
-        state = ViewState(step_idx=0)
-        traces = [
-            {"step": 0, "mem": {}},
-            {"step": 1, "mem": {}},
-            {"step": 2, "mem": {100: 0x42}},
-        ]
-        state.command_buffer = "m100"
-
-        result = run_command(state, traces)
-
-        assert "Mem[0x0064] changed at step 2" in result
-        assert "0x42" in result
-        assert state.step_idx == 2
-
-    def test_memory_track_no_change(self):
-        """Test tracking memory that doesn't change."""
-        state = ViewState(step_idx=0)
-        traces = [
-            {"step": 0, "mem": {}},
-            {"step": 1, "mem": {}},
-        ]
-        state.command_buffer = "m100"
-
-        result = run_command(state, traces)
-
-        assert "doesn't change" in result
-
-    def test_memory_search_value_decimal(self):
-        """Test searching for memory value in decimal."""
-        state = ViewState(step_idx=0)
-        traces = [
-            {"step": 0, "mem": {}},
-            {"step": 1, "mem": {100: 42}},
-        ]
-        state.command_buffer = "m100=42"
-
-        result = run_command(state, traces)
-
-        assert "Mem[0x0064]=0x2A at step 1" in result
-        assert state.step_idx == 1
-
-    def test_memory_search_value_hex(self):
-        """Test searching for memory value in hex."""
-        state = ViewState(step_idx=0)
-        traces = [
-            {"step": 0, "mem": {}},
-            {"step": 1, "mem": {0x64: 0xFF}},
-        ]
-        state.command_buffer = "m0x64=0xFF"
-
-        result = run_command(state, traces)
-
-        assert "at step 1" in result
-        assert state.step_idx == 1
-
-    def test_memory_search_not_found(self):
-        """Test memory search when value not found."""
-        state = ViewState(step_idx=0)
-        traces = [
-            {"step": 0, "mem": {}},
-            {"step": 1, "mem": {100: 42}},
-        ]
-        state.command_buffer = "m100=99"
-
-        result = run_command(state, traces)
-
-        assert "not found" in result
-
-    def test_memory_invalid_format(self):
-        """Test invalid memory command format."""
-        state = ViewState()
-        traces = [{"step": 0, "mem": {}}]
-        state.command_buffer = "mxyz"
-
-        result = run_command(state, traces)
-
-        assert "Invalid" in result
-
-
-class TestRunCommandFlag:
-    """Test flag tracking and search commands."""
-
-    def test_flag_track_zero_change(self):
-        """Test tracking Zero flag changes."""
-        state = ViewState(step_idx=0)
-        traces = [
-            {"step": 0, "sreg": 0b00000000},  # Z=0
-            {"step": 1, "sreg": 0b00000010},  # Z=1
-        ]
-        state.command_buffer = "fZ"
-
-        result = run_command(state, traces)
-
-        assert "Flag Z changed at step 1" in result
-        assert state.step_idx == 1
-
-    def test_flag_track_carry_change(self):
-        """Test tracking Carry flag changes."""
-        state = ViewState(step_idx=0)
-        traces = [
-            {"step": 0, "sreg": 0b00000000},  # C=0
-            {"step": 1, "sreg": 0b00000001},  # C=1
-        ]
-        state.command_buffer = "fC"
-
-        result = run_command(state, traces)
-
-        assert "Flag C changed at step 1" in result
-        assert state.step_idx == 1
-
-    def test_flag_track_no_change(self):
-        """Test tracking flag that doesn't change."""
-        state = ViewState(step_idx=0)
-        traces = [
-            {"step": 0, "sreg": 0b00000000},
-            {"step": 1, "sreg": 0b00000000},
-        ]
-        state.command_buffer = "fZ"
-
-        result = run_command(state, traces)
-
-        assert "doesn't change" in result
-
-    def test_flag_search_value_set(self):
-        """Test searching for flag set (=1)."""
-        state = ViewState(step_idx=0)
-        traces = [
-            {"step": 0, "sreg": 0b00000000},
-            {"step": 1, "sreg": 0b00000010},  # Z=1
-        ]
-        state.command_buffer = "fZ=1"
-
-        result = run_command(state, traces)
-
-        assert "Flag Z=1 at step 1" in result
-        assert state.step_idx == 1
-
-    def test_flag_search_value_clear(self):
-        """Test searching for flag clear (=0)."""
-        state = ViewState(step_idx=0)
-        traces = [
-            {"step": 0, "sreg": 0b00000010},  # Z=1
-            {"step": 1, "sreg": 0b00000000},  # Z=0
-        ]
-        state.command_buffer = "fZ=0"
-
-        result = run_command(state, traces)
-
-        assert "Flag Z=0 at step 1" in result
-        assert state.step_idx == 1
-
-    def test_flag_all_flags(self):
-        """Test all flag names."""
-        flags = ["I", "T", "H", "S", "V", "N", "Z", "C"]
-        state = ViewState(step_idx=0)
-        traces = [
-            {"step": 0, "sreg": 0b00000000},
-            {"step": 1, "sreg": 0b11111111},  # All flags set
-        ]
-
-        for flag in flags:
-            state.step_idx = 0
-            state.command_buffer = f"f{flag}"
-            result = run_command(state, traces)
-            assert "changed" in result
-
-    def test_flag_case_insensitive(self):
-        """Test flag names are case insensitive."""
-        state = ViewState(step_idx=0)
-        traces = [
-            {"step": 0, "sreg": 0b00000000},
-            {"step": 1, "sreg": 0b00000010},
-        ]
-        state.command_buffer = "fz"  # lowercase
-
-        result = run_command(state, traces)
-
-        assert "Flag Z changed" in result
-
-    def test_flag_invalid_name(self):
-        """Test invalid flag name."""
-        state = ViewState()
-        traces = [{"step": 0, "sreg": 0}]
-        state.command_buffer = "fX"
-
-        result = run_command(state, traces)
-
-        assert "Invalid flag" in result
-
-    def test_flag_invalid_value(self):
-        """Test invalid flag value."""
-        state = ViewState()
-        traces = [{"step": 0, "sreg": 0}]
-        state.command_buffer = "fZ=2"
-
-        result = run_command(state, traces)
-
-        assert "must be 0 or 1" in result
-
-
-class TestRunCommandMisc:
-    """Test miscellaneous commands."""
-
-    def test_help_command_h(self):
-        """Test help command with 'h'."""
-        state = ViewState()
-        traces = [{"step": 0}]
-        state.command_buffer = "h"
-
-        result = run_command(state, traces)
-
-        assert "Commands:" in result
-        assert "NUM" in result
-
-    def test_help_command_help(self):
-        """Test help command with 'help'."""
-        state = ViewState()
-        traces = [{"step": 0}]
-        state.command_buffer = "help"
-
-        result = run_command(state, traces)
-
-        assert "Commands:" in result
-
-    def test_unknown_command(self):
-        """Test unknown command."""
-        state = ViewState()
-        traces = [{"step": 0}]
-        state.command_buffer = "xyz123"
-
-        result = run_command(state, traces)
-
-        assert "Unknown:" in result
-
-    def test_empty_command(self):
-        """Test empty command."""
-        state = ViewState()
-        traces = [{"step": 0}]
-        state.command_buffer = ""
-
-        result = run_command(state, traces)
-
-        assert "Unknown:" in result or result == ""
-
-
-class TestRunCommandIntegration:
-    """Integration tests with actual CPU traces."""
-
-    def test_command_with_real_trace(self):
-        """Test commands with actual CPU execution trace."""
-        cpu = CPU()
-        asm = assemble("""
-            ldi r16, 10
-            ldi r17, 20
-            add r16, r17
-            ldi r18, 100
-        """)
-        cpu.load_program(asm)
-        cpu.run()
-
-        traces = cpu.step_trace
-        state = ViewState()
-
-        state.command_buffer = "/add"
-        result = run_command(state, traces)
-        assert "Found" in result
-
-        state.step_idx = 0
-        state.command_buffer = "r16=30"
-        result = run_command(state, traces)
-        assert "R16=0x1E" in result or "not found" in result
-
-    def test_multiple_commands_sequence(self):
-        """Test sequence of different commands."""
-        cpu = CPU()
-        asm = assemble("""
-            ldi r16, 1
-            ldi r17, 2
-            add r16, r17
-        """)
-        cpu.load_program(asm)
-        cpu.run()
-
-        traces = cpu.step_trace
-        state = ViewState()
-
-        state.command_buffer = "1"
-        run_command(state, traces)
-        assert state.step_idx == 1
-
-        state.command_buffer = "+1"
-        run_command(state, traces)
-        assert state.step_idx == 2
-
-        state.command_buffer = "-1"
-        run_command(state, traces)
-        assert state.step_idx == 1
-
-
-class TestKeyContext:
-    """Test KeyContext methods."""
-
-    def test_set_status(self):
-        """Test setting status message."""
-        state = ViewState()
-        ctx = KeyContext(
-            state=state,
-            scr=None,
-            traces=[],
-            cpu=None,
-            mem_addr_start=0,
-            mem_addr_end=31,
-            source_lines=None,
-            n=0,
-        )
-
-        before_time = time.time()
-        ctx.set_status("Test message")
-        after_time = time.time()
-
-        assert state.status_msg == "Test message"
-        assert state.status_time >= before_time
-        assert state.status_time <= after_time
-
-    def test_set_status_multiple_times(self):
-        """Test setting status message multiple times."""
-        state = ViewState()
-        ctx = KeyContext(
-            state=state,
-            scr=None,
-            traces=[],
-            cpu=None,
-            mem_addr_start=0,
-            mem_addr_end=31,
-            source_lines=None,
-            n=0,
-        )
-
-        ctx.set_status("First message")
-        first_time = state.status_time
-
-        time.sleep(0.01)  # Small delay to ensure time changes
-
-        ctx.set_status("Second message")
-        second_time = state.status_time
-
-        assert state.status_msg == "Second message"
-        assert second_time > first_time
-
-
-class TestKeyHandlerDecorator:
-    """Test the key_handler decorator."""
-
-    def test_key_handler_decorator_registration(self):
-        """Test that key_handler decorator registers handlers correctly."""
-        from tiny8.cli import _key_handlers
-
-        assert ord("q") in _key_handlers
-        assert 27 in _key_handlers
-        assert ord(" ") in _key_handlers
-        assert ord("l") in _key_handlers
-        assert ord("h") in _key_handlers
-        assert ord("w") in _key_handlers
-        assert ord("b") in _key_handlers
-
-
-class TestViewStateDefaults:
-    """Test ViewState default values."""
-
-    def test_viewstate_defaults(self):
-        """Test ViewState initializes with correct defaults."""
-        state = ViewState()
-
-        assert state.step_idx == 0
-        assert state.scroll_offset == 0
-        assert not state.playing
-        assert state.last_advance_time == 0.0
-        assert state.delay == 0.15
-        assert state.show_all_regs
-        assert not state.show_all_mem
-        assert not state.command_mode
-        assert state.command_buffer == ""
-        assert state.marks == {}
-        assert state.status_msg == ""
-        assert state.status_time == 0.0
-
-    def test_viewstate_custom_values(self):
-        """Test ViewState with custom values."""
-        marks = {"a": 10, "b": 20}
-        state = ViewState(
-            step_idx=5,
-            scroll_offset=3,
-            playing=True,
-            delay=0.5,
-            show_all_regs=False,
-            show_all_mem=True,
-            command_mode=True,
-            command_buffer="test",
-            marks=marks,
-            status_msg="Status",
-        )
-
-        assert state.step_idx == 5
-        assert state.scroll_offset == 3
-        assert state.playing
-        assert state.delay == 0.5
-        assert not state.show_all_regs
-        assert state.show_all_mem
-        assert state.command_mode
-        assert state.command_buffer == "test"
-        assert state.marks == marks
-        assert state.status_msg == "Status"
diff --git a/tests/test_compiler.py b/tests/test_compiler.py
new file mode 100644
index 0000000..9ab8aaa
--- /dev/null
+++ b/tests/test_compiler.py
@@ -0,0 +1,300 @@
+"""Unit tests for Tiny8 C compiler."""
+
+from tiny8 import CPU, assemble
+from tiny8.compiler import compile_c, optimize_assembly
+
+
+def test_compiler_variable_and_arithmetic():
+    c_code = """
+    int main() {
+        int a = 10;
+        int b = 25;
+        int c = a + b;
+        poke(0x80, c);
+        return 0;
+    }
+    """
+    asm = compile_c(c_code)
+    asm_res = assemble(asm)
+    cpu = CPU()
+    cpu.load_program(asm_res)
+    cpu.run(max_steps=100, show_progress=False)
+
+    # 10 + 25 = 35
+    assert cpu.read_ram(0x80) == 35
+
+
+def test_compiler_while_loop():
+    c_code = """
+    int main() {
+        int sum = 0;
+        int i = 5;
+        while (i > 0) {
+            sum = sum + i;
+            i = i - 1;
+        }
+        poke(0x81, sum);
+        return 0;
+    }
+    """
+    asm = compile_c(c_code)
+    asm_res = assemble(asm)
+    cpu = CPU()
+    cpu.load_program(asm_res)
+    cpu.run(max_steps=200, show_progress=False)
+
+    # 5 + 4 + 3 + 2 + 1 = 15
+    assert cpu.read_ram(0x81) == 15
+
+
+def test_compiler_if_else():
+    c_code = """
+    int main() {
+        int x = 20;
+        int res = 0;
+        if (x < 15) {
+            res = 1;
+        } else {
+            res = 2;
+        }
+        poke(0x82, res);
+        return 0;
+    }
+    """
+    asm = compile_c(c_code)
+    asm_res = assemble(asm)
+    cpu = CPU()
+    cpu.load_program(asm_res)
+    cpu.run(max_steps=100, show_progress=False)
+
+    assert cpu.read_ram(0x82) == 2
+
+
+def test_compiler_function_call():
+    c_code = """
+    int double_val(int x) {
+        return x * 2;
+    }
+
+    int main() {
+        int val = double_val(21);
+        poke(0x83, val);
+        return 0;
+    }
+    """
+    asm = compile_c(c_code)
+    asm_res = assemble(asm)
+    cpu = CPU()
+    cpu.load_program(asm_res)
+    cpu.run(max_steps=150, show_progress=False)
+
+    # 21 * 2 = 42
+    assert cpu.read_ram(0x83) == 42
+
+
+def test_compiler_for_loop_and_break():
+    c_code = """
+    int main() {
+        int sum = 0;
+        int i = 0;
+        for (i = 0; i < 10; i = i + 1) {
+            if (i == 4) {
+                break;
+            }
+            sum = sum + i;
+        }
+        poke(0x84, sum);
+        return 0;
+    }
+    """
+    asm = compile_c(c_code)
+    asm_res = assemble(asm)
+    cpu = CPU()
+    cpu.load_program(asm_res)
+    cpu.run(max_steps=300, show_progress=False)
+
+    # 0 + 1 + 2 + 3 = 6
+    assert cpu.read_ram(0x84) == 6
+
+
+def test_compiler_array():
+    c_code = """
+    int main() {
+        int arr[4];
+        arr[0] = 10;
+        arr[1] = 20;
+        arr[2] = 30;
+        arr[3] = arr[0] + arr[1] + arr[2];
+        poke(0x85, arr[3]);
+        return 0;
+    }
+    """
+    asm = compile_c(c_code)
+    asm_res = assemble(asm)
+    cpu = CPU()
+    cpu.load_program(asm_res)
+    cpu.run(max_steps=300, show_progress=False)
+
+    assert cpu.read_ram(0x85) == 60
+
+
+def test_compiler_vram():
+    c_code = """
+    int main() {
+        vram_set(2, 3, 5);
+        int v = vram_get(2, 3);
+        poke(0x86, v);
+        return 0;
+    }
+    """
+    asm = compile_c(c_code)
+    asm_res = assemble(asm)
+    cpu = CPU()
+    cpu.load_program(asm_res)
+    cpu.run(max_steps=200, show_progress=False)
+
+    # 0x0200 + 3*32 + 2 = 0x0200 + 98 = 610
+    assert cpu.read_ram(512 + 3 * 32 + 2) == 5
+    assert cpu.read_ram(0x86) == 5
+
+
+def test_compiler_char_literals():
+    c_code = """
+    int main() {
+        char ch = 'T';
+        poke(0x87, ch);
+        vram_set(0, 0, 'O');
+        int v = vram_get(0, 0);
+        poke(0x88, v);
+        return 0;
+    }
+    """
+    asm = compile_c(c_code)
+    asm_res = assemble(asm)
+    cpu = CPU()
+    cpu.load_program(asm_res)
+    cpu.run(max_steps=200, show_progress=False)
+
+    assert cpu.read_ram(0x87) == ord("T")
+    assert cpu.read_ram(512) == ord("O")
+    assert cpu.read_ram(0x88) == ord("O")
+
+
+def test_compiler_vram_puts():
+    c_code = """
+    int main() {
+        vram_puts(14, 1, "TINY8");
+        return 0;
+    }
+    """
+    asm = compile_c(c_code)
+    asm_res = assemble(asm)
+    cpu = CPU()
+    cpu.load_program(asm_res)
+    cpu.run(max_steps=200, show_progress=False)
+
+    # row 1, col 14: 0x0200 + 1*32 + 14 = 512 + 32 + 14 = 558
+    assert "".join(chr(cpu.read_ram(558 + i)) for i in range(5)) == "TINY8"
+
+
+def test_compiler_array_initializer():
+    c_code = """
+    int g_arr[3] = {10, 20, 30};
+    int main() {
+        int l_arr[] = {40, 50};
+        poke(0x70, g_arr[1]);
+        poke(0x71, l_arr[0]);
+        poke(0x72, l_arr[1]);
+        return 0;
+    }
+    """
+    asm = compile_c(c_code)
+    asm_res = assemble(asm)
+    cpu = CPU()
+    cpu.load_program(asm_res)
+    cpu.run(max_steps=500, show_progress=False)
+
+    assert cpu.read_ram(0x70) == 20
+    assert cpu.read_ram(0x71) == 40
+    assert cpu.read_ram(0x72) == 50
+
+
+class TestCompilerOptimization:
+    """Unit tests for compiler peephole optimization and constant folding."""
+
+    def test_constant_folding_basic_arithmetic(self):
+        """Verify that arithmetic on literals is folded at compile time."""
+        src = """
+        int main() {
+            int x = 10 + 20 * 2;
+            return x;
+        }
+        """
+        asm = compile_c(src, optimize=True)
+        # 10 + 20 * 2 = 50 -> should emit LDI R16, 50 directly without ADD/MUL
+        assert "LDI R16, 50" in asm
+        assert "ADD" not in asm
+        assert "MUL" not in asm
+
+    def test_constant_folding_bitwise_and_logic(self):
+        """Verify bitwise and relational expressions are folded at compile time."""
+        src = """
+        int main() {
+            int a = 0xFF & 0x0F;
+            int b = 5 > 2;
+            int c = !0;
+            return a + b + c;
+        }
+        """
+        asm = compile_c(src, optimize=True)
+        assert "LDI R16, 15" in asm  # 0xFF & 0x0F = 15
+        assert "LDI R16, 1" in asm  # 5 > 2 = 1, !0 = 1
+
+    def test_peephole_remove_redundant_mov(self):
+        """Verify that MOV Rx, Rx is eliminated."""
+        lines = [
+            "    LDI R16, 42",
+            "    MOV R16, R16",
+            "    MOV R17, R17",
+            "    RET",
+        ]
+        opt = optimize_assembly(lines)
+        assert opt == ["    LDI R16, 42", "    RET"]
+
+    def test_peephole_push_pop_simplification(self):
+        """Verify PUSH Rx; POP Ry becomes MOV Ry, Rx and PUSH Rx; POP Rx is eliminated."""
+        lines = [
+            "    PUSH R16",
+            "    POP R17",
+            "    PUSH R18",
+            "    POP R18",
+            "    RET",
+        ]
+        opt = optimize_assembly(lines)
+        assert opt == ["    MOV R17, R16", "    RET"]
+
+    def test_peephole_remove_redundant_store_reload(self):
+        """Verify store followed immediately by reload is eliminated."""
+        lines = [
+            "    LDI R30, 96",
+            "    ST R30, R16",
+            "    LDI R30, 96",
+            "    LD R16, R30",
+            "    RET",
+        ]
+        opt = optimize_assembly(lines)
+        assert opt == [
+            "    LDI R30, 96",
+            "    ST R30, R16",
+            "    RET",
+        ]
+
+    def test_peephole_remove_jump_to_next_label(self):
+        """Verify JMP target immediately preceding target: is removed."""
+        lines = [
+            "    JMP loop",
+            "loop:",
+            "    NOP",
+        ]
+        opt = optimize_assembly(lines)
+        assert opt == ["loop:", "    NOP"]
diff --git a/tests/test_control_flow.py b/tests/test_control_flow.py
index f4568c3..b2f96b8 100644
--- a/tests/test_control_flow.py
+++ b/tests/test_control_flow.py
@@ -5,7 +5,7 @@
 
 import pytest
 
-from tiny8.cpu import SREG_C, SREG_Z
+from tiny8.cpu import SREG_C, SREG_I, SREG_Z
 
 
 class TestJMP:
@@ -166,6 +166,51 @@ def test_brlt_less_than(self, cpu_with_program, helper):
         """)
         helper.assert_register(cpu, 2, 1)
 
+    def test_brmi_and_brpl_branches(self, cpu_with_program, helper):
+        """Test BRMI (minus) and BRPL (plus) branch behaviors."""
+        # 10 - 20 is negative -> BRMI taken
+        cpu1 = cpu_with_program("""
+            ldi r0, 10
+            ldi r1, 20
+            sub r0, r1
+            brmi minus_taken
+            ldi r2, 0
+            jmp done1
+        minus_taken:
+            ldi r2, 1
+        done1:
+            nop
+        """)
+        helper.assert_register(cpu1, 2, 1)
+
+        # 20 - 10 is positive -> BRPL taken
+        cpu2 = cpu_with_program("""
+            ldi r0, 20
+            ldi r1, 10
+            sub r0, r1
+            brpl plus_taken
+            ldi r2, 0
+            jmp done2
+        plus_taken:
+            ldi r2, 1
+        done2:
+            nop
+        """)
+        helper.assert_register(cpu2, 2, 1)
+
+    def test_branch_with_numeric_target(self, cpu_with_program, helper):
+        """Test branching using explicit numeric instruction address."""
+        cpu = cpu_with_program("""
+            ldi r0, 100
+            ldi r1, 200
+            sub r0, r1
+        """)
+        # Append BRMI jumping directly to instruction index 0
+        cpu.program.append(("BRMI", (0,)))
+        cpu.pc = len(cpu.program) - 1
+        cpu.step()
+        assert cpu.pc == 0
+
     @pytest.mark.parametrize(
         "a,b,branch,expected",
         [
@@ -173,6 +218,8 @@ def test_brlt_less_than(self, cpu_with_program, helper):
             (10, 5, "brne", 1),  # Not equal
             (5, 10, "brcs", 1),  # Carry set (a < b)
             (10, 5, "brcc", 1),  # Carry clear (a >= b)
+            (5, 10, "brlo", 1),  # Lower unsigned
+            (10, 5, "brsh", 1),  # Same or higher unsigned
         ],
     )
     def test_branches_parametrized(
@@ -262,6 +309,21 @@ def test_call_preserves_registers(self, cpu_with_program, helper):
         # 100 + 50 = 150, r1 should be preserved as 200
         helper.assert_registers(cpu, {0: 150, 1: 200})
 
+    def test_reti_restores_interrupt_flag(self, cpu_with_program, helper):
+        """Test RETI restores PC and sets Global Interrupt flag (I=1)."""
+        cpu = cpu_with_program("""
+            cli
+            call isr
+            jmp done
+        isr:
+            ldi r0, 77
+            reti
+        done:
+            nop
+        """)
+        helper.assert_register(cpu, 0, 77)
+        helper.assert_flag(cpu, SREG_I, True, "I")
+
 
 class TestCompare:
     """Test CP, CPC, CPI (Compare) instructions."""
diff --git a/tests/test_cpu_branches.py b/tests/test_cpu_branches.py
deleted file mode 100644
index df9c9dc..0000000
--- a/tests/test_cpu_branches.py
+++ /dev/null
@@ -1,347 +0,0 @@
-"""CPU branch instruction tests.
-
-Tests for conditional branches, stack operations, calls, and returns.
-"""
-
-from tiny8 import CPU, assemble
-
-
-class TestConditionalBranches:
-    """Test conditional branch instructions."""
-
-    def test_brmi_not_taken(self):
-        """Test branch if minus when not taken."""
-        cpu = CPU()
-        asm = assemble("""
-            ldi r16, 100
-            ldi r17, 50
-            sub r16, r17
-            brmi skip
-            ldi r18, 1
-        skip:
-            ldi r19, 2
-        """)
-        cpu.load_program(asm)
-        cpu.run()
-        assert cpu.read_reg(18) == 1  # Not skipped
-
-    def test_brmi_jump_taken(self):
-        """Test BRMI when negative flag is set and jump is taken."""
-        cpu = CPU()
-        asm = assemble("""
-            ldi r16, 100
-            ldi r17, 200
-            sub r16, r17
-            brmi target
-            ldi r18, 1
-        target:
-            ldi r19, 2
-        """)
-        cpu.load_program(asm)
-        cpu.run()
-        # The jump should be taken because 100 - 200 is negative
-        assert cpu.regs[19] == 2
-        assert cpu.regs[18] == 0  # This should not execute
-
-    def test_brpl_not_taken(self):
-        """Test branch if plus when not taken."""
-        cpu = CPU()
-        asm = assemble("""
-            ldi r16, 50
-            ldi r17, 100
-            sub r16, r17
-            brpl skip
-            ldi r18, 1
-        skip:
-            ldi r19, 2
-        """)
-        cpu.load_program(asm)
-        cpu.run()
-        assert cpu.read_reg(18) == 1  # Not skipped
-
-    def test_brpl_jump_taken(self):
-        """Test BRPL when negative flag is clear and jump is taken."""
-        cpu = CPU()
-        asm = assemble("""
-            ldi r16, 200
-            ldi r17, 100
-            sub r16, r17
-            brpl target
-            ldi r18, 1
-        target:
-            ldi r19, 2
-        """)
-        cpu.load_program(asm)
-        cpu.run()
-        # The jump should be taken because 200 - 100 is positive
-        assert cpu.regs[19] == 2
-        assert cpu.regs[18] == 0  # This should not execute
-
-    def test_brge_taken(self):
-        """Test branch if greater or equal when taken."""
-        cpu = CPU()
-        asm = assemble("""
-            ldi r16, 100
-            ldi r17, 50
-            cp r16, r17
-            brge skip
-            ldi r18, 99
-        skip:
-            ldi r19, 1
-        """)
-        cpu.load_program(asm)
-        cpu.run()
-        assert cpu.read_reg(18) == 0  # Skipped
-        assert cpu.read_reg(19) == 1
-
-    def test_brge_not_taken(self):
-        """Test branch if greater or equal when not taken."""
-        cpu = CPU()
-        asm = assemble("""
-            ldi r16, 50
-            ldi r17, 100
-            cp r16, r17
-            brge skip
-            ldi r18, 1
-        skip:
-            ldi r19, 2
-        """)
-        cpu.load_program(asm)
-        cpu.run()
-        assert cpu.read_reg(18) == 1  # Not skipped
-
-    def test_brlt_taken(self):
-        """Test branch if less than when taken."""
-        cpu = CPU()
-        asm = assemble("""
-            ldi r16, 50
-            ldi r17, 100
-            cp r16, r17
-            brlt skip
-            ldi r18, 99
-        skip:
-            ldi r19, 1
-        """)
-        cpu.load_program(asm)
-        cpu.run()
-        assert cpu.read_reg(18) == 0  # Skipped
-        assert cpu.read_reg(19) == 1
-
-    def test_brlt_not_taken(self):
-        """Test branch if less than when not taken."""
-        cpu = CPU()
-        asm = assemble("""
-            ldi r16, 100
-            ldi r17, 50
-            cp r16, r17
-            brlt skip
-            ldi r18, 1
-        skip:
-            ldi r19, 2
-        """)
-        cpu.load_program(asm)
-        cpu.run()
-        assert cpu.read_reg(18) == 1  # Not skipped
-
-    def test_brpl_jump_case(self):
-        """Test BRPL actually jumping."""
-        cpu = CPU()
-        asm = assemble("""
-            ldi r16, 100
-            ldi r17, 50
-            sub r16, r17
-            ldi r18, 0
-            brpl target
-            ldi r18, 99
-        target:
-            ldi r19, 1
-        """)
-        cpu.load_program(asm)
-        cpu.run()
-        # With positive result, should jump and skip r18 assignment
-        assert cpu.read_reg(18) == 0
-
-    def test_brmi_with_integer_label(self):
-        """Test BRMI with integer label."""
-        cpu = CPU()
-        asm = assemble("""
-            ldi r16, 200
-            ldi r17, 100
-            sub r16, r17
-        """)
-        cpu.load_program(asm)
-        cpu.run()
-        # Now manually test brmi with integer
-        cpu.program.append(("BRMI", (0,)))
-        cpu.pc = len(cpu.program) - 1
-        cpu.step()
-
-    def test_brpl_with_integer_label(self):
-        """Test BRPL with integer label."""
-        cpu = CPU()
-        asm = assemble("""
-            ldi r16, 100
-            ldi r17, 50
-            sub r16, r17
-        """)
-        cpu.load_program(asm)
-        cpu.run()
-        # Now manually test brpl with integer
-        cpu.program.append(("BRPL", (0,)))
-        cpu.pc = len(cpu.program) - 1
-        cpu.step()
-
-
-class TestStackAndCall:
-    """Test stack operations, calls, and returns."""
-
-    def test_push_pop(self):
-        """Test push and pop instructions."""
-        cpu = CPU()
-        asm = assemble("""
-            ldi r16, 42
-            push r16
-            ldi r16, 0
-            pop r17
-        """)
-        cpu.load_program(asm)
-        cpu.run()
-        assert cpu.read_reg(17) == 42
-
-    def test_multiple_push_pop(self):
-        """Test multiple push and pop operations."""
-        cpu = CPU()
-        asm = assemble("""
-            ldi r16, 10
-            ldi r17, 20
-            ldi r18, 30
-            push r16
-            push r17
-            push r18
-            pop r19
-            pop r20
-            pop r21
-        """)
-        cpu.load_program(asm)
-        cpu.run()
-        assert cpu.read_reg(19) == 30
-        assert cpu.read_reg(20) == 20
-        assert cpu.read_reg(21) == 10
-
-    def test_call_ret(self):
-        """Test call and ret instructions."""
-        cpu = CPU()
-        asm = assemble("""
-            call func
-            ldi r16, 1
-            jmp done
-        func:
-            ldi r17, 2
-            ret
-        done:
-            nop
-        """)
-        cpu.load_program(asm)
-        cpu.run()
-        assert cpu.read_reg(16) == 1
-        assert cpu.read_reg(17) == 2
-
-    def test_nested_calls(self):
-        """Test nested function calls."""
-        cpu = CPU()
-        asm = assemble("""
-            call func1
-            ldi r16, 1
-            jmp done
-        func1:
-            call func2
-            ldi r17, 2
-            ret
-        func2:
-            ldi r18, 3
-            ret
-        done:
-            nop
-        """)
-        cpu.load_program(asm)
-        cpu.run()
-        assert cpu.read_reg(16) == 1
-        assert cpu.read_reg(17) == 2
-        assert cpu.read_reg(18) == 3
-
-    def test_reti(self):
-        """Test return from interrupt."""
-        cpu = CPU()
-        asm = assemble("""
-            call isr
-            ldi r16, 1
-            jmp done
-        isr:
-            ldi r17, 2
-            reti
-        done:
-            nop
-        """)
-        cpu.load_program(asm)
-        cpu.run()
-        assert cpu.read_reg(16) == 1
-        assert cpu.read_reg(17) == 2
-
-
-class TestSetClearInstructions:
-    """Test SET and CLEAR type instructions."""
-
-    def test_ser_clr(self):
-        """Test SER and CLR instructions."""
-        cpu = CPU()
-        asm = assemble("""
-            ser r16
-            clr r17
-        """)
-        cpu.load_program(asm)
-        cpu.run()
-        assert cpu.read_reg(16) == 0xFF
-        assert cpu.read_reg(17) == 0
-
-    def test_adc_with_carry(self):
-        """Test ADC with carry flag set."""
-        cpu = CPU()
-        asm = assemble("""
-            ldi r16, 5
-            ldi r17, 10
-            add r16, r17
-            ldi r18, 20
-            ldi r19, 30
-            adc r18, r19
-        """)
-        cpu.load_program(asm)
-        cpu.run()
-        # r18 should be 20 + 30 + carry (if any)
-
-
-class TestLogicalOperations:
-    """Test logical operations for branch coverage."""
-
-    def test_or_operation_edge_case(self):
-        """Test OR operation with different values."""
-        cpu = CPU()
-        asm = assemble("""
-            ldi r16, 0x0F
-            ldi r17, 0xF0
-            or r16, r17
-        """)
-        cpu.load_program(asm)
-        cpu.run()
-        assert cpu.read_reg(16) == 0xFF
-
-    def test_eor_operation_edge_case(self):
-        """Test EOR operation with same values."""
-        cpu = CPU()
-        asm = assemble("""
-            ldi r16, 0xFF
-            ldi r17, 0xFF
-            eor r16, r17
-        """)
-        cpu.load_program(asm)
-        cpu.run()
-        assert cpu.read_reg(16) == 0
diff --git a/tests/test_cpu_core.py b/tests/test_cpu_core.py
index 1300b17..6ca87a9 100644
--- a/tests/test_cpu_core.py
+++ b/tests/test_cpu_core.py
@@ -113,19 +113,48 @@ def test_ori_instruction(self):
         cpu.run()
         assert cpu.read_reg(16) == 0b11111111
 
-    def test_eori_instruction(self):
-        """Test XOR with immediate."""
+    def test_asr_instruction(self):
+        """Test arithmetic shift right preserves sign bit and updates flags."""
+        from tiny8.cpu import SREG_C, SREG_N
+
         cpu = CPU()
         asm = assemble("""
-            ldi r16, 0b11110000
-            eori r16, 0b11111111
+            ldi r16, 0b10000001
+            asr r16
         """)
         cpu.load_program(asm)
         cpu.run()
-        assert cpu.read_reg(16) == 0b00001111
+        assert cpu.read_reg(16) == 0b11000000
+        assert cpu.get_flag(SREG_C) is True
+        assert cpu.get_flag(SREG_N) is True
+
+    def test_muls_and_mulsu_instructions(self):
+        """Test signed and signed-with-unsigned multiplications."""
+        cpu = CPU()
+        asm = assemble("""
+            ldi r16, 0xFE
+            ldi r17, 3
+            muls r16, r17
+            ldi r18, 0xFE
+            ldi r19, 100
+            mulsu r18, r19
+        """)
+        cpu.load_program(asm)
+        cpu.step()
+        cpu.step()
+        cpu.step()
+        assert cpu.read_reg(0) == 0xFA
+        assert cpu.read_reg(1) == 0xFF
+        cpu.step()
+        cpu.step()
+        cpu.step()
+        assert cpu.read_reg(0) == 0x38
+        assert cpu.read_reg(1) == 0xFF
 
     def test_tst_instruction(self):
         """Test for zero or negative."""
+        from tiny8.cpu import SREG_N, SREG_Z
+
         cpu = CPU()
         asm = assemble("""
             ldi r16, 0
@@ -133,6 +162,21 @@ def test_tst_instruction(self):
         """)
         cpu.load_program(asm)
         cpu.run()
+        assert cpu.read_reg(16) == 0
+        assert cpu.get_flag(SREG_Z) is True
+        assert cpu.get_flag(SREG_N) is False
+
+        # Also test TST with negative value
+        cpu2 = CPU()
+        asm2 = assemble("""
+            ldi r16, 0x80
+            tst r16
+        """)
+        cpu2.load_program(asm2)
+        cpu2.run()
+        assert cpu2.read_reg(16) == 0x80
+        assert cpu2.get_flag(SREG_N) is True
+        assert cpu2.get_flag(SREG_Z) is False
 
 
 class TestImmediateArithmetic:
@@ -158,6 +202,7 @@ def test_sbci_instruction(self):
         """)
         cpu.load_program(asm)
         cpu.run()
+        assert cpu.read_reg(16) == 15
 
     def test_sbc_instruction(self):
         """Test subtract with carry."""
@@ -169,6 +214,7 @@ def test_sbc_instruction(self):
         """)
         cpu.load_program(asm)
         cpu.run()
+        assert cpu.read_reg(16) == 5
 
 
 class TestSkipInstructions:
@@ -375,18 +421,6 @@ def test_sei_cli_instructions(self):
 class TestArithmeticEdgeCases:
     """Test arithmetic edge cases."""
 
-    def test_div_by_zero(self):
-        """Test division by zero."""
-        cpu = CPU()
-        asm = assemble("""
-            ldi r16, 10
-            ldi r17, 0
-            div r16, r17
-        """)
-        cpu.load_program(asm)
-        cpu.run()
-        # Division by zero sets result to 0xFF and 0
-
     def test_mul_overflow(self):
         """Test multiplication overflow."""
         cpu = CPU()
@@ -397,4 +431,6 @@ def test_mul_overflow(self):
         """)
         cpu.load_program(asm)
         cpu.run()
-        # Result is 16-bit in r0:r1
+        # 255 * 2 = 510 = 0x01FE -> r0=0xFE, r1=0x01
+        assert cpu.read_reg(0) == 0xFE
+        assert cpu.read_reg(1) == 0x01
diff --git a/tests/test_cpu_edge_cases.py b/tests/test_cpu_edge_cases.py
index a3496ae..8937a07 100644
--- a/tests/test_cpu_edge_cases.py
+++ b/tests/test_cpu_edge_cases.py
@@ -20,17 +20,15 @@ def test_invalid_instruction(self):
         ):
             cpu.step()
 
-    def test_operand_formatting_exception(self):
-        """Test that operand formatting exceptions are handled."""
+    def test_operand_formatting_none_operand(self):
+        """Test formatting instruction when operand list contains None."""
         cpu = CPU()
-        cpu.program = [("LDI", (None,))]
-        try:
-            cpu.step()
-        except Exception:
-            pass
+        cpu.program = [("NOP", ())]
+        cpu._build_predecoded()
+        assert cpu._predecoded[0][2] == "NOP"
 
     def test_operand_formatting_with_exception(self):
-        """Test operand formatting exception handling in step function."""
+        """Test operand formatting fallback when operand str() raises an exception."""
         cpu = CPU()
 
         class BadOperand:
@@ -41,11 +39,9 @@ def __repr__(self):
                 raise ValueError("Cannot format")
 
         cpu.program = [("LDI", (("reg", 16), BadOperand()))]
-        cpu.pc = 0
-        try:
-            cpu.step()
-        except Exception:
-            pass
+        cpu._build_predecoded()
+        # Fallback catches the exception and falls back to base instruction mnemonic
+        assert cpu._predecoded[0][2] == "LDI"
 
     def test_jmp_with_invalid_label(self):
         """Test JMP with invalid label raises KeyError."""
@@ -157,6 +153,8 @@ class TestCPUFlagOperations:
 
     def test_set_flags_logical_negative(self):
         """Test _set_flags_logical with negative result."""
+        from tiny8.cpu import SREG_N, SREG_S, SREG_V, SREG_Z
+
         cpu = CPU()
         asm = assemble("""
             ldi r16, 0x80
@@ -165,10 +163,16 @@ def test_set_flags_logical_negative(self):
         """)
         cpu.load_program(asm)
         cpu.run()
-        # Result should be 0x80 which has bit 7 set (negative)
+        assert cpu.read_reg(16) == 0x80
+        assert cpu.get_flag(SREG_N) is True
+        assert cpu.get_flag(SREG_Z) is False
+        assert cpu.get_flag(SREG_V) is False
+        assert cpu.get_flag(SREG_S) is True
 
     def test_set_flags_logical_zero(self):
         """Test _set_flags_logical with zero result."""
+        from tiny8.cpu import SREG_N, SREG_S, SREG_V, SREG_Z
+
         cpu = CPU()
         asm = assemble("""
             ldi r16, 0xFF
@@ -177,10 +181,14 @@ def test_set_flags_logical_zero(self):
         """)
         cpu.load_program(asm)
         cpu.run()
-        # Result should be 0
+        assert cpu.read_reg(16) == 0x00
+        assert cpu.get_flag(SREG_Z) is True
+        assert cpu.get_flag(SREG_N) is False
+        assert cpu.get_flag(SREG_V) is False
+        assert cpu.get_flag(SREG_S) is False
 
     def test_mul_result_storage(self):
-        """Test MUL stores result in rd:rd+1."""
+        """Test MUL stores result in R1:R0 per AVR DS40002198A."""
         cpu = CPU()
         asm = assemble("""
             ldi r16, 10
@@ -189,20 +197,205 @@ def test_mul_result_storage(self):
         """)
         cpu.load_program(asm)
         cpu.run()
-        # Result 200 = 0x00C8, so r16=200, r17=0
-        assert cpu.read_reg(16) == 200  # low byte
-        assert cpu.read_reg(17) == 0  # high byte
+        # Result 200 = 0x00C8, so r0=200, r1=0
+        assert cpu.read_reg(0) == 200  # low byte in R0
+        assert cpu.read_reg(1) == 0  # high byte in R1
+
+
+class TestSREGCompliance:
+    """Comprehensive tests for AVR DS40002198A Status Register (SREG) compliance."""
+
+    def test_sreg_bit_positions(self):
+        """Verify exact SREG bit indices: I=7, T=6, H=5, S=4, V=3, N=2, Z=1, C=0."""
+        from tiny8.cpu import (
+            SREG_C,
+            SREG_H,
+            SREG_I,
+            SREG_N,
+            SREG_S,
+            SREG_T,
+            SREG_V,
+            SREG_Z,
+        )
+
+        cpu = CPU()
+        flags = [
+            (SREG_C, 0, 0x01),
+            (SREG_Z, 1, 0x02),
+            (SREG_N, 2, 0x04),
+            (SREG_V, 3, 0x08),
+            (SREG_S, 4, 0x10),
+            (SREG_H, 5, 0x20),
+            (SREG_T, 6, 0x40),
+            (SREG_I, 7, 0x80),
+        ]
+        for flag_const, bit_idx, bit_mask in flags:
+            assert flag_const == bit_idx
+            cpu.sreg = 0
+            cpu.set_flag(flag_const, True)
+            assert cpu.sreg == bit_mask
+            assert cpu.get_flag(flag_const) is True
+            cpu.set_flag(flag_const, False)
+            assert cpu.sreg == 0
+            assert cpu.get_flag(flag_const) is False
+
+    def test_sreg_flags_add_half_carry_and_overflow(self):
+        """Test ADD calculates H, V, S, N, Z, C and preserves I, T."""
+        from tiny8.cpu import (
+            SREG_C,
+            SREG_H,
+            SREG_I,
+            SREG_N,
+            SREG_S,
+            SREG_T,
+            SREG_V,
+            SREG_Z,
+        )
+
+        cpu = CPU()
+        cpu.set_flag(SREG_I, True)
+        cpu.set_flag(SREG_T, True)
+        # 0x0F + 0x01 = 0x10 (Half Carry set, no overflow, no carry, not zero)
+        cpu._set_flags_add(0x0F, 0x01, 0, 0x10)
+        assert cpu.get_flag(SREG_I) is True
+        assert cpu.get_flag(SREG_T) is True
+        assert cpu.get_flag(SREG_H) is True
+        assert cpu.get_flag(SREG_C) is False
+        assert cpu.get_flag(SREG_Z) is False
+        assert cpu.get_flag(SREG_N) is False
+        assert cpu.get_flag(SREG_V) is False
+        assert cpu.get_flag(SREG_S) is False
+
+        # Signed overflow: 127 + 1 = 128 (0x7F + 0x01 = 0x80)
+        # Pos + Pos = Neg -> V=1, N=1, S = N ^ V = 0
+        cpu._set_flags_add(0x7F, 0x01, 0, 0x80)
+        assert cpu.get_flag(SREG_V) is True
+        assert cpu.get_flag(SREG_N) is True
+        assert cpu.get_flag(SREG_S) is False
+        assert cpu.get_flag(SREG_H) is True
+        assert cpu.get_flag(SREG_C) is False
+
+    def test_sreg_flags_sub_half_borrow_and_overflow(self):
+        """Test SUB calculates H, V, S, N, Z, C and preserves I, T."""
+        from tiny8.cpu import (
+            SREG_C,
+            SREG_H,
+            SREG_N,
+            SREG_S,
+            SREG_V,
+            SREG_Z,
+        )
+
+        cpu = CPU()
+        # 0x10 - 0x01 = 0x0F (Half borrow: (0 - 1) < 0 -> H=1, no unsigned borrow -> C=0)
+        cpu._set_flags_sub(0x10, 0x01, 0, 0x0F)
+        assert cpu.get_flag(SREG_H) is True
+        assert cpu.get_flag(SREG_C) is False
+        assert cpu.get_flag(SREG_Z) is False
+        assert cpu.get_flag(SREG_N) is False
+        assert cpu.get_flag(SREG_V) is False
+        assert cpu.get_flag(SREG_S) is False
+
+        # Signed underflow: -128 - 1 = +127 (0x80 - 0x01 = 0x7F)
+        # Neg - Pos = Pos -> V=1, N=0, S = N ^ V = 1
+        cpu._set_flags_sub(0x80, 0x01, 0, 0x7F)
+        assert cpu.get_flag(SREG_V) is True
+        assert cpu.get_flag(SREG_N) is False
+        assert cpu.get_flag(SREG_S) is True
+        assert cpu.get_flag(SREG_C) is False
+
+    def test_sreg_logical_preserves_c_h_t_i(self):
+        """Test logical ops (AND, OR, EOR) clear V, set S=N, and preserve C, H, T, I."""
+        from tiny8.cpu import (
+            SREG_C,
+            SREG_H,
+            SREG_I,
+            SREG_N,
+            SREG_S,
+            SREG_T,
+            SREG_V,
+            SREG_Z,
+        )
 
-    def test_div_quotient_remainder(self):
-        """Test DIV stores quotient and remainder correctly."""
         cpu = CPU()
+        cpu.set_flag(SREG_C, True)
+        cpu.set_flag(SREG_H, True)
+        cpu.set_flag(SREG_T, True)
+        cpu.set_flag(SREG_I, True)
+        cpu.set_flag(SREG_V, True)
+
+        # Result is 0x80 (Negative, non-zero)
+        cpu._set_flags_logical(0x80)
+        assert cpu.get_flag(SREG_C) is True  # Preserved
+        assert cpu.get_flag(SREG_H) is True  # Preserved
+        assert cpu.get_flag(SREG_T) is True  # Preserved
+        assert cpu.get_flag(SREG_I) is True  # Preserved
+        assert cpu.get_flag(SREG_V) is False  # Cleared
+        assert cpu.get_flag(SREG_N) is True  # Set
+        assert cpu.get_flag(SREG_S) is True  # S = N ^ V = 1 ^ 0 = 1
+        assert cpu.get_flag(SREG_Z) is False  # Non-zero
+
+    def test_sreg_inc_dec_preserves_c_h_t_i(self):
+        """Test INC and DEC preserve C, H, T, I while updating S, V, N, Z."""
+        from tiny8.cpu import (
+            SREG_C,
+            SREG_H,
+            SREG_I,
+            SREG_N,
+            SREG_S,
+            SREG_T,
+            SREG_V,
+            SREG_Z,
+        )
+
+        cpu = CPU()
+        cpu.set_flag(SREG_C, True)
+        cpu.set_flag(SREG_H, True)
+        cpu.set_flag(SREG_T, True)
+        cpu.set_flag(SREG_I, True)
+
+        # INC from 0x7F to 0x80 -> Signed overflow V=1, N=1, S=0
+        cpu._set_flags_inc(0x7F, 0x80)
+        assert cpu.get_flag(SREG_C) is True  # Preserved
+        assert cpu.get_flag(SREG_H) is True  # Preserved
+        assert cpu.get_flag(SREG_T) is True  # Preserved
+        assert cpu.get_flag(SREG_I) is True  # Preserved
+        assert cpu.get_flag(SREG_V) is True
+        assert cpu.get_flag(SREG_N) is True
+        assert cpu.get_flag(SREG_S) is False
+        assert cpu.get_flag(SREG_Z) is False
+
+        # DEC from 0x80 to 0x7F -> Signed overflow V=1, N=0, S=1
+        cpu._set_flags_dec(0x80, 0x7F)
+        assert cpu.get_flag(SREG_C) is True  # Preserved
+        assert cpu.get_flag(SREG_H) is True  # Preserved
+        assert cpu.get_flag(SREG_V) is True
+        assert cpu.get_flag(SREG_N) is False
+        assert cpu.get_flag(SREG_S) is True
+        assert cpu.get_flag(SREG_Z) is False
+
+    def test_cpu_fast_path_run_and_invoker(self):
+        """Test CPU fast-path execution loop without progress or tracing."""
+        from tiny8.cpu import _make_invoker
+
+        cpu = CPU()
+        cpu.trace_enabled = False
         asm = assemble("""
-            ldi r16, 17
-            ldi r17, 5
-            div r16, r17
+            ldi r16, 1
+            ldi r17, 2
+            add r16, r17
         """)
         cpu.load_program(asm)
-        cpu.run()
-        # 17 / 5 = 3 remainder 2
-        assert cpu.read_reg(16) == 3  # quotient
-        assert cpu.read_reg(17) == 2  # remainder
+        cpu.run(show_progress=False)
+        assert cpu.read_reg(16) == 3
+
+        # Test _make_invoker with 3+ operands fallback
+        called_args = []
+
+        def dummy_handler(a, b, c):
+            called_args.extend([a, b, c])
+
+        inv_n = _make_invoker(dummy_handler, (1, 2, 3))
+        assert inv_n is not None
+        inv_n()
+        assert called_args == [1, 2, 3]
diff --git a/tests/test_data_transfer.py b/tests/test_data_transfer.py
index 4f745cb..680c27c 100644
--- a/tests/test_data_transfer.py
+++ b/tests/test_data_transfer.py
@@ -94,11 +94,11 @@ def test_st_multiple_addresses(self, cpu_with_program, helper):
             ldi r20, 100
             ldi r21, 11
             st r20, r21
-            
+
             ldi r20, 101
             ldi r21, 22
             st r20, r21
-            
+
             ldi r20, 102
             ldi r21, 33
             st r20, r21
@@ -248,7 +248,7 @@ def test_copy_memory_block(self, cpu_with_program, helper):
             inc r0
             ldi r1, 33
             st r0, r1
-            
+
             ; Copy to destination [200-202]
             ldi r2, 100
             ldi r3, 200
@@ -279,3 +279,30 @@ def test_swap_registers_via_stack(self, cpu_with_program, helper):
             pop r17
         """)
         helper.assert_registers(cpu, {16: 99, 17: 42})
+
+
+class TestLDSSTS:
+    """Test LDS (Load Direct from SRAM) and STS (Store Direct to SRAM)."""
+
+    def test_lds_sts_basic(self, cpu_with_program, helper):
+        """Test direct 16-bit address load and store."""
+        cpu = cpu_with_program("""
+            ldi r16, 0x42
+            sts 0x0250, r16
+            lds r17, 0x0250
+        """)
+        helper.assert_register(cpu, 17, 0x42)
+        helper.assert_memory(cpu, 0x0250, 0x42)
+
+    def test_16bit_pointer_pair(self, cpu_with_program, helper):
+        """Test 16-bit pointer pairs (Z=R31:R30) with LD and ST."""
+        cpu = cpu_with_program("""
+            ldi r30, 0x10
+            ldi r31, 0x02
+            ldi r16, 99
+            st r30, r16
+            ldi r17, 0
+            ld r17, r30
+        """)
+        helper.assert_register(cpu, 17, 99)
+        helper.assert_memory(cpu, 0x0210, 99)
diff --git a/tests/test_examples.py b/tests/test_examples.py
new file mode 100644
index 0000000..b5f01a9
--- /dev/null
+++ b/tests/test_examples.py
@@ -0,0 +1,168 @@
+"""Tests for all example programs in examples/ directory."""
+
+from pathlib import Path
+
+from tiny8 import CPU, assemble, assemble_file, compile_c_file
+
+EXAMPLES_DIR = Path(__file__).parent.parent / "examples"
+
+
+def test_example_array_sum():
+    """Verify examples/array_sum.asm computes sum 180 in R16."""
+    cpu = CPU()
+    cpu.load_program(assemble_file(str(EXAMPLES_DIR / "array_sum.asm")))
+    cpu.run(max_steps=1000)
+    assert cpu.read_reg(16) == 180
+
+
+def test_example_bubblesort():
+    """Verify examples/bubblesort.asm sorts 32 elements in ascending order."""
+    cpu = CPU()
+    cpu.load_program(assemble_file(str(EXAMPLES_DIR / "bubblesort.asm")))
+    cpu.run(max_steps=50000, show_progress=False)
+    arr = [cpu.read_ram(0x60 + i) for i in range(32)]
+    assert arr == sorted(arr)
+    assert arr[0] <= arr[-1]
+    assert len(set(arr)) > 15  # Rich distribution of pseudo-random values
+
+
+def test_example_count_bits():
+    """Verify examples/count_bits.asm counts 5 set bits in 181."""
+    cpu = CPU()
+    cpu.load_program(assemble_file(str(EXAMPLES_DIR / "count_bits.asm")))
+    cpu.run(max_steps=1000)
+    assert cpu.read_reg(16) == 5
+
+
+def test_example_factorial_asm():
+    """Verify examples/factorial.asm computes 5! = 120 in R16."""
+    cpu = CPU()
+    cpu.load_program(assemble_file(str(EXAMPLES_DIR / "factorial.asm")))
+    cpu.run(max_steps=1000)
+    assert cpu.read_reg(16) == 120
+
+
+def test_example_factorial_c():
+    """Verify examples/factorial.c compiles and computes 5! = 120 in RAM[0x80]."""
+    asm_code = compile_c_file(str(EXAMPLES_DIR / "factorial.c"))
+    cpu = CPU()
+    cpu.load_program(assemble(asm_code))
+    cpu.run(max_steps=5000)
+    assert cpu.read_ram(0x80) == 120
+
+
+def test_example_fibonacci():
+    """Verify examples/fibonacci.asm computes 10th Fibonacci number 55 in R17."""
+    cpu = CPU()
+    cpu.load_program(assemble_file(str(EXAMPLES_DIR / "fibonacci.asm")))
+    cpu.run(max_steps=1000)
+    assert cpu.read_reg(17) == 55
+
+
+def test_example_find_max():
+    """Verify examples/find_max.asm finds maximum value 89 at index 3."""
+    cpu = CPU()
+    cpu.load_program(assemble_file(str(EXAMPLES_DIR / "find_max.asm")))
+    cpu.run(max_steps=1000)
+    assert cpu.read_reg(16) == 89
+    assert cpu.read_reg(17) == 3
+
+
+def test_example_gcd():
+    """Verify examples/gcd.asm computes gcd(48, 18) = 6 in R16."""
+    cpu = CPU()
+    cpu.load_program(assemble_file(str(EXAMPLES_DIR / "gcd.asm")))
+    cpu.run(max_steps=1000)
+    assert cpu.read_reg(16) == 6
+
+
+def test_example_hello_world():
+    """Verify examples/hello_world.asm writes ASCII 'HELLO' to RAM[0x60..0x64]."""
+    cpu = CPU()
+    cpu.load_program(assemble_file(str(EXAMPLES_DIR / "hello_world.asm")))
+    cpu.run(max_steps=1000)
+    chars = bytes([cpu.read_ram(0x60 + i) for i in range(5)])
+    assert chars == b"HELLO"
+
+
+def test_example_is_prime():
+    """Verify examples/is_prime.asm identifies 17 as prime (R16 = 1)."""
+    cpu = CPU()
+    cpu.load_program(assemble_file(str(EXAMPLES_DIR / "is_prime.asm")))
+    cpu.run(max_steps=1000)
+    assert cpu.read_reg(16) == 1
+
+
+def test_example_linear_search():
+    """Verify examples/linear_search.asm finds target value 56 at index 5."""
+    cpu = CPU()
+    cpu.load_program(assemble_file(str(EXAMPLES_DIR / "linear_search.asm")))
+    cpu.run(max_steps=1000)
+    assert cpu.read_reg(16) == 5
+
+
+def test_example_memory_copy():
+    """Verify examples/memory_copy.asm copies 6 bytes to RAM[0x70..0x75]."""
+    cpu = CPU()
+    cpu.load_program(assemble_file(str(EXAMPLES_DIR / "memory_copy.asm")))
+    cpu.run(max_steps=1000)
+    assert [cpu.read_ram(0x70 + i) for i in range(6)] == [10, 20, 30, 40, 50, 60]
+
+
+def test_example_multiply_by_shift():
+    """Verify examples/multiply_by_shift.asm computes 7 * 8 = 56 in R16 using shifts."""
+    cpu = CPU()
+    cpu.load_program(assemble_file(str(EXAMPLES_DIR / "multiply_by_shift.asm")))
+    cpu.run(max_steps=1000)
+    assert cpu.read_reg(16) == 56
+
+
+def test_example_power():
+    """Verify examples/power.asm computes 3^4 = 81 in R16."""
+    cpu = CPU()
+    cpu.load_program(assemble_file(str(EXAMPLES_DIR / "power.asm")))
+    cpu.run(max_steps=1000)
+    assert cpu.read_reg(16) == 81
+
+
+def test_example_reverse():
+    """Verify examples/reverse.asm reverses array in RAM[0x60..0x65]."""
+    cpu = CPU()
+    cpu.load_program(assemble_file(str(EXAMPLES_DIR / "reverse.asm")))
+    cpu.run(max_steps=1000)
+    assert [cpu.read_ram(0x60 + i) for i in range(6)] == [60, 50, 40, 30, 20, 10]
+
+
+def test_example_sum_1_to_n():
+    """Verify examples/sum_1_to_n.asm computes sum of 1..20 = 210 in R16."""
+    cpu = CPU()
+    cpu.load_program(assemble_file(str(EXAMPLES_DIR / "sum_1_to_n.asm")))
+    cpu.run(max_steps=1000)
+    assert cpu.read_reg(16) == 210
+
+
+def test_example_diffusion_mnist8_asm():
+    """Verify examples/diffusion_mnist8.asm assembles and executes reverse diffusion on Tiny8."""
+    asm_file = str(EXAMPLES_DIR / "diffusion_mnist8.asm")
+    asm = assemble_file(asm_file)
+    assert len(asm.program) > 1000
+
+    cpu = CPU()
+    cpu.load_program(asm)
+
+    # Initial noise rendering at step 8 (~70,000 instructions for 28x28 data init)
+    cpu.run(max_steps=70000, show_progress=False)
+    header_step8 = "".join(chr(cpu.read_ram(0x0200 + i)) for i in range(32))
+    assert "DIFFUSION MNIST:8" in header_step8
+    assert "STEP:[8]" in header_step8
+
+    # First denoising reverse step transition to step 7 (~180,000 additional instructions)
+    cpu.run(max_steps=180000, show_progress=False)
+    header_step7 = "".join(chr(cpu.read_ram(0x0200 + i)) for i in range(32))
+    assert "STEP:[7]" in header_step7
+
+    # Verify non-zero heatmap pixels rendered in 28x28 VRAM region
+    pixels = [
+        cpu.read_ram(0x0200 + r * 32 + c) for r in range(2, 30) for c in range(2, 30)
+    ]
+    assert any(p > 0 for p in pixels)
diff --git a/tests/test_memory.py b/tests/test_memory.py
index fffc4fb..2497d93 100644
--- a/tests/test_memory.py
+++ b/tests/test_memory.py
@@ -3,9 +3,13 @@
 Tests for RAM, ROM operations, memory snapshots, and edge cases.
 """
 
+from pathlib import Path
+
 import pytest
 
+from tiny8 import CPU, assemble, compile_c_file_with_symbols
 from tiny8.memory import Memory
+from tiny8.tui import Tiny8App
 
 
 class TestMemoryBasicOperations:
@@ -97,3 +101,110 @@ def test_snapshot_rom(self):
         assert len(snapshot) == 10
         snapshot[0] = 99
         assert mem.read_rom(0) == 1
+
+    def test_restore_ram_and_untracked_rom(self):
+        """Test restore_ram and load_rom when track_changes is False."""
+        mem = Memory(ram_size=20, rom_size=20, track_changes=False)
+        mem.load_rom([10, 20, 30])
+        assert mem.read_rom(0) == 10
+        assert mem.read_rom(1) == 20
+        assert len(mem.rom_changes) == 0
+
+        # Write initial non-zero
+        mem.write_ram(3, 100)
+        assert mem.read_ram(3) == 100
+
+        # Restore from dict with different keys and in-range values
+        mem.restore_ram({5: 250, 7: 15})
+        assert mem.read_ram(3) == 0
+        assert mem.read_ram(5) == 250
+        assert mem.read_ram(7) == 15
+
+
+class TestMemoryOptimizationAndTraceBounds:
+    """Test memory optimization, bounded trace history, and trace lifecycle."""
+
+    def test_cpu_trace_bounded_during_long_run(self):
+        """Verify that step_trace, reg_trace, and mem_trace do not grow unboundedly."""
+        asm_src = """
+        loop:
+            ldi r16, 1
+            ldi r17, 2
+            add r16, r17
+            rjmp loop
+        """
+        asm = assemble(asm_src)
+        cpu = CPU(max_trace_steps=50, max_trace_history=100)
+        cpu.load_program(asm)
+        cpu.run(max_steps=5000, show_progress=False)
+
+        assert cpu.step_count == 5000
+        assert len(cpu.step_trace) <= 50
+        assert len(cpu.reg_trace) <= 100
+        assert len(cpu.mem_trace) <= 100
+        assert len(cpu.mem.ram_changes) <= cpu.mem.max_changes
+
+    def test_cpu_tracing_disabled_skips_trace_allocations(self):
+        """Verify that disabling tracing produces no trace entries."""
+        asm_src = """
+        loop:
+            ldi r16, 42
+            sts 0x0100, r16
+            rjmp loop
+        """
+        asm = assemble(asm_src)
+        cpu = CPU()
+        cpu.load_program(asm)
+        cpu.trace_enabled = False
+        cpu.mem.track_changes = False
+
+        for _ in range(500):
+            cpu.step(record_trace=False)
+
+        assert cpu.step_count == 500
+        assert len(cpu.step_trace) == 0
+        assert len(cpu.reg_trace) == 0
+        assert len(cpu.mem_trace) == 0
+        assert len(cpu.mem.ram_changes) == 0
+
+    def test_simulation_memory_bounded(self):
+        """Simulate execution and verify memory and traces remain strictly bounded."""
+        factorial_c = Path(__file__).parent.parent / "examples" / "factorial.c"
+        asm_code, symbols = compile_c_file_with_symbols(str(factorial_c))
+        asm = assemble(asm_code)
+
+        cpu = CPU()
+        cpu.load_program(asm)
+        cpu.source_lines = factorial_c.read_text(encoding="utf-8").splitlines()
+        cpu.pc_to_line = asm.pc_to_line
+        cpu.run(max_steps=1000, show_progress=False)
+
+        app = Tiny8App(
+            cpu=cpu, file_path=str(factorial_c), max_steps=1000, var_symbols=symbols
+        )
+
+        for _ in range(20):
+            cpu.run(max_steps=3000, show_progress=False)
+
+        assert len(app.traces) <= 1000
+        assert len(cpu.step_trace) <= cpu.max_trace_steps
+        assert len(cpu.reg_trace) <= cpu.max_trace_history
+        assert len(cpu.mem_trace) <= cpu.max_trace_history
+
+    def test_clear_traces(self):
+        """Verify clear_traces empties all trace lists and change logs."""
+        cpu = CPU()
+        cpu.write_reg(16, 42)
+        cpu.write_ram(0x50, 99)
+        cpu.step_trace.append({"step": 1})
+
+        assert len(cpu.reg_trace) > 0
+        assert len(cpu.mem_trace) > 0
+        assert len(cpu.mem.ram_changes) > 0
+        assert len(cpu.step_trace) > 0
+
+        cpu.clear_traces()
+        assert len(cpu.reg_trace) == 0
+        assert len(cpu.mem_trace) == 0
+        assert len(cpu.mem.ram_changes) == 0
+        assert len(cpu.step_trace) == 0
diff --git a/tests/test_tui.py b/tests/test_tui.py
new file mode 100644
index 0000000..52683bc
--- /dev/null
+++ b/tests/test_tui.py
@@ -0,0 +1,1034 @@
+"""Tests for modern Textual CLI and widgets."""
+
+import asyncio
+
+import pytest
+from textual.widgets import Input
+
+from tiny8 import CPU, assemble
+from tiny8.tui import (
+    BtopRegistersWidget,
+    CacheProgressModalScreen,
+    CallStackWidget,
+    CheckpointManager,
+    CodeViewWidget,
+    CVariablesWidget,
+    InstructionDetailModalScreen,
+    InstructionDetailWidget,
+    LazyStatusWidget,
+    MemoryMatrixWidget,
+    MemoryWidget,
+    RegistersWidget,
+    SregWidget,
+    StackWidget,
+    TelemetryWidget,
+    Tiny8App,
+    TUIHelpScreen,
+    VimEditorScreen,
+    VimTextArea,
+    eval_condition,
+    extract_call_frames,
+    run_cli,
+)
+
+
+def create_tested_cpu() -> CPU:
+    asm_src = """
+    LDI R16, 42
+    PUSH R16
+    MOV R0, R16
+    INC R16
+    """
+    asm = assemble(asm_src)
+    cpu = CPU()
+    cpu.load_program(asm)
+    cpu.run(max_steps=10, show_progress=False)
+    return cpu
+
+
+def test_sreg_widget_rendering():
+    widget = SregWidget()
+    widget.sreg = 0b00000001
+    rendered = widget.render().plain
+    assert "C" in rendered
+    assert "0x01" in rendered
+
+
+def test_btop_registers_widget_rendering():
+    widget = BtopRegistersWidget()
+    widget.regs = [0] * 32
+    widget.regs[0] = 5
+    widget.regs[16] = 42
+    widget.regs[31] = 255
+    widget.prev_regs = [0] * 32
+    widget.prev_regs[16] = 10
+    rendered = widget.render().plain
+    assert "REGISTERS (R00..R31)" in rendered
+    assert "R00" in rendered
+    assert "R15" in rendered
+    assert "R16" in rendered
+    assert "R31" in rendered
+    assert "0x2A" in rendered
+    assert "0xFF" in rendered
+
+
+def test_registers_widget_rendering():
+    widget = RegistersWidget()
+    widget.regs = [0] * 32
+    widget.regs[16] = 42
+    rendered = widget.render().plain
+    assert "REGISTERS" in rendered
+    assert "R16:2A" in rendered
+
+
+def test_memory_widget_rendering():
+    widget = MemoryWidget()
+    widget.start_addr = 0x60
+    widget.mem = {0x60: 65, 0x61: 66}
+    rendered = widget.render().plain
+    assert "MEMORY DUMP" in rendered
+    assert "j/k: scroll" in rendered
+    assert "0x0060:" in rendered
+    assert "4142" in rendered
+
+
+def test_memory_widget_grayscale_and_hex_toggles():
+    widget = MemoryWidget()
+    widget.start_addr = 0x60
+    widget.mem = {0x60: 255, 0x61: 0}
+
+    # Default Viridis + Hex
+    assert widget.color_mode == "viridis"
+    assert widget.show_hex is True
+    assert "FF.." in widget.render().plain
+
+    # Switch to Grayscale + Pixel
+    widget.color_mode = "grayscale"
+    widget.show_hex = False
+    assert widget.get_heatmap_bg(255, "grayscale") == "#FFFFFF"
+    assert widget.get_heatmap_bg(0, "grayscale") == "#000000"
+    rendered_pixel = widget.render().plain
+    assert "Grayscale" in rendered_pixel
+    assert "PIXEL" in rendered_pixel
+    assert "FF.." not in rendered_pixel
+
+
+def test_stack_widget_rendering():
+    widget = StackWidget()
+    widget.ram_size = 2048
+    widget.sp = 2046  # 1 entry pushed
+    widget.mem = {2047: 42}
+    rendered = widget.render().plain
+    assert "CALL STACK" in rendered
+    assert "0x07FE" in rendered
+    assert "42" in rendered
+
+
+def test_instruction_detail_widget_rendering():
+    widget = InstructionDetailWidget()
+    widget.current_instr = "ADD R16, R17"
+    widget.pc = 0x0005
+    widget.sp = 0x07FE
+    widget.source_line = 12
+    widget.source_text = "add r16, r17"
+    rendered = widget.render().plain
+    assert "INSTRUCTION INSPECTOR" in rendered
+    assert "ADD R16, R17" in rendered
+    assert "Add without Carry" in rendered
+    assert "0x0005" in rendered
+    assert "Line 13" in rendered
+
+
+def test_telemetry_widget_rendering():
+    widget = TelemetryWidget()
+    widget.total_steps = 10
+    widget.current_step = 5
+    widget.instr_counts = {"ADD": 3, "LDI": 2}
+    rendered = widget.render().plain
+    assert "EXECUTION TELEMETRY" in rendered
+    assert "5/10" in rendered
+    assert "ADD" in rendered
+
+
+def test_code_view_widget_rendering():
+    widget = CodeViewWidget()
+    widget.program = [("LDI", (("reg", 16), 10)), ("ADD", (("reg", 16), ("reg", 0)))]
+    widget.current_pc = 0
+    widget.breakpoints = {1}
+    rendered_text = widget.render()
+    rendered = rendered_text.plain
+    assert "PROGRAM EXECUTION" in rendered
+    assert "LDI" in rendered
+    assert "●" in rendered
+    # Non-current line (ADD) should be styled white (#FFFFFF)
+    spans = [
+        span
+        for span in rendered_text.spans
+        if str(span.style) == "#ffffff" or str(span.style) == "#FFFFFF"
+    ]
+    assert len(spans) > 0
+
+
+def test_lazy_status_widget_rendering():
+    widget = LazyStatusWidget()
+    widget.mode = "NORMAL"
+    widget.filename = "factorial.c"
+    widget.current_step = 5
+    widget.total_steps = 20
+    widget.current_pc = 0x000E
+    widget.current_sp = 0x07FE
+    widget.current_instr = "ADD R16, R17"
+    rendered = widget.render().plain
+    assert "NORMAL" in rendered
+    assert "factorial.c" in rendered
+    assert "Step: 5" in rendered
+    assert "0x000E" in rendered
+    assert "ADD R16, R17" in rendered
+    assert "h: help" in rendered
+
+
+def test_tiny8_app_navigation_and_features():
+    async def _test():
+        cpu = create_tested_cpu()
+        app = Tiny8App(cpu=cpu)
+        async with app.run_test() as pilot:
+            assert app.current_idx == 0
+
+            # Step forward
+            await pilot.press("n")
+            assert app.current_idx == 1
+
+            # Step backward
+            await pilot.press("p")
+            assert app.current_idx == 0
+
+            # Toggle breakpoint
+            await pilot.press("b")
+            assert len(app.breakpoints) == 1
+            await pilot.press("b")
+            assert len(app.breakpoints) == 0
+
+            # Set breakpoint at PC=2 and continue
+            app.breakpoints.add(2)
+            await pilot.press("c")
+            assert app.current_idx == 2
+
+            # Memory scroll
+            initial_mem = app.mem_start
+            await pilot.press("j")
+            assert app.mem_start == initial_mem + 32
+            await pilot.press("k")
+            assert app.mem_start == initial_mem
+            await pilot.press("J")
+            assert app.mem_start == initial_mem + 128
+            await pilot.press("K")
+            assert app.mem_start == initial_mem
+
+            # Toggle play/pause
+            await pilot.press("space")
+            assert app.playing is True
+            await pilot.press("space")
+            assert app.playing is False
+
+            # Reset
+            app.current_idx = 2
+            await pilot.press("r")
+            assert app.current_idx == 0
+
+            # Open reference modal with 'i'
+            await pilot.press("i")
+            assert len(app.screen_stack) == 2
+            await pilot.press("escape")
+            assert len(app.screen_stack) == 1
+
+            # Open reference modal with 'h'
+            await pilot.press("h")
+            assert len(app.screen_stack) == 2
+            await pilot.press("escape")
+            assert len(app.screen_stack) == 1
+
+            # Command bar open and cancel
+            await pilot.press("colon")
+            cmd_bar = app.query_one("#command-bar")
+            assert cmd_bar.styles.display == "block"
+            await pilot.press("escape")
+            assert cmd_bar.styles.display == "none"
+
+            # Command bar execution with ':'
+            await pilot.press(":")
+            assert cmd_bar.styles.display == "block"
+            inp = app.query_one("#cmd-input")
+            assert inp.has_focus
+            await pilot.press("g", "o", "t", "o", " ", "2")
+            await pilot.press("enter")
+            assert cmd_bar.styles.display == "none"
+            assert app.current_idx == 2
+
+            # Command bar breakpoint command
+            await pilot.press(":")
+            await pilot.press("b", " ", "1")
+            await pilot.press("enter")
+            assert 1 in app.breakpoints
+
+    asyncio.run(_test())
+
+
+def test_run_cli_empty_trace_raises():
+    cpu = CPU()
+    with pytest.raises(RuntimeError):
+        run_cli(cpu)
+
+
+def test_vim_editor_workflow(tmp_path):
+    from pathlib import Path
+
+    async def _test():
+        test_file = str(tmp_path / "prog.c")
+        app = Tiny8App(file_path=test_file, start_in_editor=True)
+        async with app.run_test() as pilot:
+            assert len(app.screen_stack) == 2
+            editor_screen = app.screen_stack[-1]
+            assert isinstance(editor_screen, VimEditorScreen)
+
+            editor = editor_screen.query_one("#vim-editor", VimTextArea)
+            assert editor.mode == "NORMAL"
+
+            # Press 'i' to enter INSERT mode
+            await pilot.press("i")
+            assert editor.mode == "INSERT"
+
+            # Press Escape to return to NORMAL mode
+            await pilot.press("escape")
+            assert editor.mode == "NORMAL"
+
+            # Write C program
+            editor.text = "int main() { return 77; }"
+            await pilot.pause()
+
+            # Execute :w command to save
+            editor_screen.handle_vim_command("w")
+            assert Path(test_file).exists()
+            assert "77" in Path(test_file).read_text(encoding="utf-8")
+
+            # Execute :run command to compile, execute, and switch to debugger
+            editor_screen.handle_vim_command("run")
+            await pilot.pause()
+            assert len(app.screen_stack) == 1
+            assert app.num_traces > 0
+            assert app.cpu.regs[16] == 77
+
+            # Press 'e' in debugger to reopen editor
+            await pilot.press("e")
+            assert len(app.screen_stack) == 2
+            editor_screen2 = app.screen_stack[-1]
+            assert isinstance(editor_screen2, VimEditorScreen)
+
+            # Exit editor with :q
+            editor_screen2.handle_vim_command("q")
+            await pilot.pause()
+            assert len(app.screen_stack) == 1
+
+    asyncio.run(_test())
+
+
+def test_eval_condition():
+    regs = [0] * 32
+    regs[0] = 5
+    regs[16] = 42
+    mem = {0x60: 100, 0x61: 0}
+
+    assert eval_condition("R0 == 5", regs, mem) is True
+    assert eval_condition("R0 != 5", regs, mem) is False
+    assert eval_condition("R16 > 40", regs, mem) is True
+    assert eval_condition("R16 < 40", regs, mem) is False
+    assert eval_condition("mem[0x60] == 100", regs, mem) is True
+    assert eval_condition("mem[0x60] >= 100", regs, mem) is True
+    assert eval_condition("mem[0x61] == 0", regs, mem) is True
+    assert eval_condition("R0", regs, mem) is True
+    assert eval_condition("R1", regs, mem) is False
+    assert eval_condition("invalid_expr", regs, mem) is False
+
+
+def test_extract_call_frames():
+    traces = [
+        {"instr": "LDI R16, 1", "pc": 0, "sp": 2047},
+        {"instr": "RCALL my_func", "pc": 1, "sp": 2047},
+        {"instr": "ADD R16, R16", "pc": 5, "sp": 2045},
+        {"instr": "RET", "pc": 6, "sp": 2045},
+    ]
+
+    frames_at_1 = extract_call_frames(traces, 1)
+    assert len(frames_at_1) == 1
+    assert frames_at_1[0]["func"] == "my_func"
+
+    frames_at_3 = extract_call_frames(traces, 3)
+    assert len(frames_at_3) == 0
+
+
+def test_c_variables_widget():
+    w = CVariablesWidget()
+    assert "(No C variable symbols loaded)" in w.render().plain
+
+    w.var_symbols = {
+        "x": {"addr": 0x60, "type": "int"},
+        "y": {"addr": 0x61, "type": "int"},
+    }
+    w.mem = {0x60: 42, 0x61: 0}
+    w.prev_mem = {0x60: 10, 0x61: 0}
+    rendered = w.render().plain
+    assert "C VARIABLES" in rendered
+    assert "x" in rendered
+    assert "0x0060" in rendered
+    assert "0x2A" in rendered
+    assert "UPDATED" in rendered
+    assert "ZERO" in rendered
+
+
+def test_call_stack_widget():
+    w = CallStackWidget()
+    w.current_pc = 0x0010
+    assert "main() at PC:0x0010" in w.render().plain
+
+    w.frames = [{"func": "calc", "pc": 0x0004, "sp": 0x07FE}]
+    rendered = w.render().plain
+    assert "calc()" in rendered
+    assert "PC:0x0004" in rendered
+
+
+def test_memory_matrix_widget():
+    w = MemoryMatrixWidget()
+    w.base_addr = 0x60
+    w.mem = {0x60: 10}
+    w.write_counts = {0x60: 2}
+    w.read_counts = {0x61: 1}
+    rendered = w.render().plain
+    assert "2D RAM ACCESS ACTIVITY MATRIX" in rendered
+    assert "0x0060:" in rendered
+
+
+def test_advanced_debugger_features():
+    cpu = create_tested_cpu()
+
+    async def _test():
+        app = Tiny8App(cpu=cpu)
+        async with app.run_test():
+            # 1. Conditional Breakpoint
+            app.on_input_submitted(
+                Input.Submitted(app.query_one("#cmd-input", Input), "b 3 if R16 == 43")
+            )
+            assert 3 in app.breakpoints
+            assert app.conditional_breakpoints.get(3) == "R16 == 43"
+
+            # 2. Watchpoints
+            app.on_input_submitted(
+                Input.Submitted(app.query_one("#cmd-input", Input), "watch R0")
+            )
+            assert "R0" in app.watchpoints
+
+            # 3. Bookmarks
+            app.on_input_submitted(
+                Input.Submitted(app.query_one("#cmd-input", Input), "mark loop_start")
+            )
+            assert "loop_start" in app.bookmarks
+
+            # Jump via bookmark
+            app.current_idx = 0
+            app.on_input_submitted(
+                Input.Submitted(app.query_one("#cmd-input", Input), "'loop_start")
+            )
+            assert app.current_idx == app.bookmarks["loop_start"]
+
+            # 4. State Rewriting (:set, :poke)
+            app.on_input_submitted(
+                Input.Submitted(app.query_one("#cmd-input", Input), "set R5 77")
+            )
+            assert app.traces[app.current_idx]["regs"][5] == 77
+
+            app.on_input_submitted(
+                Input.Submitted(app.query_one("#cmd-input", Input), "poke 0x70 99")
+            )
+            assert app.traces[app.current_idx]["mem"][0x70] == 99
+
+            # 5. REPL (:exec)
+            prev_traces_count = len(app.traces)
+            app.on_input_submitted(
+                Input.Submitted(app.query_one("#cmd-input", Input), "exec LDI R17, 88")
+            )
+            assert len(app.traces) == prev_traces_count + 1
+            assert app.traces[app.current_idx]["regs"][17] == 88
+
+            # 6. Reverse Continue (Shift+C / action_reverse_continue)
+            app.current_idx = len(app.traces) - 1
+            app.action_reverse_continue()
+            assert app.current_idx <= len(app.traces) - 2
+
+            # 7. Clear breakpoints (:bc)
+            app.on_input_submitted(
+                Input.Submitted(app.query_one("#cmd-input", Input), "bc")
+            )
+            assert len(app.breakpoints) == 0
+            assert len(app.conditional_breakpoints) == 0
+
+            # 8. Unwatch (:unwatch)
+            app.on_input_submitted(
+                Input.Submitted(app.query_one("#cmd-input", Input), "unwatch")
+            )
+            assert len(app.watchpoints) == 0
+
+            # 9. Grayscale & Hex Mode Toggles
+            assert app.color_mode == "viridis"
+            assert app.show_hex is True
+            app.action_toggle_grayscale()
+            assert app.color_mode == "grayscale"
+            app.action_toggle_hex()
+            assert app.show_hex is False
+            app.action_cycle_mode()
+            assert app.color_mode == "grayscale"
+            assert app.show_hex is True
+
+            # Via command bar
+            app.on_input_submitted(
+                Input.Submitted(app.query_one("#cmd-input", Input), "viridis")
+            )
+            assert app.color_mode == "viridis"
+            app.on_input_submitted(
+                Input.Submitted(app.query_one("#cmd-input", Input), "pixel")
+            )
+            assert app.show_hex is False
+
+    asyncio.run(_test())
+
+
+def test_help_and_instruction_detail_screens():
+    async def _test():
+        cpu = create_tested_cpu()
+        app = Tiny8App(cpu=cpu)
+        async with app.run_test() as pilot:
+            # Press 'h' -> should open TUIHelpScreen
+            await pilot.press("h")
+            assert isinstance(app.screen, TUIHelpScreen)
+            await pilot.press("escape")
+            assert not isinstance(app.screen, TUIHelpScreen)
+
+            # Press 'question_mark' -> should open TUIHelpScreen
+            await pilot.press("question_mark")
+            assert isinstance(app.screen, TUIHelpScreen)
+            await pilot.press("escape")
+            assert not isinstance(app.screen, TUIHelpScreen)
+
+            # Press 'i' -> should open InstructionDetailModalScreen for current instruction
+            await pilot.press("i")
+            assert isinstance(app.screen, InstructionDetailModalScreen)
+            # Check current instruction details
+            assert app.screen.instr != ""
+            assert "0x" in hex(app.screen.pc)
+            await pilot.press("escape")
+            assert not isinstance(app.screen, InstructionDetailModalScreen)
+
+    asyncio.run(_test())
+
+
+def test_vim_editor_quit_command():
+    async def _test():
+        cpu = create_tested_cpu()
+        app = Tiny8App(cpu=cpu)
+        async with app.run_test() as pilot:
+            # Open Vim editor with 'e'
+            await pilot.press("e")
+            assert isinstance(app.screen, VimEditorScreen)
+
+            # Type :q and submit
+            await pilot.press("colon")
+            await pilot.press("q")
+            await pilot.press("enter")
+
+            # Must return to debugger screen, and CLI app must NOT exit
+            assert not isinstance(app.screen, VimEditorScreen)
+            assert app.is_running is True
+
+    asyncio.run(_test())
+
+
+def test_statusline_step_count_exceeds_999():
+    """Verify statusline current_step accurately displays step numbers beyond 999."""
+
+    async def _test():
+        from tiny8.assembler import assemble
+        from tiny8.tui import LazyStatusWidget
+
+        # Infinite counter loop:
+        # loop: INC R16, RJMP loop
+        asm = assemble("loop:\n    INC R16\n    RJMP loop")
+        cpu = CPU()
+        cpu.load_program(asm)
+        # Execute 1500 steps so deque maxlen (1000) is exceeded
+        cpu.run(max_steps=1500, show_progress=False)
+        assert cpu.step_count == 1500
+
+        app = Tiny8App(cpu=cpu)
+        app.current_idx = app.num_traces - 1
+        async with app.run_test():
+            lazy_status = app.query_one("#lazy-status", LazyStatusWidget)
+            # Must reflect actual step count (1500), not ring buffer index 999
+            assert lazy_status.current_step == 1500
+            rendered = lazy_status.render().plain
+            assert "Step: 1500" in rendered
+            assert "h: help" in rendered
+
+    asyncio.run(_test())
+
+
+def test_playback_speed_and_adaptive_batching():
+    """Verify playback speed acceleration down to 30ms visual limit and automatic batch scaling."""
+
+    async def _test():
+        cpu = create_tested_cpu()
+        app = Tiny8App(cpu=cpu)
+        async with app.run_test() as pilot:
+            # Initial defaults
+            assert app.speed_ms == 100
+            assert app.playback_rate_idx == 0
+            assert app.batch_size == 1
+
+            # Press '+' repeatedly to accelerate visually down to 30ms:
+            # 100 -> 80 -> 60 -> 40 -> 30 (4 steps)
+            for _ in range(4):
+                await pilot.press("+")
+            assert app.speed_ms == 30
+            assert app.playback_rate_idx == 0
+            assert app.batch_size == 1
+
+            # Once at visual threshold (30ms), pressing '+' automatically transitions to batch processing:
+            # 1 -> 5 -> 20 -> 100
+            await pilot.press("+")
+            assert app.speed_ms == 30
+            assert app.playback_rate_idx == 1
+            assert app.batch_size == 5
+
+            await pilot.press("+")
+            assert app.playback_rate_idx == 2
+            assert app.batch_size == 20
+
+            # Press '-' -> batch decreases back to 5, then 1
+            await pilot.press("-")
+            assert app.playback_rate_idx == 1
+            assert app.batch_size == 5
+
+            await pilot.press("-")
+            assert app.playback_rate_idx == 0
+            assert app.batch_size == 1
+
+            # Press '-' again -> visual interval increases: 30 -> 50ms
+            await pilot.press("-")
+            assert app.speed_ms == 50
+
+            # Test command bar :speed 25
+            await pilot.press(":")
+            await pilot.press("s", "p", "e", "e", "d", " ", "2", "5")
+            await pilot.press("enter")
+            assert app.speed_ms == 25
+
+            # Test command bar :batch 10000
+            await pilot.press(":")
+            await pilot.press("b", "a", "t", "c", "h", " ", "1", "0", "0", "0", "0")
+            await pilot.press("enter")
+            assert app.batch_size == 10000
+
+            # Test command bar :turbo
+            await pilot.press(":")
+            await pilot.press("t", "u", "r", "b", "o")
+            await pilot.press("enter")
+            assert app.speed_ms == 30
+            assert app.batch_size == 50000
+
+            # Test command bar :normal
+            await pilot.press(":")
+            await pilot.press("n", "o", "r", "m", "a", "l")
+            await pilot.press("enter")
+            assert app.speed_ms == 100
+            assert app.batch_size == 1
+
+    asyncio.run(_test())
+
+
+def test_checkpoint_manager_snapshot_and_time_travel():
+    """Verify 100-step sparse snapshots, exact step restoration, and cache invalidation."""
+    asm_src = """
+    LDI R16, 0
+loop:
+    INC R16
+    CPI R16, 250
+    BRNE loop
+    """
+    asm = assemble(asm_src)
+    cpu = CPU()
+    cpu.load_program(asm)
+
+    mgr = CheckpointManager(cpu, interval=100)
+    assert 0 in mgr.checkpoint_steps
+
+    # Step through 250 instructions
+    for _ in range(250):
+        cpu.step()
+        mgr.record_if_interval(cpu.step_count)
+
+    assert 100 in mgr.checkpoint_steps
+    assert 200 in mgr.checkpoint_steps
+    assert len(mgr.checkpoint_steps) >= 3
+
+    # Restore step 150 (nearest checkpoint is 100, then advance 50 steps)
+    ok = mgr.restore_exact_step(150)
+    assert ok is True
+    assert cpu.step_count == 150
+
+    # Test cache invalidation on memory/register edit
+    mgr.invalidate_after(120)
+    assert 200 not in mgr.checkpoint_steps
+    assert 100 in mgr.checkpoint_steps
+    assert 0 in mgr.checkpoint_steps
+
+
+def test_checkpoint_manager_infinite_loop_detection():
+    """Verify detection of HALT spin-loops and cycle loops."""
+    # 1. HALT spin loop: RJMP 0 (jump to self)
+    asm_spin = assemble("loop: RJMP loop")
+    cpu_spin = CPU()
+    cpu_spin.load_program(asm_spin)
+    mgr_spin = CheckpointManager(cpu_spin)
+    assert mgr_spin.detect_loop() is True
+    assert "HALT" in mgr_spin.loop_reason
+
+    # 2. Cycle loop: NOP; NOP; RJMP -2
+    asm_cycle = assemble("loop: NOP\nNOP\nRJMP loop")
+    cpu_cycle = CPU()
+    cpu_cycle.load_program(asm_cycle)
+    mgr_cycle = CheckpointManager(cpu_cycle)
+    # Advance a few cycles
+    detected = False
+    for _ in range(30):
+        cpu_cycle.step()
+        if mgr_cycle.detect_loop(window_size=16):
+            detected = True
+            break
+    assert detected is True
+    assert "Cycle" in mgr_cycle.loop_reason
+
+
+def test_reverse_playback_and_mode_switching():
+    """Verify reverse playback toggle, mode switching, and precomputing."""
+
+    async def _test():
+        cpu = create_tested_cpu()
+        app = Tiny8App(cpu=cpu)
+        async with app.run_test() as pilot:
+            # Default execution mode is cache
+            assert app.execution_mode == "cache"
+
+            # Switch mode via command
+            await pilot.press(":")
+            await pilot.press("m", "o", "d", "e", " ", "l", "i", "v", "e")
+            await pilot.press("enter")
+            assert app.execution_mode == "live"
+
+            await pilot.press(":")
+            await pilot.press("c", "a", "c", "h", "e")
+            await pilot.press("enter")
+            assert app.execution_mode == "cache"
+
+            # Reverse playback toggle
+            assert app.playing is False
+            await pilot.press("shift+space")
+            assert app.playing is True
+            assert app.play_direction == -1
+            await pilot.press("shift+space")
+            assert app.playing is False
+
+            # Precompute command
+            await pilot.press(":")
+            await pilot.press(
+                "p", "r", "e", "c", "o", "m", "p", "u", "t", "e", " ", "5", "0"
+            )
+            await pilot.press("enter")
+            assert len(app.checkpoint_manager.checkpoint_steps) >= 1
+
+    asyncio.run(_test())
+
+
+def test_default_cache_mode_and_precompute_before_execution():
+    """Verify cache mode is default and cache data is created before execution starts."""
+    asm_src = """
+    LDI R16, 0
+loop:
+    INC R16
+    CPI R16, 250
+    BRNE loop
+    """
+    asm = assemble(asm_src)
+    cpu = CPU()
+    cpu.load_program(asm)
+
+    app = Tiny8App(cpu=cpu, max_steps=500, precompute_cache=True)
+    # Verify default mode is cache
+    assert app.execution_mode == "cache"
+
+    # Verify cache data was created before execution
+    assert 0 in app.checkpoint_manager.checkpoint_steps
+    assert 100 in app.checkpoint_manager.checkpoint_steps
+    assert 200 in app.checkpoint_manager.checkpoint_steps
+    assert len(app.checkpoint_manager.checkpoint_steps) >= 3
+
+    # Verify app started at step 0
+    assert app.current_idx == 0
+
+    async def _test():
+        async with app.run_test() as pilot:
+            await pilot.press(":")
+            await pilot.press("g", "o", "t", "o", " ", "2", "0", "0")
+            await pilot.press("enter")
+            assert app.current_idx == 200
+
+            # Seek to step 300 via cache restore
+            ok = app.checkpoint_manager.restore_exact_step(300)
+            assert ok is True
+            assert app.cpu.step_count == 300
+
+    asyncio.run(_test())
+
+
+def test_goto_large_step_via_cache_and_dynamic_extension():
+    """Verify :goto with large step jumps instantly via cache checkpoints and extends dynamically."""
+    asm_src = """
+    LDI R16, 0
+loop:
+    INC R16
+    CPI R16, 250
+    BRNE loop
+    LDI R16, 0
+    RJMP loop
+    """
+    asm = assemble(asm_src)
+    cpu = CPU()
+    cpu.load_program(asm)
+
+    # CheckpointManager with initial precompute of 5000 steps
+    mgr = CheckpointManager(cpu, interval=100)
+    mgr.precompute(max_steps=5000)
+    assert mgr.checkpoint_steps[-1] >= 5000
+
+    # 1. Direct restore within precomputed checkpoints
+    ok = mgr.restore_exact_step(4500)
+    assert ok is True
+    assert cpu.step_count == 4500
+
+    # 2. Dynamic extension beyond initial checkpoints (e.g. step 20000)
+    ok2 = mgr.restore_exact_step(20000)
+    assert ok2 is True
+    assert cpu.step_count == 20000
+    assert 20000 in mgr.checkpoint_steps
+
+
+def test_auto_step_infinite_loop_stops_playback_without_freezing():
+    """Verify that playing into a HALT spin loop automatically stops playback and updates ProfilerWidget safely."""
+    asm_src = """
+    LDI R16, 3
+loop:
+    DEC R16
+    BRNE loop
+halt_loop:
+    RJMP halt_loop
+    """
+    asm = assemble(asm_src)
+    cpu = CPU()
+    cpu.load_program(asm)
+
+    mgr = CheckpointManager(cpu, interval=10)
+    mgr.precompute(max_steps=500)
+
+    app = Tiny8App(cpu=cpu, checkpoint_manager=mgr, execution_mode="cache")
+    app.playback_rate_idx = 7  # x50,000
+    app.speed_ms = 30
+    app.playing = True
+    app.play_direction = 1
+
+    # Trigger _auto_step: it advances towards 50,000, hits halt_loop, and auto-stops
+    app._auto_step()
+
+    assert app.playing is False
+    assert mgr.infinite_loop_detected is True
+    assert "HALT spin loop" in mgr.loop_reason
+
+
+def test_cache_progress_modal_and_visual_precompute():
+    """Verify that CacheProgressModalScreen updates and Tiny8App with show_cache_progress precomputes on mount."""
+    modal = CacheProgressModalScreen(max_steps=1000)
+    assert modal.target_steps == 1000
+
+    asm_src = """
+    LDI R16, 0
+loop:
+    INC R16
+    CPI R16, 50
+    BRNE loop
+    """
+    asm = assemble(asm_src)
+    cpu = CPU()
+    cpu.load_program(asm)
+
+    app = Tiny8App(
+        cpu=cpu,
+        max_steps=200,
+        precompute_cache=True,
+        show_cache_progress=True,
+    )
+
+    async def _test():
+        async with app.run_test() as pilot:
+            # Wait for background precomputation worker to complete
+            for _ in range(50):
+                await pilot.pause(0.05)
+                if not isinstance(app.screen, CacheProgressModalScreen):
+                    break
+            # Checkpoints should be created
+            assert len(app.checkpoint_manager.checkpoint_steps) >= 2
+            assert app.current_idx == 0
+
+    asyncio.run(_test())
+
+
+def test_precompute_until_infinite_loop():
+    """Verify that precompute runs until an infinite loop is entered when max_steps is None."""
+    asm_src = """
+    LDI R16, 0
+loop:
+    INC R16
+    CPI R16, 120
+    BRNE loop
+halt_loop:
+    RJMP halt_loop
+    """
+    asm = assemble(asm_src)
+    cpu = CPU()
+    cpu.load_program(asm)
+
+    mgr = CheckpointManager(cpu, interval=50)
+    # With max_steps=None, precompute should run until halt_loop is reached
+    computed = mgr.precompute(max_steps=None)
+
+    assert mgr.infinite_loop_detected is True
+    assert "HALT spin loop" in mgr.loop_reason
+    assert computed > 200
+    assert mgr.checkpoint_steps[-1] == computed
+
+    # Verify CacheProgressModalScreen handles None max_steps gracefully
+    modal = CacheProgressModalScreen(max_steps=None)
+    assert modal.target_steps is None
+    modal.update_progress(150, None)
+
+
+def test_app_layout_and_tab_structure():
+    """Verify SREG placement in left panel, and removal of matrix, grid, and profiler tabs."""
+    asm_src = """
+    LDI R16, 0
+loop:
+    INC R16
+    CPI R16, 20
+    BRNE loop
+    """
+    asm = assemble(asm_src)
+    cpu = CPU()
+    cpu.load_program(asm)
+    app = Tiny8App(cpu=cpu, max_steps=100)
+
+    async def _test():
+        async with app.run_test():
+            # Verify SregWidget is inside left-panel above btop-regs-view
+            left_children = [
+                type(c).__name__ for c in app.query_one("#left-panel").children
+            ]
+            assert "SregWidget" in left_children
+            assert "BtopRegistersWidget" in left_children
+            sreg_idx = left_children.index("SregWidget")
+            btop_idx = left_children.index("BtopRegistersWidget")
+            assert sreg_idx < btop_idx
+
+            # Verify top-bar is removed
+            assert len(app.query("#top-bar")) == 0
+
+            # Verify removed tabs: no tab-matrix, tab-grid, or tab-profiler
+            assert len(app.query("#tab-matrix")) == 0
+            assert len(app.query("#tab-grid")) == 0
+            assert len(app.query("#tab-profiler")) == 0
+
+    asyncio.run(_test())
+
+
+def test_memory_widget_terminal_fitting():
+    """Verify MemoryWidget adapts rows to terminal lines."""
+    mem_w = MemoryWidget()
+    mem_w.start_addr = 0x0200
+    rendered_mem = mem_w.render().plain
+    assert "MEMORY DUMP" in rendered_mem
+    assert "HEATMAP" not in rendered_mem
+    assert "0x0200:" in rendered_mem
+
+
+def test_memory_widget_full_range_at_0xffff():
+    """Verify MemoryWidget renders up to 0xFFFF correctly without out-of-bounds rows."""
+    mem_w = MemoryWidget()
+    mem_w.start_addr = 0xFFE0
+    mem_w.mem = {0xFFFF: 0xAB, 0xFFE0: 0x12}
+    rendered = mem_w.render().plain
+    assert "0xFFE0:" in rendered
+    assert "12" in rendered
+    assert "AB" in rendered
+    assert "0x10000:" not in rendered
+
+
+def test_tui_memory_navigation_full_range():
+    """Verify TUI can scroll and jump across full 0x0000..0xFFFF address space."""
+
+    async def _test():
+        cpu = CPU()
+        asm = assemble("NOP\nNOP\n")
+        cpu.load_program(asm)
+        cpu.step(record_trace=True)
+
+        app = Tiny8App(cpu=cpu, file_path="main.asm", precompute_cache=False)
+        async with app.run_test(size=(120, 36)):
+            inp = app.query_one("#cmd-input", Input)
+
+            # Jump to end of RAM via command
+            app.on_input_submitted(Input.Submitted(inp, "mem 0xFFFF"))
+            assert app.mem_start == 0xFFE0
+
+            # Jump via alias
+            app.on_input_submitted(Input.Submitted(inp, "mem vram"))
+            assert app.mem_start == 0x0200
+
+            app.on_input_submitted(Input.Submitted(inp, "mem stack"))
+            assert app.mem_start == (cpu.sp & ~0x1F)
+
+            app.on_input_submitted(Input.Submitted(inp, "mem sram"))
+            assert app.mem_start == 0x0060
+
+            app.on_input_submitted(Input.Submitted(inp, "mem 0x0600"))
+            assert app.mem_start == 0x0600
+
+            # Set memory byte at high address
+            app.on_input_submitted(Input.Submitted(inp, "set 0xFFFF 0xEF"))
+            assert cpu.mem.ram[0xFFFF] == 0xEF
+
+            # Test scrolling bounds
+            app.mem_start = 0xFFC0
+            app.action_scroll_down()
+            assert app.mem_start == 0xFFE0
+            app.action_scroll_down()
+            assert app.mem_start == 0xFFE0  # Capped at 0xFFE0 (0xFFFF row)
+
+            app.mem_start = 0x0010
+            app.action_scroll_up()
+            assert app.mem_start == 0x0000
+            app.action_scroll_up()
+            assert app.mem_start == 0x0000  # Capped at 0x0000
+
+    asyncio.run(_test())
diff --git a/tests/test_ui_components.py b/tests/test_ui_components.py
deleted file mode 100644
index 73a7c4c..0000000
--- a/tests/test_ui_components.py
+++ /dev/null
@@ -1,560 +0,0 @@
-"""Test cases for UI-related code (cli.py and visualizer.py).
-
-Following best practices for testing UI code:
-1. Separate logic from UI rendering
-2. Mock/patch UI library functions for fast tests
-3. Use headless rendering where applicable
-4. Keep tests simple and fast
-"""
-
-import io
-from unittest.mock import Mock, patch
-
-import pytest
-
-from tiny8 import CPU, assemble
-
-
-class TestCLILogic:
-    """Test CLI logic functions without actual terminal rendering."""
-
-    def test_view_state_initialization(self):
-        """Test ViewState dataclass initialization."""
-        from tiny8.cli import ViewState
-
-        state = ViewState()
-        assert state.step_idx == 0
-        assert state.scroll_offset == 0
-        assert not state.playing
-        assert state.delay == 0.15
-        assert state.show_all_regs
-        assert not state.show_all_mem
-        assert not state.command_mode
-        assert state.command_buffer == ""
-        assert state.marks == {}
-        assert state.status_msg == ""
-
-    def test_view_state_custom_values(self):
-        """Test ViewState with custom values."""
-        from tiny8.cli import ViewState
-
-        state = ViewState(
-            step_idx=5,
-            scroll_offset=10,
-            playing=True,
-            delay=0.5,
-            show_all_regs=False,
-        )
-        assert state.step_idx == 5
-        assert state.scroll_offset == 10
-        assert state.playing
-        assert state.delay == 0.5
-        assert not state.show_all_regs
-
-    def test_key_context_initialization(self):
-        """Test KeyContext dataclass initialization."""
-        from tiny8.cli import KeyContext, ViewState
-
-        cpu = CPU()
-        state = ViewState()
-        mock_scr = Mock()
-        traces = []
-
-        ctx = KeyContext(
-            state=state,
-            scr=mock_scr,
-            traces=traces,
-            cpu=cpu,
-            mem_addr_start=0x60,
-            mem_addr_end=0x7F,
-            source_lines=None,
-            n=0,
-        )
-
-        assert ctx.state == state
-        assert ctx.traces == traces
-        assert ctx.cpu == cpu
-        assert ctx.mem_addr_start == 0x60
-        assert ctx.mem_addr_end == 0x7F
-
-    def test_key_context_set_status(self):
-        """Test KeyContext status message setting."""
-        from tiny8.cli import KeyContext, ViewState
-
-        state = ViewState()
-        ctx = KeyContext(
-            state=state,
-            scr=Mock(),
-            traces=[],
-            cpu=CPU(),
-            mem_addr_start=0,
-            mem_addr_end=0,
-            source_lines=None,
-            n=0,
-        )
-
-        ctx.set_status("Test message")
-        assert ctx.state.status_msg == "Test message"
-        assert ctx.state.status_time > 0
-
-    def test_key_handler_decorator(self):
-        """Test key handler registration decorator."""
-        from tiny8.cli import _key_handlers, key_handler
-
-        original_handlers = _key_handlers.copy()
-        _key_handlers.clear()
-
-        @key_handler(ord("t"), ord("T"))
-        def test_handler(ctx):
-            return "test_result"
-
-        assert ord("t") in _key_handlers
-        assert ord("T") in _key_handlers
-        assert _key_handlers[ord("t")] == test_handler
-
-        _key_handlers.clear()
-        _key_handlers.update(original_handlers)
-
-
-class TestCLIFunctionsMocked:
-    """Test CLI functions with mocked curses."""
-
-    @patch("tiny8.cli.curses")
-    def test_run_cli_with_mock(self, mock_curses):
-        """Test run_cli with mocked curses."""
-        from tiny8.cli import run_cli
-
-        mock_curses.wrapper.return_value = None
-
-        cpu = CPU()
-        asm = assemble("ldi r16, 42")
-        cpu.load_program(asm)
-        cpu.run()
-
-        try:
-            with patch("tiny8.cli.curses.wrapper") as mock_wrapper:
-                mock_wrapper.return_value = None
-                assert callable(run_cli)
-        except Exception:
-            pass
-
-    def test_parse_go_to_step_logic(self):
-        """Test logic for parsing step numbers without UI."""
-        test_cases = [
-            ("10", 10),
-            ("0", 0),
-            ("999", 999),
-        ]
-
-        for input_str, expected in test_cases:
-            try:
-                result = int(input_str)
-                assert result == expected
-            except ValueError:
-                assert False, f"Should parse {input_str}"
-
-    def test_mark_name_validation(self):
-        """Test mark name validation logic."""
-        valid_marks = ["a", "b", "z", "A", "Z"]
-        for mark in valid_marks:
-            assert len(mark) == 1
-            assert mark.isalpha()
-
-        invalid_marks = ["1", "!", "", "ab"]
-        for mark in invalid_marks:
-            assert not (len(mark) == 1 and mark.isalpha())
-
-
-class TestVisualizerLogic:
-    """Test Visualizer logic with mocked matplotlib."""
-
-    def test_visualizer_initialization(self):
-        """Test Visualizer initialization."""
-        from tiny8.visualizer import Visualizer
-
-        cpu = CPU()
-        viz = Visualizer(cpu)
-        assert viz.cpu == cpu
-
-    @patch("tiny8.visualizer.plt")
-    @patch("tiny8.visualizer.animation")
-    def test_animate_execution_mock(self, mock_animation, mock_plt):
-        """Test animate_execution with mocked matplotlib."""
-        from tiny8.visualizer import Visualizer
-
-        cpu = CPU()
-        asm = assemble("""
-            ldi r16, 10
-            ldi r17, 20
-            add r16, r17
-        """)
-        cpu.load_program(asm)
-        cpu.run()
-
-        viz = Visualizer(cpu)
-
-        mock_fig = Mock()
-        mock_plt.subplots.return_value = (mock_fig, [Mock(), Mock(), Mock()])
-        mock_animation.FuncAnimation.return_value = Mock()
-
-        try:
-            viz.animate_execution(
-                mem_addr_start=0x60,
-                mem_addr_end=0x6F,
-                interval=100,
-                plot_every=1,
-            )
-        except Exception:
-            pass
-
-    def test_visualizer_data_preparation(self):
-        """Test data preparation logic for visualization."""
-        import numpy as np
-
-        from tiny8.visualizer import Visualizer
-
-        cpu = CPU()
-        asm = assemble("""
-            ldi r16, 5
-            ldi r17, 3
-            add r16, r17
-        """)
-        cpu.load_program(asm)
-        cpu.run()
-
-        _ = Visualizer(cpu)
-        num_steps = len(cpu.step_trace)
-
-        sreg_mat = np.zeros((8, num_steps))
-        reg_mat = np.zeros((32, num_steps))
-
-        assert sreg_mat.shape == (8, num_steps)
-        assert reg_mat.shape == (32, num_steps)
-        assert num_steps > 0
-
-        for idx, entry in enumerate(cpu.step_trace):
-            sreg = entry.get("sreg", 0)
-            regs = entry.get("regs", [0] * 32)
-
-            for bit in range(8):
-                sreg_mat[bit, idx] = (sreg >> bit) & 1
-
-            for reg_idx in range(32):
-                reg_mat[reg_idx, idx] = regs[reg_idx]
-
-        assert np.any(reg_mat)
-
-
-class TestVisualizerHeadless:
-    """Test Visualizer with headless matplotlib backend."""
-
-    def test_visualizer_headless_rendering(self):
-        """Test Visualizer with Agg backend (headless)."""
-        import matplotlib
-
-        matplotlib.use("Agg")
-
-        import matplotlib.pyplot as plt
-
-        from tiny8.visualizer import Visualizer
-
-        cpu = CPU()
-        asm = assemble("""
-            ldi r16, 10
-            inc r16
-            inc r16
-        """)
-        cpu.load_program(asm)
-        cpu.run()
-
-        _ = Visualizer(cpu)
-
-        try:
-            fig, axes = plt.subplots(3, 1, figsize=(10, 8))
-            assert len(axes) == 3
-            plt.close(fig)
-        except Exception:
-            pytest.skip("Matplotlib not available or headless mode failed")
-
-    def test_plot_generation_without_save(self, tmp_path):
-        """Test that plotting logic works without saving file."""
-        import matplotlib
-
-        matplotlib.use("Agg")
-
-        import matplotlib.pyplot as plt
-
-        data = [1, 2, 3, 4, 5]
-        plt.figure()
-        plt.plot(data)
-        plt.close()
-
-
-class TestCLIHelperFunctions:
-    """Test CLI helper functions that don't require curses."""
-
-    def test_format_register_name(self):
-        """Test register name formatting logic."""
-        for i in range(32):
-            reg_name = f"R{i}"
-            assert reg_name.startswith("R")
-            assert reg_name[1:].isdigit()
-
-    def test_format_hex_value(self):
-        """Test hex value formatting logic."""
-        test_values = [0x00, 0xFF, 0x42, 0xAB]
-        for val in test_values:
-            hex_str = f"0x{val:02X}"
-            assert hex_str.startswith("0x")
-            assert len(hex_str) == 4
-
-    def test_format_binary_value(self):
-        """Test binary value formatting logic."""
-        test_values = [0b00000000, 0b11111111, 0b10101010]
-        for val in test_values:
-            bin_str = f"{val:08b}"
-            assert len(bin_str) == 8
-            assert all(c in "01" for c in bin_str)
-
-    def test_memory_range_validation(self):
-        """Test memory range validation logic."""
-        test_cases = [
-            (0x00, 0xFF, True),
-            (0x60, 0x7F, True),
-            (0x100, 0xFF, False),  # Invalid (start > end)
-            (-1, 0x10, False),  # Invalid (negative)
-        ]
-
-        for start, end, should_be_valid in test_cases:
-            is_valid = 0 <= start <= end <= 0xFFFF
-            assert is_valid == should_be_valid
-
-
-class TestCLICommandParsing:
-    """Test command parsing logic without UI."""
-
-    def test_parse_goto_command(self):
-        """Test parsing goto command."""
-        commands = [
-            ("10", 10),
-            ("0", 0),
-            ("999", 999),
-        ]
-
-        for cmd, expected in commands:
-            if cmd.isdigit():
-                result = int(cmd)
-                assert result == expected
-
-    def test_parse_mark_command(self):
-        """Test parsing mark commands."""
-        valid_marks = ["ma", "mz", "mA", "mZ"]
-        for mark_cmd in valid_marks:
-            if mark_cmd.startswith("m") and len(mark_cmd) == 2:
-                letter = mark_cmd[1]
-                assert letter.isalpha()
-
-    def test_parse_search_command(self):
-        """Test parsing search commands."""
-        search_cmds = ["/test", "/abc", "/123"]
-        for cmd in search_cmds:
-            if cmd.startswith("/"):
-                pattern = cmd[1:]
-                assert len(pattern) > 0
-
-
-class TestVisualizerDataExtraction:
-    """Test data extraction logic from CPU traces."""
-
-    def test_extract_sreg_bits(self):
-        """Test SREG bit extraction logic."""
-        sreg_value = 0b10101010
-
-        bits = []
-        for i in range(8):
-            bit = (sreg_value >> i) & 1
-            bits.append(bit)
-
-        assert bits == [0, 1, 0, 1, 0, 1, 0, 1]
-
-    def test_extract_register_values(self):
-        """Test register value extraction from trace."""
-        cpu = CPU()
-        asm = assemble("""
-            ldi r16, 42
-            ldi r17, 100
-        """)
-        cpu.load_program(asm)
-        cpu.run()
-
-        assert len(cpu.step_trace) > 0
-        for entry in cpu.step_trace:
-            regs = entry.get("regs", [])
-            assert isinstance(regs, list)
-            if regs:
-                assert len(regs) == 32
-
-    def test_extract_memory_values(self):
-        """Test memory value extraction from trace."""
-        cpu = CPU()
-        asm = assemble("""
-            ldi r16, 42
-            inc r16
-        """)
-        cpu.load_program(asm)
-        cpu.run()
-
-        for entry in cpu.step_trace:
-            mem = entry.get("mem", {})
-            assert isinstance(mem, dict)
-
-
-class TestCLIStateManagement:
-    """Test CLI state management logic."""
-
-    def test_state_mark_management(self):
-        """Test mark storage and retrieval."""
-        from tiny8.cli import ViewState
-
-        state = ViewState()
-
-        state.marks["a"] = 10
-        state.marks["b"] = 20
-        state.marks["c"] = 30
-
-        assert state.marks["a"] == 10
-        assert state.marks["b"] == 20
-        assert state.marks["c"] == 30
-        assert len(state.marks) == 3
-
-    def test_state_command_buffer(self):
-        """Test command buffer management."""
-        from tiny8.cli import ViewState
-
-        state = ViewState()
-
-        state.command_buffer = "g"
-        state.command_buffer += "o"
-        state.command_buffer += "t"
-        state.command_buffer += "o"
-
-        assert state.command_buffer == "goto"
-
-        state.command_buffer = ""
-        assert state.command_buffer == ""
-
-    def test_state_scroll_boundaries(self):
-        """Test scroll offset boundary logic."""
-        from tiny8.cli import ViewState
-
-        state = ViewState()
-        max_scroll = 100
-
-        state.scroll_offset = 50
-        assert 0 <= state.scroll_offset <= max_scroll
-
-        state.scroll_offset = 0
-        assert state.scroll_offset >= 0
-
-        state.scroll_offset = max_scroll
-        assert state.scroll_offset <= max_scroll
-
-
-class TestVisualizerConfiguration:
-    """Test Visualizer configuration options."""
-
-    def test_visualizer_custom_parameters(self):
-        """Test Visualizer with custom parameters."""
-        from tiny8.visualizer import Visualizer
-
-        cpu = CPU()
-        asm = assemble("ldi r16, 42")
-        cpu.load_program(asm)
-        cpu.run()
-
-        _ = Visualizer(cpu)
-
-        config = {
-            "mem_addr_start": 0x100,
-            "mem_addr_end": 0x1FF,
-            "interval": 500,
-            "fps": 60,
-            "fontsize": 12,
-            "cmap": "viridis",
-            "plot_every": 2,
-        }
-
-        assert config["mem_addr_start"] < config["mem_addr_end"]
-        assert config["interval"] > 0
-        assert config["fps"] > 0
-        assert config["fontsize"] > 0
-        assert config["plot_every"] >= 1
-
-    def test_colormap_names(self):
-        """Test valid colormap names."""
-        valid_cmaps = ["viridis", "inferno", "plasma", "magma", "cividis"]
-
-        for cmap in valid_cmaps:
-            assert isinstance(cmap, str)
-            assert len(cmap) > 0
-
-
-class TestIntegrationMinimal:
-    """Minimal integration tests for UI components."""
-
-    def test_cli_with_cpu_trace(self):
-        """Test CLI can access CPU trace data."""
-        from tiny8.cli import ViewState
-
-        cpu = CPU()
-        asm = assemble("""
-            ldi r16, 10
-            ldi r17, 20
-            add r16, r17
-        """)
-        cpu.load_program(asm)
-        cpu.run()
-
-        state = ViewState()
-        traces = cpu.step_trace
-
-        assert state.step_idx >= 0
-        assert state.step_idx < len(traces) or len(traces) == 0
-
-        if traces:
-            state.step_idx = min(state.step_idx, len(traces) - 1)
-            assert 0 <= state.step_idx < len(traces)
-
-    def test_visualizer_with_cpu_trace(self):
-        """Test Visualizer can access CPU trace data."""
-        from tiny8.visualizer import Visualizer
-
-        cpu = CPU()
-        asm = assemble("""
-            ldi r16, 5
-            inc r16
-            inc r16
-        """)
-        cpu.load_program(asm)
-        cpu.run()
-
-        viz = Visualizer(cpu)
-
-        assert len(viz.cpu.step_trace) > 0
-        assert hasattr(viz.cpu, "step_trace")
-        assert viz.cpu == cpu
-
-    @patch("sys.stdout", new_callable=io.StringIO)
-    def test_cli_help_output(self, mock_stdout):
-        """Test CLI argument parsing help."""
-        import argparse
-
-        parser = argparse.ArgumentParser(description="Test CLI")
-        parser.add_argument("file", help="Assembly file")
-        parser.add_argument("--mem-start", type=int, default=0x60)
-        parser.add_argument("--mem-end", type=int, default=0x7F)
-
-        args = parser.parse_args(["test.asm", "--mem-start", "100", "--mem-end", "200"])
-        assert args.file == "test.asm"
-        assert args.mem_start == 100
-        assert args.mem_end == 200
diff --git a/tests/test_utils.py b/tests/test_utils.py
index 303522f..cffb0c6 100644
--- a/tests/test_utils.py
+++ b/tests/test_utils.py
@@ -15,18 +15,24 @@ def test_progress_bar_disabled(self):
         """Test progress bar when disabled."""
         pbar = ProgressBar(total=100, disable=True)
         pbar.update(50)
+        assert pbar.n == 0
+        assert pbar.disable is True
         pbar.close()
 
     def test_progress_bar_zero_total(self):
         """Test progress bar with None total."""
         pbar = ProgressBar(total=None, disable=True)
         pbar.update(10)
+        assert pbar.n == 0
+        assert pbar.total is None
         pbar.close()
 
     def test_progress_bar_with_context(self):
         """Test progress bar as context manager."""
         with ProgressBar(total=10, disable=True) as pbar:
             pbar.update(5)
+            assert pbar.n == 0
+            assert pbar.disable is True
 
 
 class TestProgressBarParameters:
@@ -36,18 +42,24 @@ def test_progress_bar_description(self):
         """Test progress bar with description."""
         pbar = ProgressBar(total=100, desc="Test", disable=True)
         pbar.update(10)
+        assert pbar.desc == "Test"
+        assert pbar.n == 0
         pbar.close()
 
     def test_progress_bar_ncols(self):
         """Test progress bar with custom width."""
         pbar = ProgressBar(total=100, ncols=50, disable=True)
         pbar.update(10)
+        assert pbar.ncols == 50
+        assert pbar.n == 0
         pbar.close()
 
     def test_progress_bar_mininterval(self):
         """Test progress bar with custom mininterval."""
         pbar = ProgressBar(total=100, mininterval=0.01, disable=True)
         pbar.update(10)
+        assert pbar.mininterval == 0.01
+        assert pbar.n == 0
         pbar.close()
 
 
@@ -60,6 +72,7 @@ def test_progress_bar_enabled_with_total(self):
         for i in range(10):
             pbar.update(1)
             time.sleep(0.001)
+        assert pbar.n == 10
         pbar.close()
 
     def test_progress_bar_enabled_no_total(self):
@@ -68,6 +81,7 @@ def test_progress_bar_enabled_no_total(self):
         for i in range(5):
             pbar.update(1)
             time.sleep(0.001)
+        assert pbar.n == 5
         pbar.close()
 
 
@@ -77,8 +91,11 @@ class TestProgressBarMethods:
     def test_progress_bar_set_description(self):
         """Test updating progress bar description."""
         pbar = ProgressBar(total=100, desc="Initial", disable=False, mininterval=0)
+        assert pbar.desc == "Initial"
         pbar.set_description("Updated")
+        assert pbar.desc == "Updated"
         pbar.update(10)
+        assert pbar.n == 10
         pbar.close()
 
     def test_progress_bar_reset(self):
@@ -134,12 +151,14 @@ def test_progress_bar_long_output(self):
             mininterval=0,
         )
         pbar.update(50)
+        assert pbar.n == 50
         pbar.close()
 
     def test_progress_bar_update_past_total(self):
         """Test updating progress bar past total."""
         pbar = ProgressBar(total=10, disable=False, mininterval=0)
         pbar.update(15)  # Update past total
+        assert pbar.n == 15
         pbar.close()
 
     def test_progress_bar_mininterval_skip_update(self):
@@ -150,6 +169,7 @@ def test_progress_bar_mininterval_skip_update(self):
         pbar.update(10)
         time.sleep(0.001)
         pbar.update(10)
+        assert pbar.n == 20
         pbar.close()
 
     def test_progress_bar_mininterval_with_completion(self):
@@ -158,6 +178,7 @@ def test_progress_bar_mininterval_with_completion(self):
         pbar.update(5)
         time.sleep(0.001)
         pbar.update(5)
+        assert pbar.n == 10
         pbar.close()
 
     def test_progress_bar_terminal_width_exception(self):
diff --git a/uv.lock b/uv.lock
index cfb0eb2..1de8dcf 100644
--- a/uv.lock
+++ b/uv.lock
@@ -1,6 +1,10 @@
 version = 1
-revision = 2
+revision = 3
 requires-python = ">=3.11"
+resolution-markers = [
+    "python_full_version >= '3.12'",
+    "python_full_version < '3.12'",
+]
 
 [[package]]
 name = "alabaster"
@@ -103,94 +107,21 @@ wheels = [
 ]
 
 [[package]]
-name = "colorama"
-version = "0.4.6"
+name = "click"
+version = "8.5.0"
 source = { registry = "https://pypi.org/simple" }
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+sdist = { url = "https://files.pythonhosted.org/packages/c7/0e/7fa0ef50764b67090eca4114772a2abf8b6148198475e54c660b97caeee6/click-8.5.0.tar.gz", hash = "sha256:ba0d2089de75ea0310e2dde03160e6ca10009947fb95a182f9b54021bb272e34", size = 382235, upload-time = "2026-08-26T13:33:14.56Z" }
 wheels = [
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+    { url = "https://files.pythonhosted.org/packages/58/50/6c0d534c5f134586a8e1ba4e330569e32f057e33372ae556463212fb4cd3/click-8.5.0-py3-none-any.whl", hash = "sha256:255bc9599cf7748b4b1a446ccc735421bd08a2ae529a8b88597d3de5664ee360", size = 125251, upload-time = "2026-08-26T13:33:12.928Z" },
 ]
 
 [[package]]
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-version = "1.3.3"
+name = "colorama"
+version = "0.4.6"
 source = { registry = "https://pypi.org/simple" }
-dependencies = [
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